2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/format/u_format.h"
28 #include "util/format/u_format_rgtc.h"
29 #include "util/format/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
35 #include "util/u_drm.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_batch_cache.h"
39 #include "freedreno_blitter.h"
40 #include "freedreno_fence.h"
41 #include "freedreno_screen.h"
42 #include "freedreno_surface.h"
43 #include "freedreno_context.h"
44 #include "freedreno_query_hw.h"
45 #include "freedreno_util.h"
47 #include "drm-uapi/drm_fourcc.h"
50 /* XXX this should go away, needed for 'struct winsys_handle' */
51 #include "state_tracker/drm_driver.h"
53 /* A private modifier for now, so we have a way to request tiled but not
54 * compressed. It would perhaps be good to get real modifiers for the
55 * tiled formats, but would probably need to do some work to figure out
56 * the layout(s) of the tiled modes, and whether they are the same
59 #define FD_FORMAT_MOD_QCOM_TILED fourcc_mod_code(QCOM, 0xffffffff)
62 * Go through the entire state and see if the resource is bound
63 * anywhere. If it is, mark the relevant state as dirty. This is
64 * called on realloc_bo to ensure the necessary state is re-
65 * emitted so the GPU looks at the new backing bo.
68 rebind_resource_in_ctx(struct fd_context
*ctx
, struct fd_resource
*rsc
)
70 struct pipe_resource
*prsc
= &rsc
->base
;
72 if (ctx
->rebind_resource
)
73 ctx
->rebind_resource(ctx
, rsc
);
76 if (rsc
->dirty
& FD_DIRTY_VTXBUF
) {
77 struct fd_vertexbuf_stateobj
*vb
= &ctx
->vtx
.vertexbuf
;
78 for (unsigned i
= 0; i
< vb
->count
&& !(ctx
->dirty
& FD_DIRTY_VTXBUF
); i
++) {
79 if (vb
->vb
[i
].buffer
.resource
== prsc
)
80 ctx
->dirty
|= FD_DIRTY_VTXBUF
;
84 const enum fd_dirty_3d_state per_stage_dirty
=
85 FD_DIRTY_CONST
| FD_DIRTY_TEX
| FD_DIRTY_IMAGE
| FD_DIRTY_SSBO
;
87 if (!(rsc
->dirty
& per_stage_dirty
))
90 /* per-shader-stage resources: */
91 for (unsigned stage
= 0; stage
< PIPE_SHADER_TYPES
; stage
++) {
92 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
93 * cmdstream rather than by pointer..
95 if ((rsc
->dirty
& FD_DIRTY_CONST
) &&
96 !(ctx
->dirty_shader
[stage
] & FD_DIRTY_CONST
)) {
97 struct fd_constbuf_stateobj
*cb
= &ctx
->constbuf
[stage
];
98 const unsigned num_ubos
= util_last_bit(cb
->enabled_mask
);
99 for (unsigned i
= 1; i
< num_ubos
; i
++) {
100 if (cb
->cb
[i
].buffer
== prsc
) {
101 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_CONST
;
102 ctx
->dirty
|= FD_DIRTY_CONST
;
109 if ((rsc
->dirty
& FD_DIRTY_TEX
) &&
110 !(ctx
->dirty_shader
[stage
] & FD_DIRTY_TEX
)) {
111 struct fd_texture_stateobj
*tex
= &ctx
->tex
[stage
];
112 for (unsigned i
= 0; i
< tex
->num_textures
; i
++) {
113 if (tex
->textures
[i
] && (tex
->textures
[i
]->texture
== prsc
)) {
114 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_TEX
;
115 ctx
->dirty
|= FD_DIRTY_TEX
;
122 if ((rsc
->dirty
& FD_DIRTY_IMAGE
) &&
123 !(ctx
->dirty_shader
[stage
] & FD_DIRTY_IMAGE
)) {
124 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[stage
];
125 const unsigned num_images
= util_last_bit(si
->enabled_mask
);
126 for (unsigned i
= 0; i
< num_images
; i
++) {
127 if (si
->si
[i
].resource
== prsc
) {
128 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_IMAGE
;
129 ctx
->dirty
|= FD_DIRTY_IMAGE
;
136 if ((rsc
->dirty
& FD_DIRTY_SSBO
) &&
137 !(ctx
->dirty_shader
[stage
] & FD_DIRTY_SSBO
)) {
138 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[stage
];
139 const unsigned num_ssbos
= util_last_bit(sb
->enabled_mask
);
140 for (unsigned i
= 0; i
< num_ssbos
; i
++) {
141 if (sb
->sb
[i
].buffer
== prsc
) {
142 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_SSBO
;
143 ctx
->dirty
|= FD_DIRTY_SSBO
;
152 rebind_resource(struct fd_resource
*rsc
)
154 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
156 mtx_lock(&screen
->lock
);
157 fd_resource_lock(rsc
);
160 list_for_each_entry (struct fd_context
, ctx
, &screen
->context_list
, node
)
161 rebind_resource_in_ctx(ctx
, rsc
);
163 fd_resource_unlock(rsc
);
164 mtx_unlock(&screen
->lock
);
168 realloc_bo(struct fd_resource
*rsc
, uint32_t size
)
170 struct pipe_resource
*prsc
= &rsc
->base
;
171 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
172 uint32_t flags
= DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
173 DRM_FREEDRENO_GEM_TYPE_KMEM
|
174 COND(prsc
->bind
& PIPE_BIND_SCANOUT
, DRM_FREEDRENO_GEM_SCANOUT
);
175 /* TODO other flags? */
177 /* if we start using things other than write-combine,
178 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
184 rsc
->bo
= fd_bo_new(screen
->dev
, size
, flags
, "%ux%ux%u@%u:%x",
185 prsc
->width0
, prsc
->height0
, prsc
->depth0
, rsc
->layout
.cpp
, prsc
->bind
);
187 /* Zero out the UBWC area on allocation. This fixes intermittent failures
188 * with UBWC, which I suspect are due to the HW having a hard time
189 * interpreting arbitrary values populating the flags buffer when the BO
190 * was recycled through the bo cache (instead of fresh allocations from
191 * the kernel, which are zeroed). sleep(1) in this spot didn't work
192 * around the issue, but any memset value seems to.
194 if (rsc
->layout
.ubwc
) {
195 void *buf
= fd_bo_map(rsc
->bo
);
196 memset(buf
, 0, rsc
->layout
.slices
[0].offset
);
199 rsc
->seqno
= p_atomic_inc_return(&screen
->rsc_seqno
);
200 util_range_set_empty(&rsc
->valid_buffer_range
);
201 fd_bc_invalidate_resource(rsc
, true);
205 do_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*blit
, bool fallback
)
207 struct pipe_context
*pctx
= &ctx
->base
;
209 /* TODO size threshold too?? */
210 if (fallback
|| !fd_blit(pctx
, blit
)) {
211 /* do blit on cpu: */
212 util_resource_copy_region(pctx
,
213 blit
->dst
.resource
, blit
->dst
.level
, blit
->dst
.box
.x
,
214 blit
->dst
.box
.y
, blit
->dst
.box
.z
,
215 blit
->src
.resource
, blit
->src
.level
, &blit
->src
.box
);
220 * @rsc: the resource to shadow
221 * @level: the level to discard (if box != NULL, otherwise ignored)
222 * @box: the box to discard (or NULL if none)
223 * @modifier: the modifier for the new buffer state
226 fd_try_shadow_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
,
227 unsigned level
, const struct pipe_box
*box
, uint64_t modifier
)
229 struct pipe_context
*pctx
= &ctx
->base
;
230 struct pipe_resource
*prsc
= &rsc
->base
;
231 bool fallback
= false;
236 /* TODO: somehow munge dimensions and format to copy unsupported
237 * render target format to something that is supported?
239 if (!pctx
->screen
->is_format_supported(pctx
->screen
,
240 prsc
->format
, prsc
->target
, prsc
->nr_samples
,
241 prsc
->nr_storage_samples
,
242 PIPE_BIND_RENDER_TARGET
))
245 /* do shadowing back-blits on the cpu for buffers: */
246 if (prsc
->target
== PIPE_BUFFER
)
249 bool discard_whole_level
= box
&& util_texrange_covers_whole_level(prsc
, level
,
250 box
->x
, box
->y
, box
->z
, box
->width
, box
->height
, box
->depth
);
252 /* TODO need to be more clever about current level */
253 if ((prsc
->target
>= PIPE_TEXTURE_2D
) && box
&& !discard_whole_level
)
256 struct pipe_resource
*pshadow
=
257 pctx
->screen
->resource_create_with_modifiers(pctx
->screen
,
263 assert(!ctx
->in_shadow
);
264 ctx
->in_shadow
= true;
266 /* get rid of any references that batch-cache might have to us (which
267 * should empty/destroy rsc->batches hashset)
269 fd_bc_invalidate_resource(rsc
, false);
270 rebind_resource(rsc
);
272 mtx_lock(&ctx
->screen
->lock
);
274 /* Swap the backing bo's, so shadow becomes the old buffer,
275 * blit from shadow to new buffer. From here on out, we
278 * Note that we need to do it in this order, otherwise if
279 * we go down cpu blit path, the recursive transfer_map()
280 * sees the wrong status..
282 struct fd_resource
*shadow
= fd_resource(pshadow
);
284 DBG("shadow: %p (%d) -> %p (%d)\n", rsc
, rsc
->base
.reference
.count
,
285 shadow
, shadow
->base
.reference
.count
);
287 /* TODO valid_buffer_range?? */
288 swap(rsc
->bo
, shadow
->bo
);
289 swap(rsc
->write_batch
, shadow
->write_batch
);
290 swap(rsc
->layout
, shadow
->layout
);
291 rsc
->seqno
= p_atomic_inc_return(&ctx
->screen
->rsc_seqno
);
293 /* at this point, the newly created shadow buffer is not referenced
294 * by any batches, but the existing rsc (probably) is. We need to
295 * transfer those references over:
297 debug_assert(shadow
->batch_mask
== 0);
298 struct fd_batch
*batch
;
299 foreach_batch(batch
, &ctx
->screen
->batch_cache
, rsc
->batch_mask
) {
300 struct set_entry
*entry
= _mesa_set_search(batch
->resources
, rsc
);
301 _mesa_set_remove(batch
->resources
, entry
);
302 _mesa_set_add(batch
->resources
, shadow
);
304 swap(rsc
->batch_mask
, shadow
->batch_mask
);
306 mtx_unlock(&ctx
->screen
->lock
);
308 struct pipe_blit_info blit
= {};
309 blit
.dst
.resource
= prsc
;
310 blit
.dst
.format
= prsc
->format
;
311 blit
.src
.resource
= pshadow
;
312 blit
.src
.format
= pshadow
->format
;
313 blit
.mask
= util_format_get_mask(prsc
->format
);
314 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
316 #define set_box(field, val) do { \
317 blit.dst.field = (val); \
318 blit.src.field = (val); \
321 /* blit the other levels in their entirety: */
322 for (unsigned l
= 0; l
<= prsc
->last_level
; l
++) {
323 if (box
&& l
== level
)
326 /* just blit whole level: */
328 set_box(box
.width
, u_minify(prsc
->width0
, l
));
329 set_box(box
.height
, u_minify(prsc
->height0
, l
));
330 set_box(box
.depth
, u_minify(prsc
->depth0
, l
));
332 for (int i
= 0; i
< prsc
->array_size
; i
++) {
334 do_blit(ctx
, &blit
, fallback
);
338 /* deal w/ current level specially, since we might need to split
339 * it up into a couple blits:
341 if (box
&& !discard_whole_level
) {
342 set_box(level
, level
);
344 switch (prsc
->target
) {
346 case PIPE_TEXTURE_1D
:
349 set_box(box
.height
, 1);
350 set_box(box
.depth
, 1);
354 set_box(box
.width
, box
->x
);
356 do_blit(ctx
, &blit
, fallback
);
358 if ((box
->x
+ box
->width
) < u_minify(prsc
->width0
, level
)) {
359 set_box(box
.x
, box
->x
+ box
->width
);
360 set_box(box
.width
, u_minify(prsc
->width0
, level
) - (box
->x
+ box
->width
));
362 do_blit(ctx
, &blit
, fallback
);
365 case PIPE_TEXTURE_2D
:
372 ctx
->in_shadow
= false;
374 pipe_resource_reference(&pshadow
, NULL
);
380 * Uncompress an UBWC compressed buffer "in place". This works basically
381 * like resource shadowing, creating a new resource, and doing an uncompress
382 * blit, and swapping the state between shadow and original resource so it
383 * appears to the state tracker as if nothing changed.
386 fd_resource_uncompress(struct fd_context
*ctx
, struct fd_resource
*rsc
)
389 fd_try_shadow_resource(ctx
, rsc
, 0, NULL
, FD_FORMAT_MOD_QCOM_TILED
);
391 /* shadow should not fail in any cases where we need to uncompress: */
392 debug_assert(success
);
395 static struct fd_resource
*
396 fd_alloc_staging(struct fd_context
*ctx
, struct fd_resource
*rsc
,
397 unsigned level
, const struct pipe_box
*box
)
399 struct pipe_context
*pctx
= &ctx
->base
;
400 struct pipe_resource tmpl
= rsc
->base
;
402 tmpl
.width0
= box
->width
;
403 tmpl
.height0
= box
->height
;
404 /* for array textures, box->depth is the array_size, otherwise
405 * for 3d textures, it is the depth:
407 if (tmpl
.array_size
> 1) {
408 if (tmpl
.target
== PIPE_TEXTURE_CUBE
)
409 tmpl
.target
= PIPE_TEXTURE_2D_ARRAY
;
410 tmpl
.array_size
= box
->depth
;
414 tmpl
.depth0
= box
->depth
;
417 tmpl
.bind
|= PIPE_BIND_LINEAR
;
419 struct pipe_resource
*pstaging
=
420 pctx
->screen
->resource_create(pctx
->screen
, &tmpl
);
424 return fd_resource(pstaging
);
428 fd_blit_from_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
430 struct pipe_resource
*dst
= trans
->base
.resource
;
431 struct pipe_blit_info blit
= {};
433 blit
.dst
.resource
= dst
;
434 blit
.dst
.format
= dst
->format
;
435 blit
.dst
.level
= trans
->base
.level
;
436 blit
.dst
.box
= trans
->base
.box
;
437 blit
.src
.resource
= trans
->staging_prsc
;
438 blit
.src
.format
= trans
->staging_prsc
->format
;
440 blit
.src
.box
= trans
->staging_box
;
441 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
442 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
444 do_blit(ctx
, &blit
, false);
448 fd_blit_to_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
450 struct pipe_resource
*src
= trans
->base
.resource
;
451 struct pipe_blit_info blit
= {};
453 blit
.src
.resource
= src
;
454 blit
.src
.format
= src
->format
;
455 blit
.src
.level
= trans
->base
.level
;
456 blit
.src
.box
= trans
->base
.box
;
457 blit
.dst
.resource
= trans
->staging_prsc
;
458 blit
.dst
.format
= trans
->staging_prsc
->format
;
460 blit
.dst
.box
= trans
->staging_box
;
461 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
462 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
464 do_blit(ctx
, &blit
, false);
467 static void fd_resource_transfer_flush_region(struct pipe_context
*pctx
,
468 struct pipe_transfer
*ptrans
,
469 const struct pipe_box
*box
)
471 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
473 if (ptrans
->resource
->target
== PIPE_BUFFER
)
474 util_range_add(&rsc
->base
, &rsc
->valid_buffer_range
,
475 ptrans
->box
.x
+ box
->x
,
476 ptrans
->box
.x
+ box
->x
+ box
->width
);
480 flush_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
, unsigned usage
)
482 struct fd_batch
*write_batch
= NULL
;
484 mtx_lock(&ctx
->screen
->lock
);
485 fd_batch_reference_locked(&write_batch
, rsc
->write_batch
);
486 mtx_unlock(&ctx
->screen
->lock
);
488 if (usage
& PIPE_TRANSFER_WRITE
) {
489 struct fd_batch
*batch
, *batches
[32] = {};
492 /* This is a bit awkward, probably a fd_batch_flush_locked()
493 * would make things simpler.. but we need to hold the lock
494 * to iterate the batches which reference this resource. So
495 * we must first grab references under a lock, then flush.
497 mtx_lock(&ctx
->screen
->lock
);
498 batch_mask
= rsc
->batch_mask
;
499 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
500 fd_batch_reference_locked(&batches
[batch
->idx
], batch
);
501 mtx_unlock(&ctx
->screen
->lock
);
503 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
504 fd_batch_flush(batch
);
506 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
) {
507 fd_batch_reference(&batches
[batch
->idx
], NULL
);
509 assert(rsc
->batch_mask
== 0);
510 } else if (write_batch
) {
511 fd_batch_flush(write_batch
);
514 fd_batch_reference(&write_batch
, NULL
);
516 assert(!rsc
->write_batch
);
520 fd_flush_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
522 flush_resource(fd_context(pctx
), fd_resource(prsc
), PIPE_TRANSFER_READ
);
526 fd_resource_transfer_unmap(struct pipe_context
*pctx
,
527 struct pipe_transfer
*ptrans
)
529 struct fd_context
*ctx
= fd_context(pctx
);
530 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
531 struct fd_transfer
*trans
= fd_transfer(ptrans
);
533 if (trans
->staging_prsc
) {
534 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
)
535 fd_blit_from_staging(ctx
, trans
);
536 pipe_resource_reference(&trans
->staging_prsc
, NULL
);
539 if (!(ptrans
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
540 fd_bo_cpu_fini(rsc
->bo
);
543 util_range_add(&rsc
->base
, &rsc
->valid_buffer_range
,
545 ptrans
->box
.x
+ ptrans
->box
.width
);
547 pipe_resource_reference(&ptrans
->resource
, NULL
);
548 slab_free(&ctx
->transfer_pool
, ptrans
);
552 fd_resource_transfer_map(struct pipe_context
*pctx
,
553 struct pipe_resource
*prsc
,
554 unsigned level
, unsigned usage
,
555 const struct pipe_box
*box
,
556 struct pipe_transfer
**pptrans
)
558 struct fd_context
*ctx
= fd_context(pctx
);
559 struct fd_resource
*rsc
= fd_resource(prsc
);
560 struct fdl_slice
*slice
= fd_resource_slice(rsc
, level
);
561 struct fd_transfer
*trans
;
562 struct pipe_transfer
*ptrans
;
563 enum pipe_format format
= prsc
->format
;
569 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc
, level
, usage
,
570 box
->width
, box
->height
, box
->x
, box
->y
);
572 ptrans
= slab_alloc(&ctx
->transfer_pool
);
576 /* slab_alloc_st() doesn't zero: */
577 trans
= fd_transfer(ptrans
);
578 memset(trans
, 0, sizeof(*trans
));
580 pipe_resource_reference(&ptrans
->resource
, prsc
);
581 ptrans
->level
= level
;
582 ptrans
->usage
= usage
;
584 ptrans
->stride
= slice
->pitch
;
585 ptrans
->layer_stride
= fd_resource_layer_stride(rsc
, level
);
587 /* we always need a staging texture for tiled buffers:
589 * TODO we might sometimes want to *also* shadow the resource to avoid
590 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
593 if (rsc
->layout
.tile_mode
) {
594 struct fd_resource
*staging_rsc
;
596 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
598 struct fdl_slice
*staging_slice
=
599 fd_resource_slice(staging_rsc
, 0);
600 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
601 trans
->staging_prsc
= &staging_rsc
->base
;
602 trans
->base
.stride
= staging_slice
->pitch
;
603 trans
->base
.layer_stride
= fd_resource_layer_stride(staging_rsc
, 0);
604 trans
->staging_box
= *box
;
605 trans
->staging_box
.x
= 0;
606 trans
->staging_box
.y
= 0;
607 trans
->staging_box
.z
= 0;
609 if (usage
& PIPE_TRANSFER_READ
) {
610 fd_blit_to_staging(ctx
, trans
);
612 fd_bo_cpu_prep(staging_rsc
->bo
, ctx
->pipe
,
613 DRM_FREEDRENO_PREP_READ
);
616 buf
= fd_bo_map(staging_rsc
->bo
);
621 ctx
->stats
.staging_uploads
++;
627 if (ctx
->in_shadow
&& !(usage
& PIPE_TRANSFER_READ
))
628 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
630 if (usage
& PIPE_TRANSFER_READ
)
631 op
|= DRM_FREEDRENO_PREP_READ
;
633 if (usage
& PIPE_TRANSFER_WRITE
)
634 op
|= DRM_FREEDRENO_PREP_WRITE
;
636 bool needs_flush
= pending(rsc
, !!(usage
& PIPE_TRANSFER_WRITE
));
638 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
639 if (needs_flush
|| fd_resource_busy(rsc
, op
)) {
640 rebind_resource(rsc
);
641 realloc_bo(rsc
, fd_bo_size(rsc
->bo
));
643 } else if ((usage
& PIPE_TRANSFER_WRITE
) &&
644 prsc
->target
== PIPE_BUFFER
&&
645 !util_ranges_intersect(&rsc
->valid_buffer_range
,
646 box
->x
, box
->x
+ box
->width
)) {
647 /* We are trying to write to a previously uninitialized range. No need
650 } else if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
651 struct fd_batch
*write_batch
= NULL
;
653 /* hold a reference, so it doesn't disappear under us: */
654 fd_context_lock(ctx
);
655 fd_batch_reference_locked(&write_batch
, rsc
->write_batch
);
656 fd_context_unlock(ctx
);
658 if ((usage
& PIPE_TRANSFER_WRITE
) && write_batch
&&
659 write_batch
->back_blit
) {
660 /* if only thing pending is a back-blit, we can discard it: */
661 fd_batch_reset(write_batch
);
664 /* If the GPU is writing to the resource, or if it is reading from the
665 * resource and we're trying to write to it, flush the renders.
667 bool busy
= needs_flush
|| fd_resource_busy(rsc
, op
);
669 /* if we need to flush/stall, see if we can make a shadow buffer
672 * TODO we could go down this path !reorder && !busy_for_read
673 * ie. we only *don't* want to go down this path if the blit
674 * will trigger a flush!
676 if (ctx
->screen
->reorder
&& busy
&& !(usage
& PIPE_TRANSFER_READ
) &&
677 (usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
678 /* try shadowing only if it avoids a flush, otherwise staging would
681 if (needs_flush
&& fd_try_shadow_resource(ctx
, rsc
, level
,
682 box
, DRM_FORMAT_MOD_LINEAR
)) {
683 needs_flush
= busy
= false;
684 ctx
->stats
.shadow_uploads
++;
686 struct fd_resource
*staging_rsc
;
689 flush_resource(ctx
, rsc
, usage
);
693 /* in this case, we don't need to shadow the whole resource,
694 * since any draw that references the previous contents has
695 * already had rendering flushed for all tiles. So we can
696 * use a staging buffer to do the upload.
698 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
700 struct fdl_slice
*staging_slice
=
701 fd_resource_slice(staging_rsc
, 0);
702 trans
->staging_prsc
= &staging_rsc
->base
;
703 trans
->base
.stride
= staging_slice
->pitch
;
704 trans
->base
.layer_stride
=
705 fd_resource_layer_stride(staging_rsc
, 0);
706 trans
->staging_box
= *box
;
707 trans
->staging_box
.x
= 0;
708 trans
->staging_box
.y
= 0;
709 trans
->staging_box
.z
= 0;
710 buf
= fd_bo_map(staging_rsc
->bo
);
715 fd_batch_reference(&write_batch
, NULL
);
717 ctx
->stats
.staging_uploads
++;
725 flush_resource(ctx
, rsc
, usage
);
729 fd_batch_reference(&write_batch
, NULL
);
731 /* The GPU keeps track of how the various bo's are being used, and
732 * will wait if necessary for the proper operation to have
736 ret
= fd_bo_cpu_prep(rsc
->bo
, ctx
->pipe
, op
);
742 buf
= fd_bo_map(rsc
->bo
);
744 box
->y
/ util_format_get_blockheight(format
) * ptrans
->stride
+
745 box
->x
/ util_format_get_blockwidth(format
) * rsc
->layout
.cpp
+
746 fd_resource_offset(rsc
, level
, box
->z
);
748 if (usage
& PIPE_TRANSFER_WRITE
)
756 fd_resource_transfer_unmap(pctx
, ptrans
);
761 fd_resource_destroy(struct pipe_screen
*pscreen
,
762 struct pipe_resource
*prsc
)
764 struct fd_resource
*rsc
= fd_resource(prsc
);
765 fd_bc_invalidate_resource(rsc
, true);
769 renderonly_scanout_destroy(rsc
->scanout
, fd_screen(pscreen
)->ro
);
771 util_range_destroy(&rsc
->valid_buffer_range
);
772 simple_mtx_destroy(&rsc
->lock
);
777 fd_resource_modifier(struct fd_resource
*rsc
)
779 if (!rsc
->layout
.tile_mode
)
780 return DRM_FORMAT_MOD_LINEAR
;
782 if (rsc
->layout
.ubwc_layer_size
)
783 return DRM_FORMAT_MOD_QCOM_COMPRESSED
;
785 /* TODO invent a modifier for tiled but not UBWC buffers: */
786 return DRM_FORMAT_MOD_INVALID
;
790 fd_resource_get_handle(struct pipe_screen
*pscreen
,
791 struct pipe_context
*pctx
,
792 struct pipe_resource
*prsc
,
793 struct winsys_handle
*handle
,
796 struct fd_resource
*rsc
= fd_resource(prsc
);
798 handle
->modifier
= fd_resource_modifier(rsc
);
800 return fd_screen_bo_get_handle(pscreen
, rsc
->bo
, rsc
->scanout
,
801 fd_resource_slice(rsc
, 0)->pitch
, handle
);
805 setup_slices(struct fd_resource
*rsc
, uint32_t alignment
, enum pipe_format format
)
807 struct pipe_resource
*prsc
= &rsc
->base
;
808 struct fd_screen
*screen
= fd_screen(prsc
->screen
);
809 enum util_format_layout layout
= util_format_description(format
)->layout
;
810 uint32_t pitchalign
= screen
->gmem_alignw
;
811 uint32_t level
, size
= 0;
812 uint32_t width
= prsc
->width0
;
813 uint32_t height
= prsc
->height0
;
814 uint32_t depth
= prsc
->depth0
;
815 /* in layer_first layout, the level (slice) contains just one
816 * layer (since in fact the layer contains the slices)
818 uint32_t layers_in_level
= rsc
->layout
.layer_first
? 1 : prsc
->array_size
;
820 for (level
= 0; level
<= prsc
->last_level
; level
++) {
821 struct fdl_slice
*slice
= fd_resource_slice(rsc
, level
);
824 if (layout
== UTIL_FORMAT_LAYOUT_ASTC
)
825 width
= util_align_npot(width
, pitchalign
* util_format_get_blockwidth(format
));
827 width
= align(width
, pitchalign
);
828 slice
->pitch
= util_format_get_nblocksx(format
, width
) * rsc
->layout
.cpp
;
829 slice
->offset
= size
;
830 blocks
= util_format_get_nblocks(format
, width
, height
);
831 /* 1d array and 2d array textures must all have the same layer size
832 * for each miplevel on a3xx. 3d textures can have different layer
833 * sizes for high levels, but the hw auto-sizer is buggy (or at least
834 * different than what this code does), so as soon as the layer size
835 * range gets into range, we stop reducing it.
837 if (prsc
->target
== PIPE_TEXTURE_3D
&& (
839 (level
> 1 && fd_resource_slice(rsc
, level
- 1)->size0
> 0xf000)))
840 slice
->size0
= align(blocks
* rsc
->layout
.cpp
, alignment
);
841 else if (level
== 0 || rsc
->layout
.layer_first
|| alignment
== 1)
842 slice
->size0
= align(blocks
* rsc
->layout
.cpp
, alignment
);
844 slice
->size0
= fd_resource_slice(rsc
, level
- 1)->size0
;
846 size
+= slice
->size0
* depth
* layers_in_level
;
848 width
= u_minify(width
, 1);
849 height
= u_minify(height
, 1);
850 depth
= u_minify(depth
, 1);
857 slice_alignment(enum pipe_texture_target target
)
859 /* on a3xx, 2d array and 3d textures seem to want their
860 * layers aligned to page boundaries:
863 case PIPE_TEXTURE_3D
:
864 case PIPE_TEXTURE_1D_ARRAY
:
865 case PIPE_TEXTURE_2D_ARRAY
:
872 /* cross generation texture layout to plug in to screen->setup_slices()..
873 * replace with generation specific one as-needed.
875 * TODO for a4xx probably can extract out the a4xx specific logic int
876 * a small fd4_setup_slices() wrapper that sets up layer_first, and then
880 fd_setup_slices(struct fd_resource
*rsc
)
884 alignment
= slice_alignment(rsc
->base
.target
);
886 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
887 if (is_a4xx(screen
)) {
888 switch (rsc
->base
.target
) {
889 case PIPE_TEXTURE_3D
:
890 rsc
->layout
.layer_first
= false;
893 rsc
->layout
.layer_first
= true;
899 return setup_slices(rsc
, alignment
, rsc
->base
.format
);
902 /* special case to resize query buf after allocated.. */
904 fd_resource_resize(struct pipe_resource
*prsc
, uint32_t sz
)
906 struct fd_resource
*rsc
= fd_resource(prsc
);
908 debug_assert(prsc
->width0
== 0);
909 debug_assert(prsc
->target
== PIPE_BUFFER
);
910 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
913 realloc_bo(rsc
, fd_screen(prsc
->screen
)->setup_slices(rsc
));
917 fd_resource_layout_init(struct pipe_resource
*prsc
)
919 struct fd_resource
*rsc
= fd_resource(prsc
);
920 struct fdl_layout
*layout
= &rsc
->layout
;
922 layout
->width0
= prsc
->width0
;
923 layout
->height0
= prsc
->height0
;
924 layout
->depth0
= prsc
->depth0
;
926 layout
->cpp
= util_format_get_blocksize(prsc
->format
);
927 layout
->cpp
*= fd_resource_nr_samples(prsc
);
928 layout
->cpp_shift
= ffs(layout
->cpp
) - 1;
932 * Create a new texture object, using the given template info.
934 static struct pipe_resource
*
935 fd_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
936 const struct pipe_resource
*tmpl
,
937 const uint64_t *modifiers
, int count
)
939 struct fd_screen
*screen
= fd_screen(pscreen
);
940 struct fd_resource
*rsc
;
941 struct pipe_resource
*prsc
;
942 enum pipe_format format
= tmpl
->format
;
945 /* when using kmsro, scanout buffers are allocated on the display device
946 * create_with_modifiers() doesn't give us usage flags, so we have to
947 * assume that all calls with modifiers are scanout-possible
950 ((tmpl
->bind
& PIPE_BIND_SCANOUT
) ||
951 !(count
== 1 && modifiers
[0] == DRM_FORMAT_MOD_INVALID
))) {
952 struct pipe_resource scanout_templat
= *tmpl
;
953 struct renderonly_scanout
*scanout
;
954 struct winsys_handle handle
;
956 /* apply freedreno alignment requirement */
957 scanout_templat
.width0
= align(tmpl
->width0
, screen
->gmem_alignw
);
959 scanout
= renderonly_scanout_for_resource(&scanout_templat
,
960 screen
->ro
, &handle
);
964 renderonly_scanout_destroy(scanout
, screen
->ro
);
966 assert(handle
.type
== WINSYS_HANDLE_TYPE_FD
);
967 rsc
= fd_resource(pscreen
->resource_from_handle(pscreen
, tmpl
,
969 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
970 close(handle
.handle
);
977 rsc
= CALLOC_STRUCT(fd_resource
);
980 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
981 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc
,
982 tmpl
->target
, util_format_name(format
),
983 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
984 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
985 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
991 fd_resource_layout_init(prsc
);
994 (PIPE_BIND_SCANOUT | \
996 PIPE_BIND_DISPLAY_TARGET)
998 bool linear
= drm_find_modifier(DRM_FORMAT_MOD_LINEAR
, modifiers
, count
);
999 if (tmpl
->bind
& LINEAR
)
1002 if (fd_mesa_debug
& FD_DBG_NOTILE
)
1005 /* Normally, for non-shared buffers, allow buffer compression if
1006 * not shared, otherwise only allow if QCOM_COMPRESSED modifier
1009 * TODO we should probably also limit tiled in a similar way,
1010 * except we don't have a format modifier for tiled. (We probably
1013 bool allow_ubwc
= drm_find_modifier(DRM_FORMAT_MOD_INVALID
, modifiers
, count
);
1014 if (tmpl
->bind
& PIPE_BIND_SHARED
)
1015 allow_ubwc
= drm_find_modifier(DRM_FORMAT_MOD_QCOM_COMPRESSED
, modifiers
, count
);
1017 allow_ubwc
&= !(fd_mesa_debug
& FD_DBG_NOUBWC
);
1019 pipe_reference_init(&prsc
->reference
, 1);
1021 prsc
->screen
= pscreen
;
1023 if (screen
->tile_mode
&&
1024 (tmpl
->target
!= PIPE_BUFFER
) &&
1026 rsc
->layout
.tile_mode
= screen
->tile_mode(prsc
);
1029 util_range_init(&rsc
->valid_buffer_range
);
1031 simple_mtx_init(&rsc
->lock
, mtx_plain
);
1033 rsc
->internal_format
= format
;
1035 rsc
->layout
.ubwc
= rsc
->layout
.tile_mode
&& is_a6xx(screen
) && allow_ubwc
;
1037 if (prsc
->target
== PIPE_BUFFER
) {
1038 assert(prsc
->format
== PIPE_FORMAT_R8_UNORM
);
1039 size
= prsc
->width0
;
1040 fdl_layout_buffer(&rsc
->layout
, size
);
1042 size
= screen
->setup_slices(rsc
);
1045 /* special case for hw-query buffer, which we need to allocate before we
1049 /* note, semi-intention == instead of & */
1050 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
1054 /* Set the layer size if the (non-a6xx) backend hasn't done so. */
1055 if (rsc
->layout
.layer_first
&& !rsc
->layout
.layer_size
) {
1056 rsc
->layout
.layer_size
= align(size
, 4096);
1057 size
= rsc
->layout
.layer_size
* prsc
->array_size
;
1060 if (fd_mesa_debug
& FD_DBG_LAYOUT
)
1061 fdl_dump_layout(&rsc
->layout
);
1063 realloc_bo(rsc
, size
);
1069 fd_resource_destroy(pscreen
, prsc
);
1073 static struct pipe_resource
*
1074 fd_resource_create(struct pipe_screen
*pscreen
,
1075 const struct pipe_resource
*tmpl
)
1077 const uint64_t mod
= DRM_FORMAT_MOD_INVALID
;
1078 return fd_resource_create_with_modifiers(pscreen
, tmpl
, &mod
, 1);
1082 * Create a texture from a winsys_handle. The handle is often created in
1083 * another process by first creating a pipe texture and then calling
1084 * resource_get_handle.
1086 static struct pipe_resource
*
1087 fd_resource_from_handle(struct pipe_screen
*pscreen
,
1088 const struct pipe_resource
*tmpl
,
1089 struct winsys_handle
*handle
, unsigned usage
)
1091 struct fd_screen
*screen
= fd_screen(pscreen
);
1092 struct fd_resource
*rsc
= CALLOC_STRUCT(fd_resource
);
1093 struct fdl_slice
*slice
= fd_resource_slice(rsc
, 0);
1094 struct pipe_resource
*prsc
= &rsc
->base
;
1095 uint32_t pitchalign
= fd_screen(pscreen
)->gmem_alignw
* rsc
->layout
.cpp
;
1097 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
1098 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
1099 tmpl
->target
, util_format_name(tmpl
->format
),
1100 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
1101 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
1102 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
1108 fd_resource_layout_init(prsc
);
1110 pipe_reference_init(&prsc
->reference
, 1);
1112 prsc
->screen
= pscreen
;
1114 util_range_init(&rsc
->valid_buffer_range
);
1116 simple_mtx_init(&rsc
->lock
, mtx_plain
);
1118 rsc
->bo
= fd_screen_bo_from_handle(pscreen
, handle
);
1122 rsc
->internal_format
= tmpl
->format
;
1123 slice
->pitch
= handle
->stride
;
1124 slice
->offset
= handle
->offset
;
1125 slice
->size0
= handle
->stride
* prsc
->height0
;
1127 if ((slice
->pitch
< align(prsc
->width0
* rsc
->layout
.cpp
, pitchalign
)) ||
1128 (slice
->pitch
& (pitchalign
- 1)))
1131 assert(rsc
->layout
.cpp
);
1133 if (screen
->layout_resource_for_modifier(rsc
, handle
->modifier
) < 0)
1138 renderonly_create_gpu_import_for_resource(prsc
, screen
->ro
, NULL
);
1139 /* failure is expected in some cases.. */
1147 fd_resource_destroy(pscreen
, prsc
);
1152 fd_render_condition_check(struct pipe_context
*pctx
)
1154 struct fd_context
*ctx
= fd_context(pctx
);
1156 if (!ctx
->cond_query
)
1159 union pipe_query_result res
= { 0 };
1161 ctx
->cond_mode
!= PIPE_RENDER_COND_NO_WAIT
&&
1162 ctx
->cond_mode
!= PIPE_RENDER_COND_BY_REGION_NO_WAIT
;
1164 if (pctx
->get_query_result(pctx
, ctx
->cond_query
, wait
, &res
))
1165 return (bool)res
.u64
!= ctx
->cond_cond
;
1171 fd_invalidate_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
1173 struct fd_context
*ctx
= fd_context(pctx
);
1174 struct fd_resource
*rsc
= fd_resource(prsc
);
1177 * TODO I guess we could track that the resource is invalidated and
1178 * use that as a hint to realloc rather than stall in _transfer_map(),
1179 * even in the non-DISCARD_WHOLE_RESOURCE case?
1181 * Note: we set dirty bits to trigger invalidate logic fd_draw_vbo
1184 if (rsc
->write_batch
) {
1185 struct fd_batch
*batch
= rsc
->write_batch
;
1186 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1188 if (pfb
->zsbuf
&& pfb
->zsbuf
->texture
== prsc
) {
1189 batch
->resolve
&= ~(FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
);
1190 ctx
->dirty
|= FD_DIRTY_ZSA
;
1193 for (unsigned i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1194 if (pfb
->cbufs
[i
] && pfb
->cbufs
[i
]->texture
== prsc
) {
1195 batch
->resolve
&= ~(PIPE_CLEAR_COLOR0
<< i
);
1196 ctx
->dirty
|= FD_DIRTY_FRAMEBUFFER
;
1204 static enum pipe_format
1205 fd_resource_get_internal_format(struct pipe_resource
*prsc
)
1207 return fd_resource(prsc
)->internal_format
;
1211 fd_resource_set_stencil(struct pipe_resource
*prsc
,
1212 struct pipe_resource
*stencil
)
1214 fd_resource(prsc
)->stencil
= fd_resource(stencil
);
1217 static struct pipe_resource
*
1218 fd_resource_get_stencil(struct pipe_resource
*prsc
)
1220 struct fd_resource
*rsc
= fd_resource(prsc
);
1222 return &rsc
->stencil
->base
;
1226 static const struct u_transfer_vtbl transfer_vtbl
= {
1227 .resource_create
= fd_resource_create
,
1228 .resource_destroy
= fd_resource_destroy
,
1229 .transfer_map
= fd_resource_transfer_map
,
1230 .transfer_flush_region
= fd_resource_transfer_flush_region
,
1231 .transfer_unmap
= fd_resource_transfer_unmap
,
1232 .get_internal_format
= fd_resource_get_internal_format
,
1233 .set_stencil
= fd_resource_set_stencil
,
1234 .get_stencil
= fd_resource_get_stencil
,
1237 static const uint64_t supported_modifiers
[] = {
1238 DRM_FORMAT_MOD_LINEAR
,
1242 fd_layout_resource_for_modifier(struct fd_resource
*rsc
, uint64_t modifier
)
1245 case DRM_FORMAT_MOD_LINEAR
:
1253 fd_resource_screen_init(struct pipe_screen
*pscreen
)
1255 struct fd_screen
*screen
= fd_screen(pscreen
);
1256 bool fake_rgtc
= screen
->gpu_id
< 400;
1258 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1259 /* NOTE: u_transfer_helper does not yet support the _with_modifiers()
1262 pscreen
->resource_create_with_modifiers
= fd_resource_create_with_modifiers
;
1263 pscreen
->resource_from_handle
= fd_resource_from_handle
;
1264 pscreen
->resource_get_handle
= fd_resource_get_handle
;
1265 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1267 pscreen
->transfer_helper
= u_transfer_helper_create(&transfer_vtbl
,
1268 true, false, fake_rgtc
, true);
1270 if (!screen
->setup_slices
)
1271 screen
->setup_slices
= fd_setup_slices
;
1272 if (!screen
->layout_resource_for_modifier
)
1273 screen
->layout_resource_for_modifier
= fd_layout_resource_for_modifier
;
1274 if (!screen
->supported_modifiers
) {
1275 screen
->supported_modifiers
= supported_modifiers
;
1276 screen
->num_supported_modifiers
= ARRAY_SIZE(supported_modifiers
);
1281 fd_get_sample_position(struct pipe_context
*context
,
1282 unsigned sample_count
, unsigned sample_index
,
1285 /* The following is copied from nouveau/nv50 except for position
1286 * values, which are taken from blob driver */
1287 static const uint8_t pos1
[1][2] = { { 0x8, 0x8 } };
1288 static const uint8_t pos2
[2][2] = {
1289 { 0xc, 0xc }, { 0x4, 0x4 } };
1290 static const uint8_t pos4
[4][2] = {
1291 { 0x6, 0x2 }, { 0xe, 0x6 },
1292 { 0x2, 0xa }, { 0xa, 0xe } };
1293 /* TODO needs to be verified on supported hw */
1294 static const uint8_t pos8
[8][2] = {
1295 { 0x9, 0x5 }, { 0x7, 0xb },
1296 { 0xd, 0x9 }, { 0x5, 0x3 },
1297 { 0x3, 0xd }, { 0x1, 0x7 },
1298 { 0xb, 0xf }, { 0xf, 0x1 } };
1300 const uint8_t (*ptr
)[2];
1302 switch (sample_count
) {
1320 pos_out
[0] = ptr
[sample_index
][0] / 16.0f
;
1321 pos_out
[1] = ptr
[sample_index
][1] / 16.0f
;
1325 fd_blit_pipe(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
1327 /* wrap fd_blit to return void */
1328 fd_blit(pctx
, blit_info
);
1332 fd_resource_context_init(struct pipe_context
*pctx
)
1334 pctx
->transfer_map
= u_transfer_helper_transfer_map
;
1335 pctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1336 pctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1337 pctx
->buffer_subdata
= u_default_buffer_subdata
;
1338 pctx
->texture_subdata
= u_default_texture_subdata
;
1339 pctx
->create_surface
= fd_create_surface
;
1340 pctx
->surface_destroy
= fd_surface_destroy
;
1341 pctx
->resource_copy_region
= fd_resource_copy_region
;
1342 pctx
->blit
= fd_blit_pipe
;
1343 pctx
->flush_resource
= fd_flush_resource
;
1344 pctx
->invalidate_resource
= fd_invalidate_resource
;
1345 pctx
->get_sample_position
= fd_get_sample_position
;