freedreno: Drop the extra offset field for mipmap slices.
[mesa.git] / src / gallium / drivers / freedreno / freedreno_resource.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "util/format/u_format.h"
28 #include "util/format/u_format_rgtc.h"
29 #include "util/format/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
34 #include "util/set.h"
35 #include "util/u_drm.h"
36
37 #include "freedreno_resource.h"
38 #include "freedreno_batch_cache.h"
39 #include "freedreno_blitter.h"
40 #include "freedreno_fence.h"
41 #include "freedreno_screen.h"
42 #include "freedreno_surface.h"
43 #include "freedreno_context.h"
44 #include "freedreno_query_hw.h"
45 #include "freedreno_util.h"
46
47 #include "drm-uapi/drm_fourcc.h"
48 #include <errno.h>
49
50 /* XXX this should go away, needed for 'struct winsys_handle' */
51 #include "state_tracker/drm_driver.h"
52
53 /* A private modifier for now, so we have a way to request tiled but not
54 * compressed. It would perhaps be good to get real modifiers for the
55 * tiled formats, but would probably need to do some work to figure out
56 * the layout(s) of the tiled modes, and whether they are the same
57 * across generations.
58 */
59 #define FD_FORMAT_MOD_QCOM_TILED fourcc_mod_code(QCOM, 0xffffffff)
60
61 /**
62 * Go through the entire state and see if the resource is bound
63 * anywhere. If it is, mark the relevant state as dirty. This is
64 * called on realloc_bo to ensure the neccessary state is re-
65 * emitted so the GPU looks at the new backing bo.
66 */
67 static void
68 rebind_resource(struct fd_context *ctx, struct pipe_resource *prsc)
69 {
70 /* VBOs */
71 for (unsigned i = 0; i < ctx->vtx.vertexbuf.count && !(ctx->dirty & FD_DIRTY_VTXBUF); i++) {
72 if (ctx->vtx.vertexbuf.vb[i].buffer.resource == prsc)
73 ctx->dirty |= FD_DIRTY_VTXBUF;
74 }
75
76 /* per-shader-stage resources: */
77 for (unsigned stage = 0; stage < PIPE_SHADER_TYPES; stage++) {
78 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
79 * cmdstream rather than by pointer..
80 */
81 const unsigned num_ubos = util_last_bit(ctx->constbuf[stage].enabled_mask);
82 for (unsigned i = 1; i < num_ubos; i++) {
83 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_CONST)
84 break;
85 if (ctx->constbuf[stage].cb[i].buffer == prsc)
86 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_CONST;
87 }
88
89 /* Textures */
90 for (unsigned i = 0; i < ctx->tex[stage].num_textures; i++) {
91 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_TEX)
92 break;
93 if (ctx->tex[stage].textures[i] && (ctx->tex[stage].textures[i]->texture == prsc))
94 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_TEX;
95 }
96
97 /* Images */
98 const unsigned num_images = util_last_bit(ctx->shaderimg[stage].enabled_mask);
99 for (unsigned i = 0; i < num_images; i++) {
100 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_IMAGE)
101 break;
102 if (ctx->shaderimg[stage].si[i].resource == prsc)
103 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_IMAGE;
104 }
105
106 /* SSBOs */
107 const unsigned num_ssbos = util_last_bit(ctx->shaderbuf[stage].enabled_mask);
108 for (unsigned i = 0; i < num_ssbos; i++) {
109 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_SSBO)
110 break;
111 if (ctx->shaderbuf[stage].sb[i].buffer == prsc)
112 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_SSBO;
113 }
114 }
115 }
116
117 static void
118 realloc_bo(struct fd_resource *rsc, uint32_t size)
119 {
120 struct pipe_resource *prsc = &rsc->base;
121 struct fd_screen *screen = fd_screen(rsc->base.screen);
122 uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
123 DRM_FREEDRENO_GEM_TYPE_KMEM |
124 COND(prsc->bind & PIPE_BIND_SCANOUT, DRM_FREEDRENO_GEM_SCANOUT);
125 /* TODO other flags? */
126
127 /* if we start using things other than write-combine,
128 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
129 */
130
131 if (rsc->bo)
132 fd_bo_del(rsc->bo);
133
134 rsc->bo = fd_bo_new(screen->dev, size, flags, "%ux%ux%u@%u:%x",
135 prsc->width0, prsc->height0, prsc->depth0, rsc->layout.cpp, prsc->bind);
136 rsc->seqno = p_atomic_inc_return(&screen->rsc_seqno);
137 util_range_set_empty(&rsc->valid_buffer_range);
138 fd_bc_invalidate_resource(rsc, true);
139 }
140
141 static void
142 do_blit(struct fd_context *ctx, const struct pipe_blit_info *blit, bool fallback)
143 {
144 struct pipe_context *pctx = &ctx->base;
145
146 /* TODO size threshold too?? */
147 if (fallback || !fd_blit(pctx, blit)) {
148 /* do blit on cpu: */
149 util_resource_copy_region(pctx,
150 blit->dst.resource, blit->dst.level, blit->dst.box.x,
151 blit->dst.box.y, blit->dst.box.z,
152 blit->src.resource, blit->src.level, &blit->src.box);
153 }
154 }
155
156 /**
157 * @rsc: the resource to shadow
158 * @level: the level to discard (if box != NULL, otherwise ignored)
159 * @box: the box to discard (or NULL if none)
160 * @modifier: the modifier for the new buffer state
161 */
162 static bool
163 fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
164 unsigned level, const struct pipe_box *box, uint64_t modifier)
165 {
166 struct pipe_context *pctx = &ctx->base;
167 struct pipe_resource *prsc = &rsc->base;
168 bool fallback = false;
169
170 if (prsc->next)
171 return false;
172
173 /* TODO: somehow munge dimensions and format to copy unsupported
174 * render target format to something that is supported?
175 */
176 if (!pctx->screen->is_format_supported(pctx->screen,
177 prsc->format, prsc->target, prsc->nr_samples,
178 prsc->nr_storage_samples,
179 PIPE_BIND_RENDER_TARGET))
180 fallback = true;
181
182 /* do shadowing back-blits on the cpu for buffers: */
183 if (prsc->target == PIPE_BUFFER)
184 fallback = true;
185
186 bool discard_whole_level = box && util_texrange_covers_whole_level(prsc, level,
187 box->x, box->y, box->z, box->width, box->height, box->depth);
188
189 /* TODO need to be more clever about current level */
190 if ((prsc->target >= PIPE_TEXTURE_2D) && box && !discard_whole_level)
191 return false;
192
193 struct pipe_resource *pshadow =
194 pctx->screen->resource_create_with_modifiers(pctx->screen,
195 prsc, &modifier, 1);
196
197 if (!pshadow)
198 return false;
199
200 assert(!ctx->in_shadow);
201 ctx->in_shadow = true;
202
203 /* get rid of any references that batch-cache might have to us (which
204 * should empty/destroy rsc->batches hashset)
205 */
206 fd_bc_invalidate_resource(rsc, false);
207
208 mtx_lock(&ctx->screen->lock);
209
210 /* Swap the backing bo's, so shadow becomes the old buffer,
211 * blit from shadow to new buffer. From here on out, we
212 * cannot fail.
213 *
214 * Note that we need to do it in this order, otherwise if
215 * we go down cpu blit path, the recursive transfer_map()
216 * sees the wrong status..
217 */
218 struct fd_resource *shadow = fd_resource(pshadow);
219
220 DBG("shadow: %p (%d) -> %p (%d)\n", rsc, rsc->base.reference.count,
221 shadow, shadow->base.reference.count);
222
223 /* TODO valid_buffer_range?? */
224 swap(rsc->bo, shadow->bo);
225 swap(rsc->write_batch, shadow->write_batch);
226 for (int level = 0; level <= prsc->last_level; level++)
227 swap(rsc->layout.slices[level], shadow->layout.slices[level]);
228 swap(rsc->layout.ubwc_offset, shadow->layout.ubwc_offset);
229 swap(rsc->layout.ubwc_pitch, shadow->layout.ubwc_pitch);
230 swap(rsc->layout.ubwc_size, shadow->layout.ubwc_size);
231 rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno);
232
233 /* at this point, the newly created shadow buffer is not referenced
234 * by any batches, but the existing rsc (probably) is. We need to
235 * transfer those references over:
236 */
237 debug_assert(shadow->batch_mask == 0);
238 struct fd_batch *batch;
239 foreach_batch(batch, &ctx->screen->batch_cache, rsc->batch_mask) {
240 struct set_entry *entry = _mesa_set_search(batch->resources, rsc);
241 _mesa_set_remove(batch->resources, entry);
242 _mesa_set_add(batch->resources, shadow);
243 }
244 swap(rsc->batch_mask, shadow->batch_mask);
245
246 mtx_unlock(&ctx->screen->lock);
247
248 struct pipe_blit_info blit = {};
249 blit.dst.resource = prsc;
250 blit.dst.format = prsc->format;
251 blit.src.resource = pshadow;
252 blit.src.format = pshadow->format;
253 blit.mask = util_format_get_mask(prsc->format);
254 blit.filter = PIPE_TEX_FILTER_NEAREST;
255
256 #define set_box(field, val) do { \
257 blit.dst.field = (val); \
258 blit.src.field = (val); \
259 } while (0)
260
261 /* blit the other levels in their entirety: */
262 for (unsigned l = 0; l <= prsc->last_level; l++) {
263 if (box && l == level)
264 continue;
265
266 /* just blit whole level: */
267 set_box(level, l);
268 set_box(box.width, u_minify(prsc->width0, l));
269 set_box(box.height, u_minify(prsc->height0, l));
270 set_box(box.depth, u_minify(prsc->depth0, l));
271
272 do_blit(ctx, &blit, fallback);
273 }
274
275 /* deal w/ current level specially, since we might need to split
276 * it up into a couple blits:
277 */
278 if (box && !discard_whole_level) {
279 set_box(level, level);
280
281 switch (prsc->target) {
282 case PIPE_BUFFER:
283 case PIPE_TEXTURE_1D:
284 set_box(box.y, 0);
285 set_box(box.z, 0);
286 set_box(box.height, 1);
287 set_box(box.depth, 1);
288
289 if (box->x > 0) {
290 set_box(box.x, 0);
291 set_box(box.width, box->x);
292
293 do_blit(ctx, &blit, fallback);
294 }
295 if ((box->x + box->width) < u_minify(prsc->width0, level)) {
296 set_box(box.x, box->x + box->width);
297 set_box(box.width, u_minify(prsc->width0, level) - (box->x + box->width));
298
299 do_blit(ctx, &blit, fallback);
300 }
301 break;
302 case PIPE_TEXTURE_2D:
303 /* TODO */
304 default:
305 unreachable("TODO");
306 }
307 }
308
309 ctx->in_shadow = false;
310
311 pipe_resource_reference(&pshadow, NULL);
312
313 return true;
314 }
315
316 /**
317 * Uncompress an UBWC compressed buffer "in place". This works basically
318 * like resource shadowing, creating a new resource, and doing an uncompress
319 * blit, and swapping the state between shadow and original resource so it
320 * appears to the state tracker as if nothing changed.
321 */
322 void
323 fd_resource_uncompress(struct fd_context *ctx, struct fd_resource *rsc)
324 {
325 bool success =
326 fd_try_shadow_resource(ctx, rsc, 0, NULL, FD_FORMAT_MOD_QCOM_TILED);
327
328 /* shadow should not fail in any cases where we need to uncompress: */
329 debug_assert(success);
330
331 /*
332 * TODO what if rsc is used in other contexts, we don't currently
333 * have a good way to rebind_resource() in other contexts. And an
334 * app that is reading one resource in multiple contexts, isn't
335 * going to expect that the resource is modified.
336 *
337 * Hopefully the edge cases where we need to uncompress are rare
338 * enough that they mostly only show up in deqp.
339 */
340
341 rebind_resource(ctx, &rsc->base);
342 }
343
344 static struct fd_resource *
345 fd_alloc_staging(struct fd_context *ctx, struct fd_resource *rsc,
346 unsigned level, const struct pipe_box *box)
347 {
348 struct pipe_context *pctx = &ctx->base;
349 struct pipe_resource tmpl = rsc->base;
350
351 tmpl.width0 = box->width;
352 tmpl.height0 = box->height;
353 /* for array textures, box->depth is the array_size, otherwise
354 * for 3d textures, it is the depth:
355 */
356 if (tmpl.array_size > 1) {
357 if (tmpl.target == PIPE_TEXTURE_CUBE)
358 tmpl.target = PIPE_TEXTURE_2D_ARRAY;
359 tmpl.array_size = box->depth;
360 tmpl.depth0 = 1;
361 } else {
362 tmpl.array_size = 1;
363 tmpl.depth0 = box->depth;
364 }
365 tmpl.last_level = 0;
366 tmpl.bind |= PIPE_BIND_LINEAR;
367
368 struct pipe_resource *pstaging =
369 pctx->screen->resource_create(pctx->screen, &tmpl);
370 if (!pstaging)
371 return NULL;
372
373 return fd_resource(pstaging);
374 }
375
376 static void
377 fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
378 {
379 struct pipe_resource *dst = trans->base.resource;
380 struct pipe_blit_info blit = {};
381
382 blit.dst.resource = dst;
383 blit.dst.format = dst->format;
384 blit.dst.level = trans->base.level;
385 blit.dst.box = trans->base.box;
386 blit.src.resource = trans->staging_prsc;
387 blit.src.format = trans->staging_prsc->format;
388 blit.src.level = 0;
389 blit.src.box = trans->staging_box;
390 blit.mask = util_format_get_mask(trans->staging_prsc->format);
391 blit.filter = PIPE_TEX_FILTER_NEAREST;
392
393 do_blit(ctx, &blit, false);
394 }
395
396 static void
397 fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
398 {
399 struct pipe_resource *src = trans->base.resource;
400 struct pipe_blit_info blit = {};
401
402 blit.src.resource = src;
403 blit.src.format = src->format;
404 blit.src.level = trans->base.level;
405 blit.src.box = trans->base.box;
406 blit.dst.resource = trans->staging_prsc;
407 blit.dst.format = trans->staging_prsc->format;
408 blit.dst.level = 0;
409 blit.dst.box = trans->staging_box;
410 blit.mask = util_format_get_mask(trans->staging_prsc->format);
411 blit.filter = PIPE_TEX_FILTER_NEAREST;
412
413 do_blit(ctx, &blit, false);
414 }
415
416 static void fd_resource_transfer_flush_region(struct pipe_context *pctx,
417 struct pipe_transfer *ptrans,
418 const struct pipe_box *box)
419 {
420 struct fd_resource *rsc = fd_resource(ptrans->resource);
421
422 if (ptrans->resource->target == PIPE_BUFFER)
423 util_range_add(&rsc->base, &rsc->valid_buffer_range,
424 ptrans->box.x + box->x,
425 ptrans->box.x + box->x + box->width);
426 }
427
428 static void
429 flush_resource(struct fd_context *ctx, struct fd_resource *rsc, unsigned usage)
430 {
431 struct fd_batch *write_batch = NULL;
432
433 mtx_lock(&ctx->screen->lock);
434 fd_batch_reference_locked(&write_batch, rsc->write_batch);
435 mtx_unlock(&ctx->screen->lock);
436
437 if (usage & PIPE_TRANSFER_WRITE) {
438 struct fd_batch *batch, *batches[32] = {};
439 uint32_t batch_mask;
440
441 /* This is a bit awkward, probably a fd_batch_flush_locked()
442 * would make things simpler.. but we need to hold the lock
443 * to iterate the batches which reference this resource. So
444 * we must first grab references under a lock, then flush.
445 */
446 mtx_lock(&ctx->screen->lock);
447 batch_mask = rsc->batch_mask;
448 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
449 fd_batch_reference_locked(&batches[batch->idx], batch);
450 mtx_unlock(&ctx->screen->lock);
451
452 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
453 fd_batch_flush(batch, false);
454
455 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask) {
456 fd_batch_sync(batch);
457 fd_batch_reference(&batches[batch->idx], NULL);
458 }
459 assert(rsc->batch_mask == 0);
460 } else if (write_batch) {
461 fd_batch_flush(write_batch, true);
462 }
463
464 fd_batch_reference(&write_batch, NULL);
465
466 assert(!rsc->write_batch);
467 }
468
469 static void
470 fd_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
471 {
472 flush_resource(fd_context(pctx), fd_resource(prsc), PIPE_TRANSFER_READ);
473 }
474
475 static void
476 fd_resource_transfer_unmap(struct pipe_context *pctx,
477 struct pipe_transfer *ptrans)
478 {
479 struct fd_context *ctx = fd_context(pctx);
480 struct fd_resource *rsc = fd_resource(ptrans->resource);
481 struct fd_transfer *trans = fd_transfer(ptrans);
482
483 if (trans->staging_prsc) {
484 if (ptrans->usage & PIPE_TRANSFER_WRITE)
485 fd_blit_from_staging(ctx, trans);
486 pipe_resource_reference(&trans->staging_prsc, NULL);
487 }
488
489 if (!(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
490 fd_bo_cpu_fini(rsc->bo);
491 }
492
493 util_range_add(&rsc->base, &rsc->valid_buffer_range,
494 ptrans->box.x,
495 ptrans->box.x + ptrans->box.width);
496
497 pipe_resource_reference(&ptrans->resource, NULL);
498 slab_free(&ctx->transfer_pool, ptrans);
499 }
500
501 static void *
502 fd_resource_transfer_map(struct pipe_context *pctx,
503 struct pipe_resource *prsc,
504 unsigned level, unsigned usage,
505 const struct pipe_box *box,
506 struct pipe_transfer **pptrans)
507 {
508 struct fd_context *ctx = fd_context(pctx);
509 struct fd_resource *rsc = fd_resource(prsc);
510 struct fdl_slice *slice = fd_resource_slice(rsc, level);
511 struct fd_transfer *trans;
512 struct pipe_transfer *ptrans;
513 enum pipe_format format = prsc->format;
514 uint32_t op = 0;
515 uint32_t offset;
516 char *buf;
517 int ret = 0;
518
519 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc, level, usage,
520 box->width, box->height, box->x, box->y);
521
522 ptrans = slab_alloc(&ctx->transfer_pool);
523 if (!ptrans)
524 return NULL;
525
526 /* slab_alloc_st() doesn't zero: */
527 trans = fd_transfer(ptrans);
528 memset(trans, 0, sizeof(*trans));
529
530 pipe_resource_reference(&ptrans->resource, prsc);
531 ptrans->level = level;
532 ptrans->usage = usage;
533 ptrans->box = *box;
534 ptrans->stride = util_format_get_nblocksx(format, slice->pitch) * rsc->layout.cpp;
535 ptrans->layer_stride = fd_resource_layer_stride(rsc, level);
536
537 /* we always need a staging texture for tiled buffers:
538 *
539 * TODO we might sometimes want to *also* shadow the resource to avoid
540 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
541 * texture.
542 */
543 if (rsc->layout.tile_mode) {
544 struct fd_resource *staging_rsc;
545
546 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
547 if (staging_rsc) {
548 struct fdl_slice *staging_slice =
549 fd_resource_slice(staging_rsc, 0);
550 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
551 trans->staging_prsc = &staging_rsc->base;
552 trans->base.stride = util_format_get_nblocksx(format,
553 staging_slice->pitch) * staging_rsc->layout.cpp;
554 trans->base.layer_stride = fd_resource_layer_stride(staging_rsc, 0);
555 trans->staging_box = *box;
556 trans->staging_box.x = 0;
557 trans->staging_box.y = 0;
558 trans->staging_box.z = 0;
559
560 if (usage & PIPE_TRANSFER_READ) {
561 fd_blit_to_staging(ctx, trans);
562
563 struct fd_batch *batch = NULL;
564
565 fd_context_lock(ctx);
566 fd_batch_reference_locked(&batch, staging_rsc->write_batch);
567 fd_context_unlock(ctx);
568
569 /* we can't fd_bo_cpu_prep() until the blit to staging
570 * is submitted to kernel.. in that case write_batch
571 * wouldn't be NULL yet:
572 */
573 if (batch) {
574 fd_batch_sync(batch);
575 fd_batch_reference(&batch, NULL);
576 }
577
578 fd_bo_cpu_prep(staging_rsc->bo, ctx->pipe,
579 DRM_FREEDRENO_PREP_READ);
580 }
581
582 buf = fd_bo_map(staging_rsc->bo);
583 offset = 0;
584
585 *pptrans = ptrans;
586
587 ctx->stats.staging_uploads++;
588
589 return buf;
590 }
591 }
592
593 if (ctx->in_shadow && !(usage & PIPE_TRANSFER_READ))
594 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
595
596 if (usage & PIPE_TRANSFER_READ)
597 op |= DRM_FREEDRENO_PREP_READ;
598
599 if (usage & PIPE_TRANSFER_WRITE)
600 op |= DRM_FREEDRENO_PREP_WRITE;
601
602 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
603 realloc_bo(rsc, fd_bo_size(rsc->bo));
604 rebind_resource(ctx, prsc);
605 } else if ((usage & PIPE_TRANSFER_WRITE) &&
606 prsc->target == PIPE_BUFFER &&
607 !util_ranges_intersect(&rsc->valid_buffer_range,
608 box->x, box->x + box->width)) {
609 /* We are trying to write to a previously uninitialized range. No need
610 * to wait.
611 */
612 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
613 struct fd_batch *write_batch = NULL;
614
615 /* hold a reference, so it doesn't disappear under us: */
616 fd_context_lock(ctx);
617 fd_batch_reference_locked(&write_batch, rsc->write_batch);
618 fd_context_unlock(ctx);
619
620 if ((usage & PIPE_TRANSFER_WRITE) && write_batch &&
621 write_batch->back_blit) {
622 /* if only thing pending is a back-blit, we can discard it: */
623 fd_batch_reset(write_batch);
624 }
625
626 /* If the GPU is writing to the resource, or if it is reading from the
627 * resource and we're trying to write to it, flush the renders.
628 */
629 bool needs_flush = pending(rsc, !!(usage & PIPE_TRANSFER_WRITE));
630 bool busy = needs_flush || (0 != fd_bo_cpu_prep(rsc->bo,
631 ctx->pipe, op | DRM_FREEDRENO_PREP_NOSYNC));
632
633 /* if we need to flush/stall, see if we can make a shadow buffer
634 * to avoid this:
635 *
636 * TODO we could go down this path !reorder && !busy_for_read
637 * ie. we only *don't* want to go down this path if the blit
638 * will trigger a flush!
639 */
640 if (ctx->screen->reorder && busy && !(usage & PIPE_TRANSFER_READ) &&
641 (usage & PIPE_TRANSFER_DISCARD_RANGE)) {
642 /* try shadowing only if it avoids a flush, otherwise staging would
643 * be better:
644 */
645 if (needs_flush && fd_try_shadow_resource(ctx, rsc, level,
646 box, DRM_FORMAT_MOD_LINEAR)) {
647 needs_flush = busy = false;
648 rebind_resource(ctx, prsc);
649 ctx->stats.shadow_uploads++;
650 } else {
651 struct fd_resource *staging_rsc;
652
653 if (needs_flush) {
654 flush_resource(ctx, rsc, usage);
655 needs_flush = false;
656 }
657
658 /* in this case, we don't need to shadow the whole resource,
659 * since any draw that references the previous contents has
660 * already had rendering flushed for all tiles. So we can
661 * use a staging buffer to do the upload.
662 */
663 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
664 if (staging_rsc) {
665 struct fdl_slice *staging_slice =
666 fd_resource_slice(staging_rsc, 0);
667 trans->staging_prsc = &staging_rsc->base;
668 trans->base.stride = util_format_get_nblocksx(format,
669 staging_slice->pitch) * staging_rsc->layout.cpp;
670 trans->base.layer_stride =
671 fd_resource_layer_stride(staging_rsc, 0);
672 trans->staging_box = *box;
673 trans->staging_box.x = 0;
674 trans->staging_box.y = 0;
675 trans->staging_box.z = 0;
676 buf = fd_bo_map(staging_rsc->bo);
677 offset = 0;
678
679 *pptrans = ptrans;
680
681 fd_batch_reference(&write_batch, NULL);
682
683 ctx->stats.staging_uploads++;
684
685 return buf;
686 }
687 }
688 }
689
690 if (needs_flush) {
691 flush_resource(ctx, rsc, usage);
692 needs_flush = false;
693 }
694
695 fd_batch_reference(&write_batch, NULL);
696
697 /* The GPU keeps track of how the various bo's are being used, and
698 * will wait if necessary for the proper operation to have
699 * completed.
700 */
701 if (busy) {
702 ret = fd_bo_cpu_prep(rsc->bo, ctx->pipe, op);
703 if (ret)
704 goto fail;
705 }
706 }
707
708 buf = fd_bo_map(rsc->bo);
709 offset =
710 box->y / util_format_get_blockheight(format) * ptrans->stride +
711 box->x / util_format_get_blockwidth(format) * rsc->layout.cpp +
712 fd_resource_offset(rsc, level, box->z);
713
714 if (usage & PIPE_TRANSFER_WRITE)
715 rsc->valid = true;
716
717 *pptrans = ptrans;
718
719 return buf + offset;
720
721 fail:
722 fd_resource_transfer_unmap(pctx, ptrans);
723 return NULL;
724 }
725
726 static void
727 fd_resource_destroy(struct pipe_screen *pscreen,
728 struct pipe_resource *prsc)
729 {
730 struct fd_resource *rsc = fd_resource(prsc);
731 fd_bc_invalidate_resource(rsc, true);
732 if (rsc->bo)
733 fd_bo_del(rsc->bo);
734 if (rsc->scanout)
735 renderonly_scanout_destroy(rsc->scanout, fd_screen(pscreen)->ro);
736
737 util_range_destroy(&rsc->valid_buffer_range);
738 FREE(rsc);
739 }
740
741 static uint64_t
742 fd_resource_modifier(struct fd_resource *rsc)
743 {
744 if (!rsc->layout.tile_mode)
745 return DRM_FORMAT_MOD_LINEAR;
746
747 if (rsc->layout.ubwc_size)
748 return DRM_FORMAT_MOD_QCOM_COMPRESSED;
749
750 /* TODO invent a modifier for tiled but not UBWC buffers: */
751 return DRM_FORMAT_MOD_INVALID;
752 }
753
754 static bool
755 fd_resource_get_handle(struct pipe_screen *pscreen,
756 struct pipe_context *pctx,
757 struct pipe_resource *prsc,
758 struct winsys_handle *handle,
759 unsigned usage)
760 {
761 struct fd_resource *rsc = fd_resource(prsc);
762
763 handle->modifier = fd_resource_modifier(rsc);
764
765 return fd_screen_bo_get_handle(pscreen, rsc->bo, rsc->scanout,
766 fd_resource_slice(rsc, 0)->pitch * rsc->layout.cpp, handle);
767 }
768
769 static uint32_t
770 setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format format)
771 {
772 struct pipe_resource *prsc = &rsc->base;
773 struct fd_screen *screen = fd_screen(prsc->screen);
774 enum util_format_layout layout = util_format_description(format)->layout;
775 uint32_t pitchalign = screen->gmem_alignw;
776 uint32_t level, size = 0;
777 uint32_t width = prsc->width0;
778 uint32_t height = prsc->height0;
779 uint32_t depth = prsc->depth0;
780 /* in layer_first layout, the level (slice) contains just one
781 * layer (since in fact the layer contains the slices)
782 */
783 uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size;
784
785 for (level = 0; level <= prsc->last_level; level++) {
786 struct fdl_slice *slice = fd_resource_slice(rsc, level);
787 uint32_t blocks;
788
789 if (layout == UTIL_FORMAT_LAYOUT_ASTC)
790 slice->pitch = width =
791 util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
792 else
793 slice->pitch = width = align(width, pitchalign);
794 slice->offset = size;
795 blocks = util_format_get_nblocks(format, width, height);
796 /* 1d array and 2d array textures must all have the same layer size
797 * for each miplevel on a3xx. 3d textures can have different layer
798 * sizes for high levels, but the hw auto-sizer is buggy (or at least
799 * different than what this code does), so as soon as the layer size
800 * range gets into range, we stop reducing it.
801 */
802 if (prsc->target == PIPE_TEXTURE_3D && (
803 level == 1 ||
804 (level > 1 && fd_resource_slice(rsc, level - 1)->size0 > 0xf000)))
805 slice->size0 = align(blocks * rsc->layout.cpp, alignment);
806 else if (level == 0 || rsc->layout.layer_first || alignment == 1)
807 slice->size0 = align(blocks * rsc->layout.cpp, alignment);
808 else
809 slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
810
811 size += slice->size0 * depth * layers_in_level;
812
813 width = u_minify(width, 1);
814 height = u_minify(height, 1);
815 depth = u_minify(depth, 1);
816 }
817
818 return size;
819 }
820
821 static uint32_t
822 slice_alignment(enum pipe_texture_target target)
823 {
824 /* on a3xx, 2d array and 3d textures seem to want their
825 * layers aligned to page boundaries:
826 */
827 switch (target) {
828 case PIPE_TEXTURE_3D:
829 case PIPE_TEXTURE_1D_ARRAY:
830 case PIPE_TEXTURE_2D_ARRAY:
831 return 4096;
832 default:
833 return 1;
834 }
835 }
836
837 /* cross generation texture layout to plug in to screen->setup_slices()..
838 * replace with generation specific one as-needed.
839 *
840 * TODO for a4xx probably can extract out the a4xx specific logic int
841 * a small fd4_setup_slices() wrapper that sets up layer_first, and then
842 * calls this.
843 */
844 uint32_t
845 fd_setup_slices(struct fd_resource *rsc)
846 {
847 uint32_t alignment;
848
849 alignment = slice_alignment(rsc->base.target);
850
851 struct fd_screen *screen = fd_screen(rsc->base.screen);
852 if (is_a4xx(screen)) {
853 switch (rsc->base.target) {
854 case PIPE_TEXTURE_3D:
855 rsc->layout.layer_first = false;
856 break;
857 default:
858 rsc->layout.layer_first = true;
859 alignment = 1;
860 break;
861 }
862 }
863
864 return setup_slices(rsc, alignment, rsc->base.format);
865 }
866
867 /* special case to resize query buf after allocated.. */
868 void
869 fd_resource_resize(struct pipe_resource *prsc, uint32_t sz)
870 {
871 struct fd_resource *rsc = fd_resource(prsc);
872
873 debug_assert(prsc->width0 == 0);
874 debug_assert(prsc->target == PIPE_BUFFER);
875 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
876
877 prsc->width0 = sz;
878 realloc_bo(rsc, fd_screen(prsc->screen)->setup_slices(rsc));
879 }
880
881 static void
882 fd_resource_layout_init(struct pipe_resource *prsc)
883 {
884 struct fd_resource *rsc = fd_resource(prsc);
885 struct fdl_layout *layout = &rsc->layout;
886
887 layout->width0 = prsc->width0;
888 layout->height0 = prsc->height0;
889 layout->depth0 = prsc->depth0;
890
891 layout->cpp = util_format_get_blocksize(prsc->format);
892 layout->cpp *= fd_resource_nr_samples(prsc);
893 }
894
895 /**
896 * Create a new texture object, using the given template info.
897 */
898 static struct pipe_resource *
899 fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
900 const struct pipe_resource *tmpl,
901 const uint64_t *modifiers, int count)
902 {
903 struct fd_screen *screen = fd_screen(pscreen);
904 struct fd_resource *rsc;
905 struct pipe_resource *prsc;
906 enum pipe_format format = tmpl->format;
907 uint32_t size;
908
909 /* when using kmsro, scanout buffers are allocated on the display device
910 * create_with_modifiers() doesn't give us usage flags, so we have to
911 * assume that all calls with modifiers are scanout-possible
912 */
913 if (screen->ro &&
914 ((tmpl->bind & PIPE_BIND_SCANOUT) ||
915 !(count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID))) {
916 struct pipe_resource scanout_templat = *tmpl;
917 struct renderonly_scanout *scanout;
918 struct winsys_handle handle;
919
920 /* apply freedreno alignment requirement */
921 scanout_templat.width0 = align(tmpl->width0, screen->gmem_alignw);
922
923 scanout = renderonly_scanout_for_resource(&scanout_templat,
924 screen->ro, &handle);
925 if (!scanout)
926 return NULL;
927
928 renderonly_scanout_destroy(scanout, screen->ro);
929
930 assert(handle.type == WINSYS_HANDLE_TYPE_FD);
931 rsc = fd_resource(pscreen->resource_from_handle(pscreen, tmpl,
932 &handle,
933 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
934 close(handle.handle);
935 if (!rsc)
936 return NULL;
937
938 return &rsc->base;
939 }
940
941 rsc = CALLOC_STRUCT(fd_resource);
942 prsc = &rsc->base;
943
944 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
945 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc,
946 tmpl->target, util_format_name(format),
947 tmpl->width0, tmpl->height0, tmpl->depth0,
948 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
949 tmpl->usage, tmpl->bind, tmpl->flags);
950
951 if (!rsc)
952 return NULL;
953
954 *prsc = *tmpl;
955 fd_resource_layout_init(prsc);
956
957 #define LINEAR \
958 (PIPE_BIND_SCANOUT | \
959 PIPE_BIND_LINEAR | \
960 PIPE_BIND_DISPLAY_TARGET)
961
962 bool linear = drm_find_modifier(DRM_FORMAT_MOD_LINEAR, modifiers, count);
963 if (tmpl->bind & LINEAR)
964 linear = true;
965
966 /* Normally, for non-shared buffers, allow buffer compression if
967 * not shared, otherwise only allow if QCOM_COMPRESSED modifier
968 * is requested:
969 *
970 * TODO we should probably also limit tiled in a similar way,
971 * except we don't have a format modifier for tiled. (We probably
972 * should.)
973 */
974 bool allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_INVALID, modifiers, count);
975 if (tmpl->bind & PIPE_BIND_SHARED)
976 allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_QCOM_COMPRESSED, modifiers, count);
977
978 allow_ubwc &= !(fd_mesa_debug & FD_DBG_NOUBWC);
979
980 pipe_reference_init(&prsc->reference, 1);
981
982 prsc->screen = pscreen;
983
984 if (screen->tile_mode &&
985 (tmpl->target != PIPE_BUFFER) &&
986 !linear) {
987 rsc->layout.tile_mode = screen->tile_mode(prsc);
988 }
989
990 util_range_init(&rsc->valid_buffer_range);
991
992 rsc->internal_format = format;
993
994 size = screen->setup_slices(rsc);
995
996 if (allow_ubwc && screen->fill_ubwc_buffer_sizes && rsc->layout.tile_mode)
997 size += screen->fill_ubwc_buffer_sizes(rsc);
998
999 /* special case for hw-query buffer, which we need to allocate before we
1000 * know the size:
1001 */
1002 if (size == 0) {
1003 /* note, semi-intention == instead of & */
1004 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
1005 return prsc;
1006 }
1007
1008 if (rsc->layout.layer_first) {
1009 rsc->layout.layer_size = align(size, 4096);
1010 size = rsc->layout.layer_size * prsc->array_size;
1011 }
1012
1013 realloc_bo(rsc, size);
1014 if (!rsc->bo)
1015 goto fail;
1016
1017 return prsc;
1018 fail:
1019 fd_resource_destroy(pscreen, prsc);
1020 return NULL;
1021 }
1022
1023 static struct pipe_resource *
1024 fd_resource_create(struct pipe_screen *pscreen,
1025 const struct pipe_resource *tmpl)
1026 {
1027 const uint64_t mod = DRM_FORMAT_MOD_INVALID;
1028 return fd_resource_create_with_modifiers(pscreen, tmpl, &mod, 1);
1029 }
1030
1031 static bool
1032 is_supported_modifier(struct pipe_screen *pscreen, enum pipe_format pfmt,
1033 uint64_t mod)
1034 {
1035 int count;
1036
1037 /* Get the count of supported modifiers: */
1038 pscreen->query_dmabuf_modifiers(pscreen, pfmt, 0, NULL, NULL, &count);
1039
1040 /* Get the supported modifiers: */
1041 uint64_t modifiers[count];
1042 pscreen->query_dmabuf_modifiers(pscreen, pfmt, count, modifiers, NULL, &count);
1043
1044 for (int i = 0; i < count; i++)
1045 if (modifiers[i] == mod)
1046 return true;
1047
1048 return false;
1049 }
1050
1051 /**
1052 * Create a texture from a winsys_handle. The handle is often created in
1053 * another process by first creating a pipe texture and then calling
1054 * resource_get_handle.
1055 */
1056 static struct pipe_resource *
1057 fd_resource_from_handle(struct pipe_screen *pscreen,
1058 const struct pipe_resource *tmpl,
1059 struct winsys_handle *handle, unsigned usage)
1060 {
1061 struct fd_screen *screen = fd_screen(pscreen);
1062 struct fd_resource *rsc = CALLOC_STRUCT(fd_resource);
1063 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
1064 struct pipe_resource *prsc = &rsc->base;
1065 uint32_t pitchalign = fd_screen(pscreen)->gmem_alignw;
1066
1067 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
1068 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
1069 tmpl->target, util_format_name(tmpl->format),
1070 tmpl->width0, tmpl->height0, tmpl->depth0,
1071 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
1072 tmpl->usage, tmpl->bind, tmpl->flags);
1073
1074 if (!rsc)
1075 return NULL;
1076
1077 *prsc = *tmpl;
1078 fd_resource_layout_init(prsc);
1079
1080 pipe_reference_init(&prsc->reference, 1);
1081
1082 prsc->screen = pscreen;
1083
1084 util_range_init(&rsc->valid_buffer_range);
1085
1086 rsc->bo = fd_screen_bo_from_handle(pscreen, handle);
1087 if (!rsc->bo)
1088 goto fail;
1089
1090 rsc->internal_format = tmpl->format;
1091 slice->pitch = handle->stride / rsc->layout.cpp;
1092 slice->offset = handle->offset;
1093 slice->size0 = handle->stride * prsc->height0;
1094
1095 if ((slice->pitch < align(prsc->width0, pitchalign)) ||
1096 (slice->pitch & (pitchalign - 1)))
1097 goto fail;
1098
1099 if (handle->modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1100 if (!is_supported_modifier(pscreen, tmpl->format,
1101 DRM_FORMAT_MOD_QCOM_COMPRESSED)) {
1102 DBG("bad modifier: %"PRIx64, handle->modifier);
1103 goto fail;
1104 }
1105 debug_assert(screen->fill_ubwc_buffer_sizes);
1106 screen->fill_ubwc_buffer_sizes(rsc);
1107 } else if (handle->modifier &&
1108 (handle->modifier != DRM_FORMAT_MOD_INVALID)) {
1109 goto fail;
1110 }
1111
1112 assert(rsc->layout.cpp);
1113
1114 if (screen->ro) {
1115 rsc->scanout =
1116 renderonly_create_gpu_import_for_resource(prsc, screen->ro, NULL);
1117 /* failure is expected in some cases.. */
1118 }
1119
1120 rsc->valid = true;
1121
1122 return prsc;
1123
1124 fail:
1125 fd_resource_destroy(pscreen, prsc);
1126 return NULL;
1127 }
1128
1129 bool
1130 fd_render_condition_check(struct pipe_context *pctx)
1131 {
1132 struct fd_context *ctx = fd_context(pctx);
1133
1134 if (!ctx->cond_query)
1135 return true;
1136
1137 union pipe_query_result res = { 0 };
1138 bool wait =
1139 ctx->cond_mode != PIPE_RENDER_COND_NO_WAIT &&
1140 ctx->cond_mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT;
1141
1142 if (pctx->get_query_result(pctx, ctx->cond_query, wait, &res))
1143 return (bool)res.u64 != ctx->cond_cond;
1144
1145 return true;
1146 }
1147
1148 static void
1149 fd_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
1150 {
1151 struct fd_context *ctx = fd_context(pctx);
1152 struct fd_resource *rsc = fd_resource(prsc);
1153
1154 /*
1155 * TODO I guess we could track that the resource is invalidated and
1156 * use that as a hint to realloc rather than stall in _transfer_map(),
1157 * even in the non-DISCARD_WHOLE_RESOURCE case?
1158 *
1159 * Note: we set dirty bits to trigger invalidate logic fd_draw_vbo
1160 */
1161
1162 if (rsc->write_batch) {
1163 struct fd_batch *batch = rsc->write_batch;
1164 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1165
1166 if (pfb->zsbuf && pfb->zsbuf->texture == prsc) {
1167 batch->resolve &= ~(FD_BUFFER_DEPTH | FD_BUFFER_STENCIL);
1168 ctx->dirty |= FD_DIRTY_ZSA;
1169 }
1170
1171 for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
1172 if (pfb->cbufs[i] && pfb->cbufs[i]->texture == prsc) {
1173 batch->resolve &= ~(PIPE_CLEAR_COLOR0 << i);
1174 ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
1175 }
1176 }
1177 }
1178
1179 rsc->valid = false;
1180 }
1181
1182 static enum pipe_format
1183 fd_resource_get_internal_format(struct pipe_resource *prsc)
1184 {
1185 return fd_resource(prsc)->internal_format;
1186 }
1187
1188 static void
1189 fd_resource_set_stencil(struct pipe_resource *prsc,
1190 struct pipe_resource *stencil)
1191 {
1192 fd_resource(prsc)->stencil = fd_resource(stencil);
1193 }
1194
1195 static struct pipe_resource *
1196 fd_resource_get_stencil(struct pipe_resource *prsc)
1197 {
1198 struct fd_resource *rsc = fd_resource(prsc);
1199 if (rsc->stencil)
1200 return &rsc->stencil->base;
1201 return NULL;
1202 }
1203
1204 static const struct u_transfer_vtbl transfer_vtbl = {
1205 .resource_create = fd_resource_create,
1206 .resource_destroy = fd_resource_destroy,
1207 .transfer_map = fd_resource_transfer_map,
1208 .transfer_flush_region = fd_resource_transfer_flush_region,
1209 .transfer_unmap = fd_resource_transfer_unmap,
1210 .get_internal_format = fd_resource_get_internal_format,
1211 .set_stencil = fd_resource_set_stencil,
1212 .get_stencil = fd_resource_get_stencil,
1213 };
1214
1215 void
1216 fd_resource_screen_init(struct pipe_screen *pscreen)
1217 {
1218 struct fd_screen *screen = fd_screen(pscreen);
1219 bool fake_rgtc = screen->gpu_id < 400;
1220
1221 pscreen->resource_create = u_transfer_helper_resource_create;
1222 /* NOTE: u_transfer_helper does not yet support the _with_modifiers()
1223 * variant:
1224 */
1225 pscreen->resource_create_with_modifiers = fd_resource_create_with_modifiers;
1226 pscreen->resource_from_handle = fd_resource_from_handle;
1227 pscreen->resource_get_handle = fd_resource_get_handle;
1228 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
1229
1230 pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl,
1231 true, false, fake_rgtc, true);
1232
1233 if (!screen->setup_slices)
1234 screen->setup_slices = fd_setup_slices;
1235 }
1236
1237 static void
1238 fd_get_sample_position(struct pipe_context *context,
1239 unsigned sample_count, unsigned sample_index,
1240 float *pos_out)
1241 {
1242 /* The following is copied from nouveau/nv50 except for position
1243 * values, which are taken from blob driver */
1244 static const uint8_t pos1[1][2] = { { 0x8, 0x8 } };
1245 static const uint8_t pos2[2][2] = {
1246 { 0xc, 0xc }, { 0x4, 0x4 } };
1247 static const uint8_t pos4[4][2] = {
1248 { 0x6, 0x2 }, { 0xe, 0x6 },
1249 { 0x2, 0xa }, { 0xa, 0xe } };
1250 /* TODO needs to be verified on supported hw */
1251 static const uint8_t pos8[8][2] = {
1252 { 0x9, 0x5 }, { 0x7, 0xb },
1253 { 0xd, 0x9 }, { 0x5, 0x3 },
1254 { 0x3, 0xd }, { 0x1, 0x7 },
1255 { 0xb, 0xf }, { 0xf, 0x1 } };
1256
1257 const uint8_t (*ptr)[2];
1258
1259 switch (sample_count) {
1260 case 1:
1261 ptr = pos1;
1262 break;
1263 case 2:
1264 ptr = pos2;
1265 break;
1266 case 4:
1267 ptr = pos4;
1268 break;
1269 case 8:
1270 ptr = pos8;
1271 break;
1272 default:
1273 assert(0);
1274 return;
1275 }
1276
1277 pos_out[0] = ptr[sample_index][0] / 16.0f;
1278 pos_out[1] = ptr[sample_index][1] / 16.0f;
1279 }
1280
1281 static void
1282 fd_blit_pipe(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
1283 {
1284 /* wrap fd_blit to return void */
1285 fd_blit(pctx, blit_info);
1286 }
1287
1288 void
1289 fd_resource_context_init(struct pipe_context *pctx)
1290 {
1291 pctx->transfer_map = u_transfer_helper_transfer_map;
1292 pctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
1293 pctx->transfer_unmap = u_transfer_helper_transfer_unmap;
1294 pctx->buffer_subdata = u_default_buffer_subdata;
1295 pctx->texture_subdata = u_default_texture_subdata;
1296 pctx->create_surface = fd_create_surface;
1297 pctx->surface_destroy = fd_surface_destroy;
1298 pctx->resource_copy_region = fd_resource_copy_region;
1299 pctx->blit = fd_blit_pipe;
1300 pctx->flush_resource = fd_flush_resource;
1301 pctx->invalidate_resource = fd_invalidate_resource;
1302 pctx->get_sample_position = fd_get_sample_position;
1303 }