src/gallium/drivers/freedreno/freedreno_resource.h

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FREEDRENO_RESOURCE_H_
  28 #define FREEDRENO_RESOURCE_H_
  29
  30 #include "util/list.h"
  31 #include "util/u_range.h"
  32 #include "util/u_transfer_helper.h"
  33
  34 #include "freedreno_batch.h"
  35 #include "freedreno_util.h"
  36 #include "freedreno/fdl/freedreno_layout.h"
  37
  38 struct fd_resource {
  39         struct pipe_resource base;
  40         struct fd_bo *bo;
  41         enum pipe_format internal_format;
  42         struct fdl_layout layout;
  43
  44         /* buffer range that has been initialized */
  45         struct util_range valid_buffer_range;
  46         bool valid;
  47         struct renderonly_scanout *scanout;
  48
  49         /* reference to the resource holding stencil data for a z32_s8 texture */
  50         /* TODO rename to secondary or auxiliary? */
  51         struct fd_resource *stencil;
  52
  53         /* bitmask of in-flight batches which reference this resource.  Note
  54          * that the batch doesn't hold reference to resources (but instead
  55          * the fd_ringbuffer holds refs to the underlying fd_bo), but in case
  56          * the resource is destroyed we need to clean up the batch's weak
  57          * references to us.
  58          */
  59         uint32_t batch_mask;
  60
  61         /* reference to batch that writes this resource: */
  62         struct fd_batch *write_batch;
  63
  64         /* Set of batches whose batch-cache key references this resource.
  65          * We need to track this to know which batch-cache entries to
  66          * invalidate if, for example, the resource is invalidated or
  67          * shadowed.
  68          */
  69         uint32_t bc_batch_mask;
  70
  71         /* Sequence # incremented each time bo changes: */
  72         uint16_t seqno;
  73
  74         /*
  75          * LRZ
  76          *
  77          * TODO lrz width/height/pitch should probably also move to
  78          * fdl_layout
  79          */
  80         bool lrz_valid : 1;
  81         uint16_t lrz_width;  // for lrz clear, does this differ from lrz_pitch?
  82         uint16_t lrz_height;
  83         uint16_t lrz_pitch;
  84         struct fd_bo *lrz;
  85 };
  86
  87 static inline struct fd_resource *
  88 fd_resource(struct pipe_resource *ptex)
  89 {
  90         return (struct fd_resource *)ptex;
  91 }
  92
  93 static inline const struct fd_resource *
  94 fd_resource_const(const struct pipe_resource *ptex)
  95 {
  96         return (const struct fd_resource *)ptex;
  97 }
  98
  99 static inline bool
 100 pending(struct fd_resource *rsc, bool write)
 101 {
 102         /* if we have a pending GPU write, we are busy in any case: */
 103         if (rsc->write_batch)
 104                 return true;
 105
 106         /* if CPU wants to write, but we are pending a GPU read, we are busy: */
 107         if (write && rsc->batch_mask)
 108                 return true;
 109
 110         if (rsc->stencil && pending(rsc->stencil, write))
 111                 return true;
 112
 113         return false;
 114 }
 115
 116 static inline bool
 117 has_depth(enum pipe_format format)
 118 {
 119         const struct util_format_description *desc =
 120                         util_format_description(format);
 121         return util_format_has_depth(desc);
 122 }
 123
 124 struct fd_transfer {
 125         struct pipe_transfer base;
 126         struct pipe_resource *staging_prsc;
 127         struct pipe_box staging_box;
 128 };
 129
 130 static inline struct fd_transfer *
 131 fd_transfer(struct pipe_transfer *ptrans)
 132 {
 133         return (struct fd_transfer *)ptrans;
 134 }
 135
 136 static inline struct fdl_slice *
 137 fd_resource_slice(struct fd_resource *rsc, unsigned level)
 138 {
 139         assert(level <= rsc->base.last_level);
 140         return &rsc->layout.slices[level];
 141 }
 142
 143 static inline uint32_t
 144 fd_resource_layer_stride(struct fd_resource *rsc, unsigned level)
 145 {
 146         return fdl_layer_stride(&rsc->layout, level);
 147 }
 148
 149 /* get offset for specified mipmap level and texture/array layer */
 150 static inline uint32_t
 151 fd_resource_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
 152 {
 153         uint32_t offset = fdl_surface_offset(&rsc->layout, level, layer);
 154         debug_assert(offset < fd_bo_size(rsc->bo));
 155         return offset;
 156 }
 157
 158 static inline uint32_t
 159 fd_resource_ubwc_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
 160 {
 161         return fdl_ubwc_offset(&rsc->layout, level, layer);
 162 }
 163
 164 /* This might be a5xx specific, but higher mipmap levels are always linear: */
 165 static inline bool
 166 fd_resource_level_linear(const struct pipe_resource *prsc, int level)
 167 {
 168         struct fd_screen *screen = fd_screen(prsc->screen);
 169         debug_assert(!is_a3xx(screen));
 170
 171         return fdl_level_linear(&fd_resource_const(prsc)->layout, level);
 172 }
 173
 174 static inline uint32_t
 175 fd_resource_tile_mode(struct pipe_resource *prsc, int level)
 176 {
 177         return fdl_tile_mode(&fd_resource(prsc)->layout, level);
 178 }
 179
 180 static inline bool
 181 fd_resource_ubwc_enabled(struct fd_resource *rsc, int level)
 182 {
 183         return fdl_ubwc_enabled(&rsc->layout, level);
 184 }
 185
 186 /* access # of samples, with 0 normalized to 1 (which is what we care about
 187  * most of the time)
 188  */
 189 static inline unsigned
 190 fd_resource_nr_samples(struct pipe_resource *prsc)
 191 {
 192         return MAX2(1, prsc->nr_samples);
 193 }
 194
 195 void fd_resource_screen_init(struct pipe_screen *pscreen);
 196 void fd_resource_context_init(struct pipe_context *pctx);
 197
 198 uint32_t fd_setup_slices(struct fd_resource *rsc);
 199 void fd_resource_resize(struct pipe_resource *prsc, uint32_t sz);
 200 void fd_resource_uncompress(struct fd_context *ctx, struct fd_resource *rsc);
 201
 202 bool fd_render_condition_check(struct pipe_context *pctx);
 203
 204 #endif /* FREEDRENO_RESOURCE_H_ */