freedreno: fix compiler warning
[mesa.git] / src / gallium / drivers / freedreno / freedreno_resource.h
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #ifndef FREEDRENO_RESOURCE_H_
28 #define FREEDRENO_RESOURCE_H_
29
30 #include "util/list.h"
31 #include "util/u_range.h"
32 #include "util/u_transfer_helper.h"
33
34 #include "freedreno_batch.h"
35 #include "freedreno_util.h"
36
37 /* Texture Layout on a3xx:
38 *
39 * Each mipmap-level contains all of it's layers (ie. all cubmap
40 * faces, all 1d/2d array elements, etc). The texture sampler is
41 * programmed with the start address of each mipmap level, and hw
42 * derives the layer offset within the level.
43 *
44 * Texture Layout on a4xx+:
45 *
46 * For cubemap and 2d array, each layer contains all of it's mipmap
47 * levels (layer_first layout).
48 *
49 * 3d textures are layed out as on a3xx, but unknown about 3d-array
50 * textures.
51 *
52 * In either case, the slice represents the per-miplevel information,
53 * but in layer_first layout it only includes the first layer, and
54 * an additional offset of (rsc->layer_size * layer) must be added.
55 */
56 struct fd_resource_slice {
57 uint32_t offset; /* offset of first layer in slice */
58 uint32_t pitch;
59 uint32_t size0; /* size of first layer in slice */
60 };
61
62 struct fd_resource {
63 struct pipe_resource base;
64 struct fd_bo *bo;
65 uint32_t cpp;
66 enum pipe_format internal_format;
67 bool layer_first; /* see above description */
68 uint32_t layer_size;
69 struct fd_resource_slice slices[MAX_MIP_LEVELS];
70 /* buffer range that has been initialized */
71 struct util_range valid_buffer_range;
72 bool valid;
73 struct renderonly_scanout *scanout;
74
75 /* reference to the resource holding stencil data for a z32_s8 texture */
76 /* TODO rename to secondary or auxiliary? */
77 struct fd_resource *stencil;
78
79 uint32_t offset;
80 uint32_t ubwc_offset;
81 uint32_t ubwc_pitch;
82 uint32_t ubwc_size;
83
84 /* bitmask of in-flight batches which reference this resource. Note
85 * that the batch doesn't hold reference to resources (but instead
86 * the fd_ringbuffer holds refs to the underlying fd_bo), but in case
87 * the resource is destroyed we need to clean up the batch's weak
88 * references to us.
89 */
90 uint32_t batch_mask;
91
92 /* reference to batch that writes this resource: */
93 struct fd_batch *write_batch;
94
95 /* Set of batches whose batch-cache key references this resource.
96 * We need to track this to know which batch-cache entries to
97 * invalidate if, for example, the resource is invalidated or
98 * shadowed.
99 */
100 uint32_t bc_batch_mask;
101
102 /* Sequence # incremented each time bo changes: */
103 uint16_t seqno;
104
105 unsigned tile_mode : 2;
106
107 /*
108 * LRZ
109 */
110 bool lrz_valid : 1;
111 uint16_t lrz_width; // for lrz clear, does this differ from lrz_pitch?
112 uint16_t lrz_height;
113 uint16_t lrz_pitch;
114 struct fd_bo *lrz;
115 };
116
117 static inline struct fd_resource *
118 fd_resource(struct pipe_resource *ptex)
119 {
120 return (struct fd_resource *)ptex;
121 }
122
123 static inline bool
124 pending(struct fd_resource *rsc, bool write)
125 {
126 /* if we have a pending GPU write, we are busy in any case: */
127 if (rsc->write_batch)
128 return true;
129
130 /* if CPU wants to write, but we are pending a GPU read, we are busy: */
131 if (write && rsc->batch_mask)
132 return true;
133
134 if (rsc->stencil && pending(rsc->stencil, write))
135 return true;
136
137 return false;
138 }
139
140 struct fd_transfer {
141 struct pipe_transfer base;
142 struct pipe_resource *staging_prsc;
143 struct pipe_box staging_box;
144 };
145
146 static inline struct fd_transfer *
147 fd_transfer(struct pipe_transfer *ptrans)
148 {
149 return (struct fd_transfer *)ptrans;
150 }
151
152 static inline struct fd_resource_slice *
153 fd_resource_slice(struct fd_resource *rsc, unsigned level)
154 {
155 assert(level <= rsc->base.last_level);
156 return &rsc->slices[level];
157 }
158
159 /* get offset for specified mipmap level and texture/array layer */
160 static inline uint32_t
161 fd_resource_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
162 {
163 struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
164 unsigned offset;
165 if (rsc->layer_first) {
166 offset = slice->offset + (rsc->layer_size * layer);
167 } else {
168 offset = slice->offset + (slice->size0 * layer);
169 }
170 debug_assert(offset < fd_bo_size(rsc->bo));
171 return offset + rsc->offset;
172 }
173
174 static inline uint32_t
175 fd_resource_ubwc_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
176 {
177 /* for now this doesn't do anything clever, but when UBWC is enabled
178 * for multi layer/level images, it will.
179 */
180 if (rsc->ubwc_size) {
181 debug_assert(level == 0);
182 debug_assert(layer == 0);
183 }
184 return rsc->ubwc_offset;
185 }
186
187 /* This might be a5xx specific, but higher mipmap levels are always linear: */
188 static inline bool
189 fd_resource_level_linear(const struct pipe_resource *prsc, int level)
190 {
191 struct fd_screen *screen = fd_screen(prsc->screen);
192 debug_assert(!is_a3xx(screen));
193
194 unsigned w = u_minify(prsc->width0, level);
195 if (w < 16)
196 return true;
197 return false;
198 }
199
200 static inline bool
201 fd_resource_ubwc_enabled(struct fd_resource *rsc, int level)
202 {
203 return rsc->ubwc_size && rsc->tile_mode &&
204 !fd_resource_level_linear(&rsc->base, level);
205 }
206
207 /* access # of samples, with 0 normalized to 1 (which is what we care about
208 * most of the time)
209 */
210 static inline unsigned
211 fd_resource_nr_samples(struct pipe_resource *prsc)
212 {
213 return MAX2(1, prsc->nr_samples);
214 }
215
216 void fd_resource_screen_init(struct pipe_screen *pscreen);
217 void fd_resource_context_init(struct pipe_context *pctx);
218
219 uint32_t fd_setup_slices(struct fd_resource *rsc);
220 void fd_resource_resize(struct pipe_resource *prsc, uint32_t sz);
221 void fd_resource_uncompress(struct fd_context *ctx, struct fd_resource *rsc);
222
223 bool fd_render_condition_check(struct pipe_context *pctx);
224
225 #endif /* FREEDRENO_RESOURCE_H_ */