0cd76f8dd50a34ccd08a84e5a13c094cbde138f4
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60 /* for fd_get_driver/device_uuid() */
61 #include "common/freedreno_uuid.h"
62
63 #include "ir3/ir3_nir.h"
64 #include "ir3/ir3_compiler.h"
65 #include "a2xx/ir2.h"
66
67 static const struct debug_named_value debug_options[] = {
68 {"msgs", FD_DBG_MSGS, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
75 {"log", FD_DBG_LOG, "Enable GPU timestamp based logging (a6xx+)"},
76 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
77 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
78 /* BIT(10) */
79 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
80 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
81 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
82 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
83 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
84 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
86 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
87 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
88 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
89 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
90 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
91 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
92 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
93 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
94 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
95 {"nofp16", FD_DBG_NOFP16, "Disable mediump precision lowering"},
96 {"nohw", FD_DBG_NOHW, "Disable submitting commands to the HW"},
97 DEBUG_NAMED_VALUE_END
98 };
99
100 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
101
102 int fd_mesa_debug = 0;
103 bool fd_binning_enabled = true;
104
105 static const char *
106 fd_screen_get_name(struct pipe_screen *pscreen)
107 {
108 static char buffer[128];
109 snprintf(buffer, sizeof(buffer), "FD%03d",
110 fd_screen(pscreen)->device_id);
111 return buffer;
112 }
113
114 static const char *
115 fd_screen_get_vendor(struct pipe_screen *pscreen)
116 {
117 return "freedreno";
118 }
119
120 static const char *
121 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
122 {
123 return "Qualcomm";
124 }
125
126
127 static uint64_t
128 fd_screen_get_timestamp(struct pipe_screen *pscreen)
129 {
130 struct fd_screen *screen = fd_screen(pscreen);
131
132 if (screen->has_timestamp) {
133 uint64_t n;
134 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
135 debug_assert(screen->max_freq > 0);
136 return n * 1000000000 / screen->max_freq;
137 } else {
138 int64_t cpu_time = os_time_get() * 1000;
139 return cpu_time + screen->cpu_gpu_time_delta;
140 }
141
142 }
143
144 static void
145 fd_screen_destroy(struct pipe_screen *pscreen)
146 {
147 struct fd_screen *screen = fd_screen(pscreen);
148
149 if (screen->pipe)
150 fd_pipe_del(screen->pipe);
151
152 if (screen->dev)
153 fd_device_del(screen->dev);
154
155 if (screen->ro)
156 FREE(screen->ro);
157
158 fd_bc_fini(&screen->batch_cache);
159 fd_gmem_screen_fini(pscreen);
160
161 slab_destroy_parent(&screen->transfer_pool);
162
163 simple_mtx_destroy(&screen->lock);
164
165 if (screen->compiler)
166 ir3_compiler_destroy(screen->compiler);
167
168 ralloc_free(screen->live_batches);
169
170 free(screen->perfcntr_queries);
171 free(screen);
172 }
173
174 /*
175 TODO either move caps to a2xx/a3xx specific code, or maybe have some
176 tables for things that differ if the delta is not too much..
177 */
178 static int
179 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
180 {
181 struct fd_screen *screen = fd_screen(pscreen);
182
183 /* this is probably not totally correct.. but it's a start: */
184 switch (param) {
185 /* Supported features (boolean caps). */
186 case PIPE_CAP_NPOT_TEXTURES:
187 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
188 case PIPE_CAP_ANISOTROPIC_FILTER:
189 case PIPE_CAP_POINT_SPRITE:
190 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
191 case PIPE_CAP_TEXTURE_SWIZZLE:
192 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
193 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
194 case PIPE_CAP_SEAMLESS_CUBE_MAP:
195 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
196 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
197 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
198 case PIPE_CAP_STRING_MARKER:
199 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
200 case PIPE_CAP_TEXTURE_BARRIER:
201 case PIPE_CAP_INVALIDATE_BUFFER:
202 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
203 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
204 case PIPE_CAP_NIR_COMPACT_ARRAYS:
205 return 1;
206
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
210 return !is_a2xx(screen);
211
212 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
213 return is_a2xx(screen);
214 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
215 return !is_a2xx(screen);
216
217 case PIPE_CAP_PACKED_UNIFORMS:
218 return !is_a2xx(screen);
219
220 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
221 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
222 return screen->has_robustness;
223
224 case PIPE_CAP_VERTEXID_NOBASE:
225 return is_a3xx(screen) || is_a4xx(screen);
226
227 case PIPE_CAP_COMPUTE:
228 return has_compute(screen);
229
230 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
231 case PIPE_CAP_PCI_GROUP:
232 case PIPE_CAP_PCI_BUS:
233 case PIPE_CAP_PCI_DEVICE:
234 case PIPE_CAP_PCI_FUNCTION:
235 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
236 return 0;
237
238 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
239 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
240 case PIPE_CAP_VERTEX_SHADER_SATURATE:
241 case PIPE_CAP_PRIMITIVE_RESTART:
242 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
243 case PIPE_CAP_TGSI_INSTANCEID:
244 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
245 case PIPE_CAP_INDEP_BLEND_ENABLE:
246 case PIPE_CAP_INDEP_BLEND_FUNC:
247 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
248 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
249 case PIPE_CAP_CONDITIONAL_RENDER:
250 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
251 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
252 case PIPE_CAP_CLIP_HALFZ:
253 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
254
255 case PIPE_CAP_FAKE_SW_MSAA:
256 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
257
258 case PIPE_CAP_TEXTURE_MULTISAMPLE:
259 return is_a5xx(screen) || is_a6xx(screen);
260
261 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
262 return is_a6xx(screen);
263
264 case PIPE_CAP_DEPTH_CLIP_DISABLE:
265 return is_a3xx(screen) || is_a4xx(screen);
266
267 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
268 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
269
270 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
271 if (is_a3xx(screen)) return 16;
272 if (is_a4xx(screen)) return 32;
273 if (is_a5xx(screen)) return 32;
274 if (is_a6xx(screen)) return 64;
275 return 0;
276 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
277 /* We could possibly emulate more by pretending 2d/rect textures and
278 * splitting high bits of index into 2nd dimension..
279 */
280 if (is_a3xx(screen)) return 8192;
281 if (is_a4xx(screen)) return 16384;
282 if (is_a5xx(screen)) return 16384;
283 if (is_a6xx(screen)) return 1 << 27;
284 return 0;
285
286 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
287 case PIPE_CAP_CUBE_MAP_ARRAY:
288 case PIPE_CAP_SAMPLER_VIEW_TARGET:
289 case PIPE_CAP_TEXTURE_QUERY_LOD:
290 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
291
292 case PIPE_CAP_START_INSTANCE:
293 /* Note that a5xx can do this, it just can't (at least with
294 * current firmware) do draw_indirect with base_instance.
295 * Since draw_indirect is needed sooner (gles31 and gl40 vs
296 * gl42), hide base_instance on a5xx. :-/
297 */
298 return is_a4xx(screen);
299
300 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
301 return 64;
302
303 case PIPE_CAP_GLSL_FEATURE_LEVEL:
304 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
305 return is_ir3(screen) ? 140 : 120;
306
307 case PIPE_CAP_ESSL_FEATURE_LEVEL:
308 /* we can probably enable 320 for a5xx too, but need to test: */
309 if (is_a6xx(screen)) return 320;
310 if (is_a5xx(screen)) return 310;
311 if (is_ir3(screen)) return 300;
312 return 120;
313
314 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
315 if (is_a6xx(screen)) return 64;
316 if (is_a5xx(screen)) return 4;
317 return 0;
318
319 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
320 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
321 return 4;
322 return 0;
323
324 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
325 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
326 return 0;
327
328 case PIPE_CAP_FBFETCH:
329 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
330 is_a6xx(screen))
331 return 1;
332 return 0;
333 case PIPE_CAP_SAMPLE_SHADING:
334 if (is_a6xx(screen)) return 1;
335 return 0;
336
337 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
338 return screen->priority_mask;
339
340 case PIPE_CAP_DRAW_INDIRECT:
341 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
342 return 1;
343 return 0;
344
345 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
346 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
347 return 1;
348 return 0;
349
350 case PIPE_CAP_LOAD_CONSTBUF:
351 /* name is confusing, but this turns on std430 packing */
352 if (is_ir3(screen))
353 return 1;
354 return 0;
355
356 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
357 return 0;
358
359 case PIPE_CAP_MAX_VIEWPORTS:
360 return 1;
361
362 case PIPE_CAP_MAX_VARYINGS:
363 return 16;
364
365 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
366 /* We don't really have a limit on this, it all goes into the main
367 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
368 * for GL_MAX_TESS_PATCH_COMPONENTS).
369 */
370 return 128;
371
372 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
373 return 64 * 1024 * 1024;
374
375 case PIPE_CAP_SHAREABLE_SHADERS:
376 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
377 /* manage the variants for these ourself, to avoid breaking precompile: */
378 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
379 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
380 if (is_ir3(screen))
381 return 1;
382 return 0;
383
384 /* Geometry shaders.. */
385 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
386 return 512;
387 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
388 return 2048;
389 case PIPE_CAP_MAX_GS_INVOCATIONS:
390 return 32;
391
392 /* Stream output. */
393 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
394 if (is_ir3(screen))
395 return PIPE_MAX_SO_BUFFERS;
396 return 0;
397 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
398 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
399 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
400 case PIPE_CAP_TGSI_TEXCOORD:
401 if (is_ir3(screen))
402 return 1;
403 return 0;
404 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
405 return 1;
406 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
407 return is_a2xx(screen);
408 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
409 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
410 if (is_ir3(screen))
411 return 16 * 4; /* should only be shader out limit? */
412 return 0;
413
414 /* Texturing. */
415 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
416 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
417 return 16384;
418 else
419 return 8192;
420 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
421 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
422 return 15;
423 else
424 return 14;
425 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
426 return 11;
427
428 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
429 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
430
431 /* Render targets. */
432 case PIPE_CAP_MAX_RENDER_TARGETS:
433 return screen->max_rts;
434 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
435 return is_a3xx(screen) ? 1 : 0;
436
437 /* Queries. */
438 case PIPE_CAP_OCCLUSION_QUERY:
439 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
440 case PIPE_CAP_QUERY_TIMESTAMP:
441 case PIPE_CAP_QUERY_TIME_ELAPSED:
442 /* only a4xx, requires new enough kernel so we know max_freq: */
443 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
444
445 case PIPE_CAP_VENDOR_ID:
446 return 0x5143;
447 case PIPE_CAP_DEVICE_ID:
448 return 0xFFFFFFFF;
449 case PIPE_CAP_ACCELERATED:
450 return 1;
451 case PIPE_CAP_VIDEO_MEMORY:
452 DBG("FINISHME: The value returned is incorrect\n");
453 return 10;
454 case PIPE_CAP_UMA:
455 return 1;
456 case PIPE_CAP_NATIVE_FENCE_FD:
457 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
458 default:
459 return u_pipe_screen_get_param_defaults(pscreen, param);
460 }
461 }
462
463 static float
464 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
465 {
466 switch (param) {
467 case PIPE_CAPF_MAX_LINE_WIDTH:
468 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
469 /* NOTE: actual value is 127.0f, but this is working around a deqp
470 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
471 * uses too small of a render target size, and gets confused when
472 * the lines start going offscreen.
473 *
474 * See: https://code.google.com/p/android/issues/detail?id=206513
475 */
476 if (fd_mesa_debug & FD_DBG_DEQP)
477 return 48.0f;
478 return 127.0f;
479 case PIPE_CAPF_MAX_POINT_WIDTH:
480 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
481 return 4092.0f;
482 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
483 return 16.0f;
484 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
485 return 15.0f;
486 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
487 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
488 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
489 return 0.0f;
490 }
491 debug_printf("unknown paramf %d\n", param);
492 return 0;
493 }
494
495 static int
496 fd_screen_get_shader_param(struct pipe_screen *pscreen,
497 enum pipe_shader_type shader,
498 enum pipe_shader_cap param)
499 {
500 struct fd_screen *screen = fd_screen(pscreen);
501
502 switch(shader)
503 {
504 case PIPE_SHADER_FRAGMENT:
505 case PIPE_SHADER_VERTEX:
506 break;
507 case PIPE_SHADER_TESS_CTRL:
508 case PIPE_SHADER_TESS_EVAL:
509 case PIPE_SHADER_GEOMETRY:
510 if (is_a6xx(screen))
511 break;
512 return 0;
513 case PIPE_SHADER_COMPUTE:
514 if (has_compute(screen))
515 break;
516 return 0;
517 default:
518 DBG("unknown shader type %d", shader);
519 return 0;
520 }
521
522 /* this is probably not totally correct.. but it's a start: */
523 switch (param) {
524 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
525 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
526 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
527 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
528 return 16384;
529 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
530 return 8; /* XXX */
531 case PIPE_SHADER_CAP_MAX_INPUTS:
532 case PIPE_SHADER_CAP_MAX_OUTPUTS:
533 return 16;
534 case PIPE_SHADER_CAP_MAX_TEMPS:
535 return 64; /* Max native temporaries. */
536 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
537 /* NOTE: seems to be limit for a3xx is actually 512 but
538 * split between VS and FS. Use lower limit of 256 to
539 * avoid getting into impossible situations:
540 */
541 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
542 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
543 return is_ir3(screen) ? 16 : 1;
544 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
545 return 1;
546 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
547 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
548 /* Technically this should be the same as for TEMP/CONST, since
549 * everything is just normal registers. This is just temporary
550 * hack until load_input/store_output handle arrays in a similar
551 * way as load_var/store_var..
552 *
553 * For tessellation stages, inputs are loaded using ldlw or ldg, both
554 * of which support indirection.
555 */
556 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
557 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
558 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
559 /* a2xx compiler doesn't handle indirect: */
560 return is_ir3(screen) ? 1 : 0;
561 case PIPE_SHADER_CAP_SUBROUTINES:
562 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
563 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
564 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
565 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
566 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
567 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
568 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
569 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
570 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
571 return 0;
572 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
573 return 1;
574 case PIPE_SHADER_CAP_INTEGERS:
575 return is_ir3(screen) ? 1 : 0;
576 case PIPE_SHADER_CAP_INT64_ATOMICS:
577 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
578 case PIPE_SHADER_CAP_INT16:
579 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
580 return 0;
581 case PIPE_SHADER_CAP_FP16:
582 return ((is_a5xx(screen) || is_a6xx(screen)) &&
583 (shader == PIPE_SHADER_COMPUTE ||
584 shader == PIPE_SHADER_FRAGMENT) &&
585 !(fd_mesa_debug & FD_DBG_NOFP16));
586 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
587 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
588 return 16;
589 case PIPE_SHADER_CAP_PREFERRED_IR:
590 return PIPE_SHADER_IR_NIR;
591 case PIPE_SHADER_CAP_SUPPORTED_IRS:
592 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
593 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
594 return 32;
595 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
596 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
597 if (is_a5xx(screen) || is_a6xx(screen)) {
598 /* a5xx (and a4xx for that matter) has one state-block
599 * for compute-shader SSBO's and another that is shared
600 * by VS/HS/DS/GS/FS.. so to simplify things for now
601 * just advertise SSBOs for FS and CS. We could possibly
602 * do what blob does, and partition the space for
603 * VS/HS/DS/GS/FS. The blob advertises:
604 *
605 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
606 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
607 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
608 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
609 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
610 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
611 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
612 *
613 * I think that way we could avoid having to patch shaders
614 * for actual SSBO indexes by using a static partitioning.
615 *
616 * Note same state block is used for images and buffers,
617 * but images also need texture state for read access
618 * (isam/isam.3d)
619 */
620 switch(shader)
621 {
622 case PIPE_SHADER_FRAGMENT:
623 case PIPE_SHADER_COMPUTE:
624 return 24;
625 default:
626 return 0;
627 }
628 }
629 return 0;
630 }
631 debug_printf("unknown shader param %d\n", param);
632 return 0;
633 }
634
635 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
636 * into per-generation backend?
637 */
638 static int
639 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
640 enum pipe_compute_cap param, void *ret)
641 {
642 struct fd_screen *screen = fd_screen(pscreen);
643 const char * const ir = "ir3";
644
645 if (!has_compute(screen))
646 return 0;
647
648 #define RET(x) do { \
649 if (ret) \
650 memcpy(ret, x, sizeof(x)); \
651 return sizeof(x); \
652 } while (0)
653
654 switch (param) {
655 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
656 // don't expose 64b pointer support yet, until ir3 supports 64b
657 // math, otherwise spir64 target is used and we get 64b pointer
658 // calculations that we can't do yet
659 // if (is_a5xx(screen))
660 // RET((uint32_t []){ 64 });
661 RET((uint32_t []){ 32 });
662
663 case PIPE_COMPUTE_CAP_IR_TARGET:
664 if (ret)
665 sprintf(ret, "%s", ir);
666 return strlen(ir) * sizeof(char);
667
668 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
669 RET((uint64_t []) { 3 });
670
671 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
672 RET(((uint64_t []) { 65535, 65535, 65535 }));
673
674 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
675 RET(((uint64_t []) { 1024, 1024, 64 }));
676
677 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
678 RET((uint64_t []) { 1024 });
679
680 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
681 RET((uint64_t []) { screen->ram_size });
682
683 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
684 RET((uint64_t []) { 32768 });
685
686 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
687 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
688 RET((uint64_t []) { 4096 });
689
690 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
691 RET((uint64_t []) { screen->ram_size });
692
693 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
694 RET((uint32_t []) { screen->max_freq / 1000000 });
695
696 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
697 RET((uint32_t []) { 9999 }); // TODO
698
699 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
700 RET((uint32_t []) { 1 });
701
702 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
703 RET((uint32_t []) { 32 }); // TODO
704
705 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
706 RET((uint64_t []) { 1024 }); // TODO
707 }
708
709 return 0;
710 }
711
712 static const void *
713 fd_get_compiler_options(struct pipe_screen *pscreen,
714 enum pipe_shader_ir ir, unsigned shader)
715 {
716 struct fd_screen *screen = fd_screen(pscreen);
717
718 if (is_ir3(screen))
719 return ir3_get_compiler_options(screen->compiler);
720
721 return ir2_get_compiler_options();
722 }
723
724 static struct disk_cache *
725 fd_get_disk_shader_cache(struct pipe_screen *pscreen)
726 {
727 struct fd_screen *screen = fd_screen(pscreen);
728
729 if (is_ir3(screen)) {
730 struct ir3_compiler *compiler = screen->compiler;
731 return compiler->disk_cache;
732 }
733
734 return NULL;
735 }
736
737 bool
738 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
739 struct fd_bo *bo,
740 struct renderonly_scanout *scanout,
741 unsigned stride,
742 struct winsys_handle *whandle)
743 {
744 whandle->stride = stride;
745
746 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
747 return fd_bo_get_name(bo, &whandle->handle) == 0;
748 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
749 if (renderonly_get_handle(scanout, whandle))
750 return true;
751 whandle->handle = fd_bo_handle(bo);
752 return true;
753 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
754 whandle->handle = fd_bo_dmabuf(bo);
755 return true;
756 } else {
757 return false;
758 }
759 }
760
761 static void
762 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
763 enum pipe_format format,
764 int max, uint64_t *modifiers,
765 unsigned int *external_only,
766 int *count)
767 {
768 struct fd_screen *screen = fd_screen(pscreen);
769 int i, num = 0;
770
771 max = MIN2(max, screen->num_supported_modifiers);
772
773 if (!max) {
774 max = screen->num_supported_modifiers;
775 external_only = NULL;
776 modifiers = NULL;
777 }
778
779 for (i = 0; i < max; i++) {
780 if (modifiers)
781 modifiers[num] = screen->supported_modifiers[i];
782
783 if (external_only)
784 external_only[num] = 0;
785
786 num++;
787 }
788
789 *count = num;
790 }
791
792 struct fd_bo *
793 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
794 struct winsys_handle *whandle)
795 {
796 struct fd_screen *screen = fd_screen(pscreen);
797 struct fd_bo *bo;
798
799 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
800 bo = fd_bo_from_name(screen->dev, whandle->handle);
801 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
802 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
803 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
804 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
805 } else {
806 DBG("Attempt to import unsupported handle type %d", whandle->type);
807 return NULL;
808 }
809
810 if (!bo) {
811 DBG("ref name 0x%08x failed", whandle->handle);
812 return NULL;
813 }
814
815 return bo;
816 }
817
818 static void _fd_fence_ref(struct pipe_screen *pscreen,
819 struct pipe_fence_handle **ptr,
820 struct pipe_fence_handle *pfence)
821 {
822 fd_fence_ref(ptr, pfence);
823 }
824
825 static void
826 fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
827 {
828 struct fd_screen *screen = fd_screen(pscreen);
829
830 fd_get_device_uuid(uuid, screen->gpu_id);
831 }
832
833 static void
834 fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
835 {
836 fd_get_driver_uuid(uuid);
837 }
838
839 struct pipe_screen *
840 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
841 {
842 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
843 struct pipe_screen *pscreen;
844 uint64_t val;
845
846 fd_mesa_debug = debug_get_option_fd_mesa_debug();
847
848 if (fd_mesa_debug & FD_DBG_NOBIN)
849 fd_binning_enabled = false;
850
851 if (!screen)
852 return NULL;
853
854 pscreen = &screen->base;
855
856 screen->dev = dev;
857 screen->refcnt = 1;
858
859 if (ro) {
860 screen->ro = renderonly_dup(ro);
861 if (!screen->ro) {
862 DBG("could not create renderonly object");
863 goto fail;
864 }
865 }
866
867 // maybe this should be in context?
868 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
869 if (!screen->pipe) {
870 DBG("could not create 3d pipe");
871 goto fail;
872 }
873
874 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
875 DBG("could not get GMEM size");
876 goto fail;
877 }
878 screen->gmemsize_bytes = val;
879
880 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
881 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
882 }
883
884 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
885 DBG("could not get device-id");
886 goto fail;
887 }
888 screen->device_id = val;
889
890 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
891 DBG("could not get gpu freq");
892 /* this limits what performance related queries are
893 * supported but is not fatal
894 */
895 screen->max_freq = 0;
896 } else {
897 screen->max_freq = val;
898 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
899 screen->has_timestamp = true;
900 }
901
902 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
903 DBG("could not get gpu-id");
904 goto fail;
905 }
906 screen->gpu_id = val;
907
908 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
909 DBG("could not get chip-id");
910 /* older kernels may not have this property: */
911 unsigned core = screen->gpu_id / 100;
912 unsigned major = (screen->gpu_id % 100) / 10;
913 unsigned minor = screen->gpu_id % 10;
914 unsigned patch = 0; /* assume the worst */
915 val = (patch & 0xff) | ((minor & 0xff) << 8) |
916 ((major & 0xff) << 16) | ((core & 0xff) << 24);
917 }
918 screen->chip_id = val;
919
920 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
921 DBG("could not get # of rings");
922 screen->priority_mask = 0;
923 } else {
924 /* # of rings equates to number of unique priority values: */
925 screen->priority_mask = (1 << val) - 1;
926 }
927
928 if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
929 screen->has_robustness = true;
930
931 struct sysinfo si;
932 sysinfo(&si);
933 screen->ram_size = si.totalram;
934
935 DBG("Pipe Info:");
936 DBG(" GPU-id: %d", screen->gpu_id);
937 DBG(" Chip-id: 0x%08x", screen->chip_id);
938 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
939
940 /* explicitly checking for GPU revisions that are known to work. This
941 * may be overly conservative for a3xx, where spoofing the gpu_id with
942 * the blob driver seems to generate identical cmdstream dumps. But
943 * on a2xx, there seem to be small differences between the GPU revs
944 * so it is probably better to actually test first on real hardware
945 * before enabling:
946 *
947 * If you have a different adreno version, feel free to add it to one
948 * of the cases below and see what happens. And if it works, please
949 * send a patch ;-)
950 */
951 switch (screen->gpu_id) {
952 case 200:
953 case 201:
954 case 205:
955 case 220:
956 fd2_screen_init(pscreen);
957 break;
958 case 305:
959 case 307:
960 case 320:
961 case 330:
962 fd3_screen_init(pscreen);
963 break;
964 case 405:
965 case 420:
966 case 430:
967 fd4_screen_init(pscreen);
968 break;
969 case 510:
970 case 530:
971 case 540:
972 fd5_screen_init(pscreen);
973 break;
974 case 618:
975 case 630:
976 case 640:
977 case 650:
978 fd6_screen_init(pscreen);
979 break;
980 default:
981 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
982 goto fail;
983 }
984
985 if (screen->gpu_id >= 600) {
986 screen->gmem_alignw = 16;
987 screen->gmem_alignh = 4;
988 screen->tile_alignw = is_a650(screen) ? 96 : 32;
989 screen->tile_alignh = 32;
990 screen->num_vsc_pipes = 32;
991 } else if (screen->gpu_id >= 500) {
992 screen->gmem_alignw = screen->tile_alignw = 64;
993 screen->gmem_alignh = screen->tile_alignh = 32;
994 screen->num_vsc_pipes = 16;
995 } else {
996 screen->gmem_alignw = screen->tile_alignw = 32;
997 screen->gmem_alignh = screen->tile_alignh = 32;
998 screen->num_vsc_pipes = 8;
999 }
1000
1001 if (fd_mesa_debug & FD_DBG_PERFC) {
1002 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
1003 &screen->num_perfcntr_groups);
1004 }
1005
1006 /* NOTE: don't enable if we have too old of a kernel to support
1007 * growable cmdstream buffers, since memory requirement for cmdstream
1008 * buffers would be too much otherwise.
1009 */
1010 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
1011 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
1012
1013 if (BATCH_DEBUG)
1014 screen->live_batches = _mesa_pointer_set_create(NULL);
1015
1016 fd_bc_init(&screen->batch_cache);
1017
1018 list_inithead(&screen->context_list);
1019
1020 (void) simple_mtx_init(&screen->lock, mtx_plain);
1021
1022 pscreen->destroy = fd_screen_destroy;
1023 pscreen->get_param = fd_screen_get_param;
1024 pscreen->get_paramf = fd_screen_get_paramf;
1025 pscreen->get_shader_param = fd_screen_get_shader_param;
1026 pscreen->get_compute_param = fd_get_compute_param;
1027 pscreen->get_compiler_options = fd_get_compiler_options;
1028 pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
1029
1030 fd_resource_screen_init(pscreen);
1031 fd_query_screen_init(pscreen);
1032 fd_gmem_screen_init(pscreen);
1033
1034 pscreen->get_name = fd_screen_get_name;
1035 pscreen->get_vendor = fd_screen_get_vendor;
1036 pscreen->get_device_vendor = fd_screen_get_device_vendor;
1037
1038 pscreen->get_timestamp = fd_screen_get_timestamp;
1039
1040 pscreen->fence_reference = _fd_fence_ref;
1041 pscreen->fence_finish = fd_fence_finish;
1042 pscreen->fence_get_fd = fd_fence_get_fd;
1043
1044 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1045
1046 pscreen->get_device_uuid = fd_screen_get_device_uuid;
1047 pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
1048
1049 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1050
1051 return pscreen;
1052
1053 fail:
1054 fd_screen_destroy(pscreen);
1055 return NULL;
1056 }