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3c0ed69a9cb13a0ad48bd49ca31f9092fbb14708
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60
61 #include "ir3/ir3_nir.h"
62 #include "a2xx/ir2.h"
63
64 /* XXX this should go away */
65 #include "state_tracker/drm_driver.h"
66
67 static const struct debug_named_value debug_options[] = {
68 {"msgs", FD_DBG_MSGS, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
75 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
76 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
77 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
78 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
79 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
80 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
81 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
82 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
83 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
84 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
86 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
87 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
88 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
89 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
90 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
91 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
92 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
93 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
94 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
95 DEBUG_NAMED_VALUE_END
96 };
97
98 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
99
100 int fd_mesa_debug = 0;
101 bool fd_binning_enabled = true;
102 static bool glsl120 = false;
103
104 static const char *
105 fd_screen_get_name(struct pipe_screen *pscreen)
106 {
107 static char buffer[128];
108 snprintf(buffer, sizeof(buffer), "FD%03d",
109 fd_screen(pscreen)->device_id);
110 return buffer;
111 }
112
113 static const char *
114 fd_screen_get_vendor(struct pipe_screen *pscreen)
115 {
116 return "freedreno";
117 }
118
119 static const char *
120 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
121 {
122 return "Qualcomm";
123 }
124
125
126 static uint64_t
127 fd_screen_get_timestamp(struct pipe_screen *pscreen)
128 {
129 struct fd_screen *screen = fd_screen(pscreen);
130
131 if (screen->has_timestamp) {
132 uint64_t n;
133 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
134 debug_assert(screen->max_freq > 0);
135 return n * 1000000000 / screen->max_freq;
136 } else {
137 int64_t cpu_time = os_time_get() * 1000;
138 return cpu_time + screen->cpu_gpu_time_delta;
139 }
140
141 }
142
143 static void
144 fd_screen_destroy(struct pipe_screen *pscreen)
145 {
146 struct fd_screen *screen = fd_screen(pscreen);
147
148 if (screen->pipe)
149 fd_pipe_del(screen->pipe);
150
151 if (screen->dev)
152 fd_device_del(screen->dev);
153
154 if (screen->ro)
155 FREE(screen->ro);
156
157 fd_bc_fini(&screen->batch_cache);
158 fd_gmem_screen_fini(pscreen);
159
160 slab_destroy_parent(&screen->transfer_pool);
161
162 mtx_destroy(&screen->lock);
163
164 ralloc_free(screen->compiler);
165
166 free(screen->perfcntr_queries);
167 free(screen);
168 }
169
170 /*
171 TODO either move caps to a2xx/a3xx specific code, or maybe have some
172 tables for things that differ if the delta is not too much..
173 */
174 static int
175 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
176 {
177 struct fd_screen *screen = fd_screen(pscreen);
178
179 /* this is probably not totally correct.. but it's a start: */
180 switch (param) {
181 /* Supported features (boolean caps). */
182 case PIPE_CAP_NPOT_TEXTURES:
183 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
184 case PIPE_CAP_ANISOTROPIC_FILTER:
185 case PIPE_CAP_POINT_SPRITE:
186 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
187 case PIPE_CAP_TEXTURE_SWIZZLE:
188 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
189 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
190 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
191 case PIPE_CAP_SEAMLESS_CUBE_MAP:
192 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
193 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
194 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
195 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
196 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
197 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
198 case PIPE_CAP_STRING_MARKER:
199 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
200 case PIPE_CAP_TEXTURE_BARRIER:
201 case PIPE_CAP_INVALIDATE_BUFFER:
202 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
203 return 1;
204
205 case PIPE_CAP_PACKED_UNIFORMS:
206 return !is_a2xx(screen);
207
208 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
209 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
210 return screen->has_robustness;
211
212 case PIPE_CAP_VERTEXID_NOBASE:
213 return is_a3xx(screen) || is_a4xx(screen);
214
215 case PIPE_CAP_COMPUTE:
216 return has_compute(screen);
217
218 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
219 case PIPE_CAP_PCI_GROUP:
220 case PIPE_CAP_PCI_BUS:
221 case PIPE_CAP_PCI_DEVICE:
222 case PIPE_CAP_PCI_FUNCTION:
223 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
224 return 0;
225
226 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
227 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
228 case PIPE_CAP_VERTEX_SHADER_SATURATE:
229 case PIPE_CAP_PRIMITIVE_RESTART:
230 case PIPE_CAP_TGSI_INSTANCEID:
231 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
232 case PIPE_CAP_INDEP_BLEND_ENABLE:
233 case PIPE_CAP_INDEP_BLEND_FUNC:
234 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
235 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
236 case PIPE_CAP_CONDITIONAL_RENDER:
237 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
238 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
239 case PIPE_CAP_CLIP_HALFZ:
240 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
241
242 case PIPE_CAP_FAKE_SW_MSAA:
243 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
244
245 case PIPE_CAP_TEXTURE_MULTISAMPLE:
246 return is_a5xx(screen) || is_a6xx(screen);
247
248 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
249 return is_a6xx(screen);
250
251 case PIPE_CAP_DEPTH_CLIP_DISABLE:
252 return is_a3xx(screen) || is_a4xx(screen);
253
254 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
255 return is_a5xx(screen) || is_a6xx(screen);
256
257 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
258 if (is_a3xx(screen)) return 16;
259 if (is_a4xx(screen)) return 32;
260 if (is_a5xx(screen)) return 32;
261 if (is_a6xx(screen)) return 64;
262 return 0;
263 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
264 /* We could possibly emulate more by pretending 2d/rect textures and
265 * splitting high bits of index into 2nd dimension..
266 */
267 if (is_a3xx(screen)) return 8192;
268 if (is_a4xx(screen)) return 16384;
269 if (is_a5xx(screen)) return 16384;
270 if (is_a6xx(screen)) return 1 << 27;
271 return 0;
272
273 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
274 case PIPE_CAP_CUBE_MAP_ARRAY:
275 case PIPE_CAP_SAMPLER_VIEW_TARGET:
276 case PIPE_CAP_TEXTURE_QUERY_LOD:
277 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
278
279 case PIPE_CAP_START_INSTANCE:
280 /* Note that a5xx can do this, it just can't (at least with
281 * current firmware) do draw_indirect with base_instance.
282 * Since draw_indirect is needed sooner (gles31 and gl40 vs
283 * gl42), hide base_instance on a5xx. :-/
284 */
285 return is_a4xx(screen);
286
287 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
288 return 64;
289
290 case PIPE_CAP_GLSL_FEATURE_LEVEL:
291 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
292 if (glsl120)
293 return 120;
294 return is_ir3(screen) ? 140 : 120;
295
296 case PIPE_CAP_ESSL_FEATURE_LEVEL:
297 /* we can probably enable 320 for a5xx too, but need to test: */
298 if (is_a6xx(screen)) return 320;
299 if (is_a5xx(screen)) return 310;
300 if (is_ir3(screen)) return 300;
301 return 120;
302
303 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
304 if (is_a6xx(screen)) return 64;
305 if (is_a5xx(screen)) return 4;
306 return 0;
307
308 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
309 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
310 return 4;
311 return 0;
312
313 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
314 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
315 return 0;
316
317 case PIPE_CAP_FBFETCH:
318 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
319 is_a6xx(screen))
320 return 1;
321 return 0;
322 case PIPE_CAP_SAMPLE_SHADING:
323 if (is_a6xx(screen)) return 1;
324 return 0;
325
326 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
327 return screen->priority_mask;
328
329 case PIPE_CAP_DRAW_INDIRECT:
330 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
331 return 1;
332 return 0;
333
334 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
335 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
336 return 1;
337 return 0;
338
339 case PIPE_CAP_LOAD_CONSTBUF:
340 /* name is confusing, but this turns on std430 packing */
341 if (is_ir3(screen))
342 return 1;
343 return 0;
344
345 case PIPE_CAP_MAX_VIEWPORTS:
346 return 1;
347
348 case PIPE_CAP_MAX_VARYINGS:
349 return 16;
350
351 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
352 /* We don't really have a limit on this, it all goes into the main
353 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
354 * for GL_MAX_TESS_PATCH_COMPONENTS).
355 */
356 return 128;
357
358 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
359 return 64 * 1024 * 1024;
360
361 case PIPE_CAP_SHAREABLE_SHADERS:
362 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
363 /* manage the variants for these ourself, to avoid breaking precompile: */
364 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
365 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
366 if (is_ir3(screen))
367 return 1;
368 return 0;
369
370 /* Geometry shaders.. */
371 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
372 return 512;
373 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
374 return 2048;
375 case PIPE_CAP_MAX_GS_INVOCATIONS:
376 return 32;
377
378 /* Stream output. */
379 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
380 if (is_ir3(screen))
381 return PIPE_MAX_SO_BUFFERS;
382 return 0;
383 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
384 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
385 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
386 if (is_ir3(screen))
387 return 1;
388 return 0;
389 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
390 return 1;
391 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
392 return is_a2xx(screen);
393 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
394 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
395 if (is_ir3(screen))
396 return 16 * 4; /* should only be shader out limit? */
397 return 0;
398
399 /* Texturing. */
400 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
401 return 1 << (MAX_MIP_LEVELS - 1);
402 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
403 return MAX_MIP_LEVELS;
404 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
405 return 11;
406
407 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
408 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
409
410 /* Render targets. */
411 case PIPE_CAP_MAX_RENDER_TARGETS:
412 return screen->max_rts;
413 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
414 return is_a3xx(screen) ? 1 : 0;
415
416 /* Queries. */
417 case PIPE_CAP_OCCLUSION_QUERY:
418 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
419 case PIPE_CAP_QUERY_TIMESTAMP:
420 case PIPE_CAP_QUERY_TIME_ELAPSED:
421 /* only a4xx, requires new enough kernel so we know max_freq: */
422 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
423
424 case PIPE_CAP_VENDOR_ID:
425 return 0x5143;
426 case PIPE_CAP_DEVICE_ID:
427 return 0xFFFFFFFF;
428 case PIPE_CAP_ACCELERATED:
429 return 1;
430 case PIPE_CAP_VIDEO_MEMORY:
431 DBG("FINISHME: The value returned is incorrect\n");
432 return 10;
433 case PIPE_CAP_UMA:
434 return 1;
435 case PIPE_CAP_NATIVE_FENCE_FD:
436 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
437 default:
438 return u_pipe_screen_get_param_defaults(pscreen, param);
439 }
440 }
441
442 static float
443 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
444 {
445 switch (param) {
446 case PIPE_CAPF_MAX_LINE_WIDTH:
447 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
448 /* NOTE: actual value is 127.0f, but this is working around a deqp
449 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
450 * uses too small of a render target size, and gets confused when
451 * the lines start going offscreen.
452 *
453 * See: https://code.google.com/p/android/issues/detail?id=206513
454 */
455 if (fd_mesa_debug & FD_DBG_DEQP)
456 return 48.0f;
457 return 127.0f;
458 case PIPE_CAPF_MAX_POINT_WIDTH:
459 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
460 return 4092.0f;
461 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
462 return 16.0f;
463 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
464 return 15.0f;
465 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
466 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
467 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
468 return 0.0f;
469 }
470 debug_printf("unknown paramf %d\n", param);
471 return 0;
472 }
473
474 static int
475 fd_screen_get_shader_param(struct pipe_screen *pscreen,
476 enum pipe_shader_type shader,
477 enum pipe_shader_cap param)
478 {
479 struct fd_screen *screen = fd_screen(pscreen);
480
481 switch(shader)
482 {
483 case PIPE_SHADER_FRAGMENT:
484 case PIPE_SHADER_VERTEX:
485 break;
486 case PIPE_SHADER_TESS_CTRL:
487 case PIPE_SHADER_TESS_EVAL:
488 case PIPE_SHADER_GEOMETRY:
489 if (is_a6xx(screen))
490 break;
491 return 0;
492 case PIPE_SHADER_COMPUTE:
493 if (has_compute(screen))
494 break;
495 return 0;
496 default:
497 DBG("unknown shader type %d", shader);
498 return 0;
499 }
500
501 /* this is probably not totally correct.. but it's a start: */
502 switch (param) {
503 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
504 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
505 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
506 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
507 return 16384;
508 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
509 return 8; /* XXX */
510 case PIPE_SHADER_CAP_MAX_INPUTS:
511 case PIPE_SHADER_CAP_MAX_OUTPUTS:
512 return 16;
513 case PIPE_SHADER_CAP_MAX_TEMPS:
514 return 64; /* Max native temporaries. */
515 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
516 /* NOTE: seems to be limit for a3xx is actually 512 but
517 * split between VS and FS. Use lower limit of 256 to
518 * avoid getting into impossible situations:
519 */
520 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
521 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
522 return is_ir3(screen) ? 16 : 1;
523 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
524 return 1;
525 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
526 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
527 /* Technically this should be the same as for TEMP/CONST, since
528 * everything is just normal registers. This is just temporary
529 * hack until load_input/store_output handle arrays in a similar
530 * way as load_var/store_var..
531 *
532 * For tessellation stages, inputs are loaded using ldlw or ldg, both
533 * of which support indirection.
534 */
535 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
536 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
537 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
538 /* a2xx compiler doesn't handle indirect: */
539 return is_ir3(screen) ? 1 : 0;
540 case PIPE_SHADER_CAP_SUBROUTINES:
541 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
542 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
543 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
544 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
545 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
546 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
547 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
548 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
549 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
550 return 0;
551 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
552 return 1;
553 case PIPE_SHADER_CAP_INTEGERS:
554 if (glsl120)
555 return 0;
556 return is_ir3(screen) ? 1 : 0;
557 case PIPE_SHADER_CAP_INT64_ATOMICS:
558 return 0;
559 case PIPE_SHADER_CAP_FP16:
560 return 0;
561 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
562 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
563 return 16;
564 case PIPE_SHADER_CAP_PREFERRED_IR:
565 return PIPE_SHADER_IR_NIR;
566 case PIPE_SHADER_CAP_SUPPORTED_IRS:
567 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
568 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
569 return 32;
570 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
571 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
572 if (is_a5xx(screen) || is_a6xx(screen)) {
573 /* a5xx (and a4xx for that matter) has one state-block
574 * for compute-shader SSBO's and another that is shared
575 * by VS/HS/DS/GS/FS.. so to simplify things for now
576 * just advertise SSBOs for FS and CS. We could possibly
577 * do what blob does, and partition the space for
578 * VS/HS/DS/GS/FS. The blob advertises:
579 *
580 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
581 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
582 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
583 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
584 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
585 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
586 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
587 *
588 * I think that way we could avoid having to patch shaders
589 * for actual SSBO indexes by using a static partitioning.
590 *
591 * Note same state block is used for images and buffers,
592 * but images also need texture state for read access
593 * (isam/isam.3d)
594 */
595 switch(shader)
596 {
597 case PIPE_SHADER_FRAGMENT:
598 case PIPE_SHADER_COMPUTE:
599 return 24;
600 default:
601 return 0;
602 }
603 }
604 return 0;
605 }
606 debug_printf("unknown shader param %d\n", param);
607 return 0;
608 }
609
610 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
611 * into per-generation backend?
612 */
613 static int
614 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
615 enum pipe_compute_cap param, void *ret)
616 {
617 struct fd_screen *screen = fd_screen(pscreen);
618 const char * const ir = "ir3";
619
620 if (!has_compute(screen))
621 return 0;
622
623 #define RET(x) do { \
624 if (ret) \
625 memcpy(ret, x, sizeof(x)); \
626 return sizeof(x); \
627 } while (0)
628
629 switch (param) {
630 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
631 // don't expose 64b pointer support yet, until ir3 supports 64b
632 // math, otherwise spir64 target is used and we get 64b pointer
633 // calculations that we can't do yet
634 // if (is_a5xx(screen))
635 // RET((uint32_t []){ 64 });
636 RET((uint32_t []){ 32 });
637
638 case PIPE_COMPUTE_CAP_IR_TARGET:
639 if (ret)
640 sprintf(ret, "%s", ir);
641 return strlen(ir) * sizeof(char);
642
643 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
644 RET((uint64_t []) { 3 });
645
646 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
647 RET(((uint64_t []) { 65535, 65535, 65535 }));
648
649 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
650 RET(((uint64_t []) { 1024, 1024, 64 }));
651
652 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
653 RET((uint64_t []) { 1024 });
654
655 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
656 RET((uint64_t []) { screen->ram_size });
657
658 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
659 RET((uint64_t []) { 32768 });
660
661 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
662 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
663 RET((uint64_t []) { 4096 });
664
665 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
666 RET((uint64_t []) { screen->ram_size });
667
668 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
669 RET((uint32_t []) { screen->max_freq / 1000000 });
670
671 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
672 RET((uint32_t []) { 9999 }); // TODO
673
674 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
675 RET((uint32_t []) { 1 });
676
677 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
678 RET((uint32_t []) { 32 }); // TODO
679
680 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
681 RET((uint64_t []) { 1024 }); // TODO
682 }
683
684 return 0;
685 }
686
687 static const void *
688 fd_get_compiler_options(struct pipe_screen *pscreen,
689 enum pipe_shader_ir ir, unsigned shader)
690 {
691 struct fd_screen *screen = fd_screen(pscreen);
692
693 if (is_ir3(screen))
694 return ir3_get_compiler_options(screen->compiler);
695
696 return ir2_get_compiler_options();
697 }
698
699 bool
700 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
701 struct fd_bo *bo,
702 struct renderonly_scanout *scanout,
703 unsigned stride,
704 struct winsys_handle *whandle)
705 {
706 whandle->stride = stride;
707
708 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
709 return fd_bo_get_name(bo, &whandle->handle) == 0;
710 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
711 if (renderonly_get_handle(scanout, whandle))
712 return true;
713 whandle->handle = fd_bo_handle(bo);
714 return true;
715 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
716 whandle->handle = fd_bo_dmabuf(bo);
717 return true;
718 } else {
719 return false;
720 }
721 }
722
723 static void
724 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
725 enum pipe_format format,
726 int max, uint64_t *modifiers,
727 unsigned int *external_only,
728 int *count)
729 {
730 struct fd_screen *screen = fd_screen(pscreen);
731 int i, num = 0;
732
733 max = MIN2(max, screen->num_supported_modifiers);
734
735 if (!max) {
736 max = screen->num_supported_modifiers;
737 external_only = NULL;
738 modifiers = NULL;
739 }
740
741 for (i = 0; i < max; i++) {
742 if (modifiers)
743 modifiers[num] = screen->supported_modifiers[i];
744
745 if (external_only)
746 external_only[num] = 0;
747
748 num++;
749 }
750
751 *count = num;
752 }
753
754 struct fd_bo *
755 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
756 struct winsys_handle *whandle)
757 {
758 struct fd_screen *screen = fd_screen(pscreen);
759 struct fd_bo *bo;
760
761 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
762 bo = fd_bo_from_name(screen->dev, whandle->handle);
763 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
764 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
765 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
766 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
767 } else {
768 DBG("Attempt to import unsupported handle type %d", whandle->type);
769 return NULL;
770 }
771
772 if (!bo) {
773 DBG("ref name 0x%08x failed", whandle->handle);
774 return NULL;
775 }
776
777 return bo;
778 }
779
780 static void _fd_fence_ref(struct pipe_screen *pscreen,
781 struct pipe_fence_handle **ptr,
782 struct pipe_fence_handle *pfence)
783 {
784 fd_fence_ref(ptr, pfence);
785 }
786
787 struct pipe_screen *
788 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
789 {
790 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
791 struct pipe_screen *pscreen;
792 uint64_t val;
793
794 fd_mesa_debug = debug_get_option_fd_mesa_debug();
795
796 if (fd_mesa_debug & FD_DBG_NOBIN)
797 fd_binning_enabled = false;
798
799 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
800
801 if (!screen)
802 return NULL;
803
804 pscreen = &screen->base;
805
806 screen->dev = dev;
807 screen->refcnt = 1;
808
809 if (ro) {
810 screen->ro = renderonly_dup(ro);
811 if (!screen->ro) {
812 DBG("could not create renderonly object");
813 goto fail;
814 }
815 }
816
817 // maybe this should be in context?
818 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
819 if (!screen->pipe) {
820 DBG("could not create 3d pipe");
821 goto fail;
822 }
823
824 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
825 DBG("could not get GMEM size");
826 goto fail;
827 }
828 screen->gmemsize_bytes = val;
829
830 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
831 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
832 }
833
834 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
835 DBG("could not get device-id");
836 goto fail;
837 }
838 screen->device_id = val;
839
840 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
841 DBG("could not get gpu freq");
842 /* this limits what performance related queries are
843 * supported but is not fatal
844 */
845 screen->max_freq = 0;
846 } else {
847 screen->max_freq = val;
848 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
849 screen->has_timestamp = true;
850 }
851
852 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
853 DBG("could not get gpu-id");
854 goto fail;
855 }
856 screen->gpu_id = val;
857
858 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
859 DBG("could not get chip-id");
860 /* older kernels may not have this property: */
861 unsigned core = screen->gpu_id / 100;
862 unsigned major = (screen->gpu_id % 100) / 10;
863 unsigned minor = screen->gpu_id % 10;
864 unsigned patch = 0; /* assume the worst */
865 val = (patch & 0xff) | ((minor & 0xff) << 8) |
866 ((major & 0xff) << 16) | ((core & 0xff) << 24);
867 }
868 screen->chip_id = val;
869
870 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
871 DBG("could not get # of rings");
872 screen->priority_mask = 0;
873 } else {
874 /* # of rings equates to number of unique priority values: */
875 screen->priority_mask = (1 << val) - 1;
876 }
877
878 if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
879 (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
880 screen->has_robustness = val;
881 }
882
883 struct sysinfo si;
884 sysinfo(&si);
885 screen->ram_size = si.totalram;
886
887 DBG("Pipe Info:");
888 DBG(" GPU-id: %d", screen->gpu_id);
889 DBG(" Chip-id: 0x%08x", screen->chip_id);
890 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
891
892 /* explicitly checking for GPU revisions that are known to work. This
893 * may be overly conservative for a3xx, where spoofing the gpu_id with
894 * the blob driver seems to generate identical cmdstream dumps. But
895 * on a2xx, there seem to be small differences between the GPU revs
896 * so it is probably better to actually test first on real hardware
897 * before enabling:
898 *
899 * If you have a different adreno version, feel free to add it to one
900 * of the cases below and see what happens. And if it works, please
901 * send a patch ;-)
902 */
903 switch (screen->gpu_id) {
904 case 200:
905 case 201:
906 case 205:
907 case 220:
908 fd2_screen_init(pscreen);
909 break;
910 case 305:
911 case 307:
912 case 320:
913 case 330:
914 fd3_screen_init(pscreen);
915 break;
916 case 420:
917 case 430:
918 fd4_screen_init(pscreen);
919 break;
920 case 510:
921 case 530:
922 case 540:
923 fd5_screen_init(pscreen);
924 break;
925 case 618:
926 case 630:
927 case 640:
928 fd6_screen_init(pscreen);
929 break;
930 default:
931 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
932 goto fail;
933 }
934
935 if (screen->gpu_id >= 600) {
936 screen->gmem_alignw = 32;
937 screen->gmem_alignh = 32;
938 screen->num_vsc_pipes = 32;
939 } else if (screen->gpu_id >= 500) {
940 screen->gmem_alignw = 64;
941 screen->gmem_alignh = 32;
942 screen->num_vsc_pipes = 16;
943 } else {
944 screen->gmem_alignw = 32;
945 screen->gmem_alignh = 32;
946 screen->num_vsc_pipes = 8;
947 }
948
949 if (fd_mesa_debug & FD_DBG_PERFC) {
950 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
951 &screen->num_perfcntr_groups);
952 }
953
954 /* NOTE: don't enable if we have too old of a kernel to support
955 * growable cmdstream buffers, since memory requirement for cmdstream
956 * buffers would be too much otherwise.
957 */
958 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
959 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
960
961 fd_bc_init(&screen->batch_cache);
962
963 (void) mtx_init(&screen->lock, mtx_plain);
964
965 pscreen->destroy = fd_screen_destroy;
966 pscreen->get_param = fd_screen_get_param;
967 pscreen->get_paramf = fd_screen_get_paramf;
968 pscreen->get_shader_param = fd_screen_get_shader_param;
969 pscreen->get_compute_param = fd_get_compute_param;
970 pscreen->get_compiler_options = fd_get_compiler_options;
971
972 fd_resource_screen_init(pscreen);
973 fd_query_screen_init(pscreen);
974 fd_gmem_screen_init(pscreen);
975
976 pscreen->get_name = fd_screen_get_name;
977 pscreen->get_vendor = fd_screen_get_vendor;
978 pscreen->get_device_vendor = fd_screen_get_device_vendor;
979
980 pscreen->get_timestamp = fd_screen_get_timestamp;
981
982 pscreen->fence_reference = _fd_fence_ref;
983 pscreen->fence_finish = fd_fence_finish;
984 pscreen->fence_get_fd = fd_fence_get_fd;
985
986 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
987
988 if (!screen->supported_modifiers) {
989 static const uint64_t supported_modifiers[] = {
990 DRM_FORMAT_MOD_LINEAR,
991 };
992
993 screen->supported_modifiers = supported_modifiers;
994 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
995 }
996
997 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
998
999 return pscreen;
1000
1001 fail:
1002 fd_screen_destroy(pscreen);
1003 return NULL;
1004 }