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gallium: add shader caps INT16 and FP16_DERIVATIVES
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60
61 #include "ir3/ir3_nir.h"
62 #include "a2xx/ir2.h"
63
64 static const struct debug_named_value debug_options[] = {
65 {"msgs", FD_DBG_MSGS, "Print debug messages"},
66 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
67 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
68 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
69 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
70 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
71 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
72 {"log", FD_DBG_LOG, "Enable GPU timestamp based logging (a6xx+)"},
73 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
74 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
75 /* BIT(10) */
76 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
77 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
78 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
79 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
83 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
84 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
85 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
86 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
87 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
88 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
89 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
90 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
91 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
92 {"nofp16", FD_DBG_NOFP16, "Disable mediump precision lowering"},
93 {"nohw", FD_DBG_NOHW, "Disable submitting commands to the HW"},
94 DEBUG_NAMED_VALUE_END
95 };
96
97 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
98
99 int fd_mesa_debug = 0;
100 bool fd_binning_enabled = true;
101
102 static const char *
103 fd_screen_get_name(struct pipe_screen *pscreen)
104 {
105 static char buffer[128];
106 snprintf(buffer, sizeof(buffer), "FD%03d",
107 fd_screen(pscreen)->device_id);
108 return buffer;
109 }
110
111 static const char *
112 fd_screen_get_vendor(struct pipe_screen *pscreen)
113 {
114 return "freedreno";
115 }
116
117 static const char *
118 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
119 {
120 return "Qualcomm";
121 }
122
123
124 static uint64_t
125 fd_screen_get_timestamp(struct pipe_screen *pscreen)
126 {
127 struct fd_screen *screen = fd_screen(pscreen);
128
129 if (screen->has_timestamp) {
130 uint64_t n;
131 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
132 debug_assert(screen->max_freq > 0);
133 return n * 1000000000 / screen->max_freq;
134 } else {
135 int64_t cpu_time = os_time_get() * 1000;
136 return cpu_time + screen->cpu_gpu_time_delta;
137 }
138
139 }
140
141 static void
142 fd_screen_destroy(struct pipe_screen *pscreen)
143 {
144 struct fd_screen *screen = fd_screen(pscreen);
145
146 if (screen->pipe)
147 fd_pipe_del(screen->pipe);
148
149 if (screen->dev)
150 fd_device_del(screen->dev);
151
152 if (screen->ro)
153 FREE(screen->ro);
154
155 fd_bc_fini(&screen->batch_cache);
156 fd_gmem_screen_fini(pscreen);
157
158 slab_destroy_parent(&screen->transfer_pool);
159
160 simple_mtx_destroy(&screen->lock);
161
162 ralloc_free(screen->compiler);
163 ralloc_free(screen->live_batches);
164
165 free(screen->perfcntr_queries);
166 free(screen);
167 }
168
169 /*
170 TODO either move caps to a2xx/a3xx specific code, or maybe have some
171 tables for things that differ if the delta is not too much..
172 */
173 static int
174 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
175 {
176 struct fd_screen *screen = fd_screen(pscreen);
177
178 /* this is probably not totally correct.. but it's a start: */
179 switch (param) {
180 /* Supported features (boolean caps). */
181 case PIPE_CAP_NPOT_TEXTURES:
182 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_POINT_SPRITE:
185 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
186 case PIPE_CAP_TEXTURE_SWIZZLE:
187 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
188 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
189 case PIPE_CAP_SEAMLESS_CUBE_MAP:
190 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
191 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
192 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
193 case PIPE_CAP_STRING_MARKER:
194 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
195 case PIPE_CAP_TEXTURE_BARRIER:
196 case PIPE_CAP_INVALIDATE_BUFFER:
197 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
198 return 1;
199
200 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
201 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
202 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
203 return !is_a2xx(screen);
204
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
206 return is_a2xx(screen);
207 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
208 return !is_a2xx(screen);
209
210 case PIPE_CAP_PACKED_UNIFORMS:
211 return !is_a2xx(screen);
212
213 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
214 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
215 return screen->has_robustness;
216
217 case PIPE_CAP_VERTEXID_NOBASE:
218 return is_a3xx(screen) || is_a4xx(screen);
219
220 case PIPE_CAP_COMPUTE:
221 return has_compute(screen);
222
223 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
224 case PIPE_CAP_PCI_GROUP:
225 case PIPE_CAP_PCI_BUS:
226 case PIPE_CAP_PCI_DEVICE:
227 case PIPE_CAP_PCI_FUNCTION:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
229 return 0;
230
231 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
232 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
233 case PIPE_CAP_VERTEX_SHADER_SATURATE:
234 case PIPE_CAP_PRIMITIVE_RESTART:
235 case PIPE_CAP_TGSI_INSTANCEID:
236 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
237 case PIPE_CAP_INDEP_BLEND_ENABLE:
238 case PIPE_CAP_INDEP_BLEND_FUNC:
239 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
240 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
241 case PIPE_CAP_CONDITIONAL_RENDER:
242 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
243 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
244 case PIPE_CAP_CLIP_HALFZ:
245 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
246
247 case PIPE_CAP_FAKE_SW_MSAA:
248 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
249
250 case PIPE_CAP_TEXTURE_MULTISAMPLE:
251 return is_a5xx(screen) || is_a6xx(screen);
252
253 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
254 return is_a6xx(screen);
255
256 case PIPE_CAP_DEPTH_CLIP_DISABLE:
257 return is_a3xx(screen) || is_a4xx(screen);
258
259 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
260 return is_a5xx(screen) || is_a6xx(screen);
261
262 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
263 if (is_a3xx(screen)) return 16;
264 if (is_a4xx(screen)) return 32;
265 if (is_a5xx(screen)) return 32;
266 if (is_a6xx(screen)) return 64;
267 return 0;
268 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
269 /* We could possibly emulate more by pretending 2d/rect textures and
270 * splitting high bits of index into 2nd dimension..
271 */
272 if (is_a3xx(screen)) return 8192;
273 if (is_a4xx(screen)) return 16384;
274 if (is_a5xx(screen)) return 16384;
275 if (is_a6xx(screen)) return 1 << 27;
276 return 0;
277
278 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
279 case PIPE_CAP_CUBE_MAP_ARRAY:
280 case PIPE_CAP_SAMPLER_VIEW_TARGET:
281 case PIPE_CAP_TEXTURE_QUERY_LOD:
282 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
283
284 case PIPE_CAP_START_INSTANCE:
285 /* Note that a5xx can do this, it just can't (at least with
286 * current firmware) do draw_indirect with base_instance.
287 * Since draw_indirect is needed sooner (gles31 and gl40 vs
288 * gl42), hide base_instance on a5xx. :-/
289 */
290 return is_a4xx(screen);
291
292 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
293 return 64;
294
295 case PIPE_CAP_GLSL_FEATURE_LEVEL:
296 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
297 return is_ir3(screen) ? 140 : 120;
298
299 case PIPE_CAP_ESSL_FEATURE_LEVEL:
300 /* we can probably enable 320 for a5xx too, but need to test: */
301 if (is_a6xx(screen)) return 320;
302 if (is_a5xx(screen)) return 310;
303 if (is_ir3(screen)) return 300;
304 return 120;
305
306 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
307 if (is_a6xx(screen)) return 64;
308 if (is_a5xx(screen)) return 4;
309 return 0;
310
311 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
312 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
313 return 4;
314 return 0;
315
316 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
317 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
318 return 0;
319
320 case PIPE_CAP_FBFETCH:
321 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
322 is_a6xx(screen))
323 return 1;
324 return 0;
325 case PIPE_CAP_SAMPLE_SHADING:
326 if (is_a6xx(screen)) return 1;
327 return 0;
328
329 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
330 return screen->priority_mask;
331
332 case PIPE_CAP_DRAW_INDIRECT:
333 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
334 return 1;
335 return 0;
336
337 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
338 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
339 return 1;
340 return 0;
341
342 case PIPE_CAP_LOAD_CONSTBUF:
343 /* name is confusing, but this turns on std430 packing */
344 if (is_ir3(screen))
345 return 1;
346 return 0;
347
348 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
349 return 0;
350
351 case PIPE_CAP_MAX_VIEWPORTS:
352 return 1;
353
354 case PIPE_CAP_MAX_VARYINGS:
355 return 16;
356
357 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
358 /* We don't really have a limit on this, it all goes into the main
359 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
360 * for GL_MAX_TESS_PATCH_COMPONENTS).
361 */
362 return 128;
363
364 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
365 return 64 * 1024 * 1024;
366
367 case PIPE_CAP_SHAREABLE_SHADERS:
368 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
369 /* manage the variants for these ourself, to avoid breaking precompile: */
370 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
371 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
372 if (is_ir3(screen))
373 return 1;
374 return 0;
375
376 /* Geometry shaders.. */
377 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
378 return 512;
379 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
380 return 2048;
381 case PIPE_CAP_MAX_GS_INVOCATIONS:
382 return 32;
383
384 /* Stream output. */
385 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
386 if (is_ir3(screen))
387 return PIPE_MAX_SO_BUFFERS;
388 return 0;
389 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
390 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
391 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
392 if (is_ir3(screen))
393 return 1;
394 return 0;
395 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
396 return 1;
397 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
398 return is_a2xx(screen);
399 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
400 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
401 if (is_ir3(screen))
402 return 16 * 4; /* should only be shader out limit? */
403 return 0;
404
405 /* Texturing. */
406 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
407 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
408 return 16384;
409 else
410 return 8192;
411 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
412 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
413 return 15;
414 else
415 return 14;
416 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
417 return 11;
418
419 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
420 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
421
422 /* Render targets. */
423 case PIPE_CAP_MAX_RENDER_TARGETS:
424 return screen->max_rts;
425 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
426 return is_a3xx(screen) ? 1 : 0;
427
428 /* Queries. */
429 case PIPE_CAP_OCCLUSION_QUERY:
430 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
431 case PIPE_CAP_QUERY_TIMESTAMP:
432 case PIPE_CAP_QUERY_TIME_ELAPSED:
433 /* only a4xx, requires new enough kernel so we know max_freq: */
434 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
435
436 case PIPE_CAP_VENDOR_ID:
437 return 0x5143;
438 case PIPE_CAP_DEVICE_ID:
439 return 0xFFFFFFFF;
440 case PIPE_CAP_ACCELERATED:
441 return 1;
442 case PIPE_CAP_VIDEO_MEMORY:
443 DBG("FINISHME: The value returned is incorrect\n");
444 return 10;
445 case PIPE_CAP_UMA:
446 return 1;
447 case PIPE_CAP_NATIVE_FENCE_FD:
448 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
449 default:
450 return u_pipe_screen_get_param_defaults(pscreen, param);
451 }
452 }
453
454 static float
455 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
456 {
457 switch (param) {
458 case PIPE_CAPF_MAX_LINE_WIDTH:
459 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
460 /* NOTE: actual value is 127.0f, but this is working around a deqp
461 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
462 * uses too small of a render target size, and gets confused when
463 * the lines start going offscreen.
464 *
465 * See: https://code.google.com/p/android/issues/detail?id=206513
466 */
467 if (fd_mesa_debug & FD_DBG_DEQP)
468 return 48.0f;
469 return 127.0f;
470 case PIPE_CAPF_MAX_POINT_WIDTH:
471 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
472 return 4092.0f;
473 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
474 return 16.0f;
475 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
476 return 15.0f;
477 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
478 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
479 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
480 return 0.0f;
481 }
482 debug_printf("unknown paramf %d\n", param);
483 return 0;
484 }
485
486 static int
487 fd_screen_get_shader_param(struct pipe_screen *pscreen,
488 enum pipe_shader_type shader,
489 enum pipe_shader_cap param)
490 {
491 struct fd_screen *screen = fd_screen(pscreen);
492
493 switch(shader)
494 {
495 case PIPE_SHADER_FRAGMENT:
496 case PIPE_SHADER_VERTEX:
497 break;
498 case PIPE_SHADER_TESS_CTRL:
499 case PIPE_SHADER_TESS_EVAL:
500 case PIPE_SHADER_GEOMETRY:
501 if (is_a6xx(screen))
502 break;
503 return 0;
504 case PIPE_SHADER_COMPUTE:
505 if (has_compute(screen))
506 break;
507 return 0;
508 default:
509 DBG("unknown shader type %d", shader);
510 return 0;
511 }
512
513 /* this is probably not totally correct.. but it's a start: */
514 switch (param) {
515 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
516 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
517 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
518 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
519 return 16384;
520 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
521 return 8; /* XXX */
522 case PIPE_SHADER_CAP_MAX_INPUTS:
523 case PIPE_SHADER_CAP_MAX_OUTPUTS:
524 return 16;
525 case PIPE_SHADER_CAP_MAX_TEMPS:
526 return 64; /* Max native temporaries. */
527 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
528 /* NOTE: seems to be limit for a3xx is actually 512 but
529 * split between VS and FS. Use lower limit of 256 to
530 * avoid getting into impossible situations:
531 */
532 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
533 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
534 return is_ir3(screen) ? 16 : 1;
535 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
536 return 1;
537 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
538 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
539 /* Technically this should be the same as for TEMP/CONST, since
540 * everything is just normal registers. This is just temporary
541 * hack until load_input/store_output handle arrays in a similar
542 * way as load_var/store_var..
543 *
544 * For tessellation stages, inputs are loaded using ldlw or ldg, both
545 * of which support indirection.
546 */
547 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
548 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
549 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
550 /* a2xx compiler doesn't handle indirect: */
551 return is_ir3(screen) ? 1 : 0;
552 case PIPE_SHADER_CAP_SUBROUTINES:
553 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
554 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
555 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
556 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
557 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
558 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
559 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
560 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
561 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
562 return 0;
563 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
564 return 1;
565 case PIPE_SHADER_CAP_INTEGERS:
566 return is_ir3(screen) ? 1 : 0;
567 case PIPE_SHADER_CAP_INT64_ATOMICS:
568 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
569 case PIPE_SHADER_CAP_INT16:
570 return 0;
571 case PIPE_SHADER_CAP_FP16:
572 return ((is_a5xx(screen) || is_a6xx(screen)) &&
573 (shader == PIPE_SHADER_COMPUTE ||
574 shader == PIPE_SHADER_FRAGMENT) &&
575 !(fd_mesa_debug & FD_DBG_NOFP16));
576 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
577 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
578 return 16;
579 case PIPE_SHADER_CAP_PREFERRED_IR:
580 return PIPE_SHADER_IR_NIR;
581 case PIPE_SHADER_CAP_SUPPORTED_IRS:
582 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
583 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
584 return 32;
585 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
586 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
587 if (is_a5xx(screen) || is_a6xx(screen)) {
588 /* a5xx (and a4xx for that matter) has one state-block
589 * for compute-shader SSBO's and another that is shared
590 * by VS/HS/DS/GS/FS.. so to simplify things for now
591 * just advertise SSBOs for FS and CS. We could possibly
592 * do what blob does, and partition the space for
593 * VS/HS/DS/GS/FS. The blob advertises:
594 *
595 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
596 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
597 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
598 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
599 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
600 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
601 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
602 *
603 * I think that way we could avoid having to patch shaders
604 * for actual SSBO indexes by using a static partitioning.
605 *
606 * Note same state block is used for images and buffers,
607 * but images also need texture state for read access
608 * (isam/isam.3d)
609 */
610 switch(shader)
611 {
612 case PIPE_SHADER_FRAGMENT:
613 case PIPE_SHADER_COMPUTE:
614 return 24;
615 default:
616 return 0;
617 }
618 }
619 return 0;
620 }
621 debug_printf("unknown shader param %d\n", param);
622 return 0;
623 }
624
625 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
626 * into per-generation backend?
627 */
628 static int
629 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
630 enum pipe_compute_cap param, void *ret)
631 {
632 struct fd_screen *screen = fd_screen(pscreen);
633 const char * const ir = "ir3";
634
635 if (!has_compute(screen))
636 return 0;
637
638 #define RET(x) do { \
639 if (ret) \
640 memcpy(ret, x, sizeof(x)); \
641 return sizeof(x); \
642 } while (0)
643
644 switch (param) {
645 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
646 // don't expose 64b pointer support yet, until ir3 supports 64b
647 // math, otherwise spir64 target is used and we get 64b pointer
648 // calculations that we can't do yet
649 // if (is_a5xx(screen))
650 // RET((uint32_t []){ 64 });
651 RET((uint32_t []){ 32 });
652
653 case PIPE_COMPUTE_CAP_IR_TARGET:
654 if (ret)
655 sprintf(ret, "%s", ir);
656 return strlen(ir) * sizeof(char);
657
658 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
659 RET((uint64_t []) { 3 });
660
661 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
662 RET(((uint64_t []) { 65535, 65535, 65535 }));
663
664 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
665 RET(((uint64_t []) { 1024, 1024, 64 }));
666
667 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
668 RET((uint64_t []) { 1024 });
669
670 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
671 RET((uint64_t []) { screen->ram_size });
672
673 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
674 RET((uint64_t []) { 32768 });
675
676 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
677 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
678 RET((uint64_t []) { 4096 });
679
680 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
681 RET((uint64_t []) { screen->ram_size });
682
683 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
684 RET((uint32_t []) { screen->max_freq / 1000000 });
685
686 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
687 RET((uint32_t []) { 9999 }); // TODO
688
689 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
690 RET((uint32_t []) { 1 });
691
692 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
693 RET((uint32_t []) { 32 }); // TODO
694
695 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
696 RET((uint64_t []) { 1024 }); // TODO
697 }
698
699 return 0;
700 }
701
702 static const void *
703 fd_get_compiler_options(struct pipe_screen *pscreen,
704 enum pipe_shader_ir ir, unsigned shader)
705 {
706 struct fd_screen *screen = fd_screen(pscreen);
707
708 if (is_ir3(screen))
709 return ir3_get_compiler_options(screen->compiler);
710
711 return ir2_get_compiler_options();
712 }
713
714 bool
715 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
716 struct fd_bo *bo,
717 struct renderonly_scanout *scanout,
718 unsigned stride,
719 struct winsys_handle *whandle)
720 {
721 whandle->stride = stride;
722
723 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
724 return fd_bo_get_name(bo, &whandle->handle) == 0;
725 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
726 if (renderonly_get_handle(scanout, whandle))
727 return true;
728 whandle->handle = fd_bo_handle(bo);
729 return true;
730 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
731 whandle->handle = fd_bo_dmabuf(bo);
732 return true;
733 } else {
734 return false;
735 }
736 }
737
738 static void
739 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
740 enum pipe_format format,
741 int max, uint64_t *modifiers,
742 unsigned int *external_only,
743 int *count)
744 {
745 struct fd_screen *screen = fd_screen(pscreen);
746 int i, num = 0;
747
748 max = MIN2(max, screen->num_supported_modifiers);
749
750 if (!max) {
751 max = screen->num_supported_modifiers;
752 external_only = NULL;
753 modifiers = NULL;
754 }
755
756 for (i = 0; i < max; i++) {
757 if (modifiers)
758 modifiers[num] = screen->supported_modifiers[i];
759
760 if (external_only)
761 external_only[num] = 0;
762
763 num++;
764 }
765
766 *count = num;
767 }
768
769 struct fd_bo *
770 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
771 struct winsys_handle *whandle)
772 {
773 struct fd_screen *screen = fd_screen(pscreen);
774 struct fd_bo *bo;
775
776 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
777 bo = fd_bo_from_name(screen->dev, whandle->handle);
778 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
779 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
780 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
781 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
782 } else {
783 DBG("Attempt to import unsupported handle type %d", whandle->type);
784 return NULL;
785 }
786
787 if (!bo) {
788 DBG("ref name 0x%08x failed", whandle->handle);
789 return NULL;
790 }
791
792 return bo;
793 }
794
795 static void _fd_fence_ref(struct pipe_screen *pscreen,
796 struct pipe_fence_handle **ptr,
797 struct pipe_fence_handle *pfence)
798 {
799 fd_fence_ref(ptr, pfence);
800 }
801
802 struct pipe_screen *
803 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
804 {
805 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
806 struct pipe_screen *pscreen;
807 uint64_t val;
808
809 fd_mesa_debug = debug_get_option_fd_mesa_debug();
810
811 if (fd_mesa_debug & FD_DBG_NOBIN)
812 fd_binning_enabled = false;
813
814 if (!screen)
815 return NULL;
816
817 pscreen = &screen->base;
818
819 screen->dev = dev;
820 screen->refcnt = 1;
821
822 if (ro) {
823 screen->ro = renderonly_dup(ro);
824 if (!screen->ro) {
825 DBG("could not create renderonly object");
826 goto fail;
827 }
828 }
829
830 // maybe this should be in context?
831 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
832 if (!screen->pipe) {
833 DBG("could not create 3d pipe");
834 goto fail;
835 }
836
837 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
838 DBG("could not get GMEM size");
839 goto fail;
840 }
841 screen->gmemsize_bytes = val;
842
843 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
844 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
845 }
846
847 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
848 DBG("could not get device-id");
849 goto fail;
850 }
851 screen->device_id = val;
852
853 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
854 DBG("could not get gpu freq");
855 /* this limits what performance related queries are
856 * supported but is not fatal
857 */
858 screen->max_freq = 0;
859 } else {
860 screen->max_freq = val;
861 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
862 screen->has_timestamp = true;
863 }
864
865 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
866 DBG("could not get gpu-id");
867 goto fail;
868 }
869 screen->gpu_id = val;
870
871 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
872 DBG("could not get chip-id");
873 /* older kernels may not have this property: */
874 unsigned core = screen->gpu_id / 100;
875 unsigned major = (screen->gpu_id % 100) / 10;
876 unsigned minor = screen->gpu_id % 10;
877 unsigned patch = 0; /* assume the worst */
878 val = (patch & 0xff) | ((minor & 0xff) << 8) |
879 ((major & 0xff) << 16) | ((core & 0xff) << 24);
880 }
881 screen->chip_id = val;
882
883 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
884 DBG("could not get # of rings");
885 screen->priority_mask = 0;
886 } else {
887 /* # of rings equates to number of unique priority values: */
888 screen->priority_mask = (1 << val) - 1;
889 }
890
891 if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
892 (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
893 screen->has_robustness = val;
894 }
895
896 struct sysinfo si;
897 sysinfo(&si);
898 screen->ram_size = si.totalram;
899
900 DBG("Pipe Info:");
901 DBG(" GPU-id: %d", screen->gpu_id);
902 DBG(" Chip-id: 0x%08x", screen->chip_id);
903 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
904
905 /* explicitly checking for GPU revisions that are known to work. This
906 * may be overly conservative for a3xx, where spoofing the gpu_id with
907 * the blob driver seems to generate identical cmdstream dumps. But
908 * on a2xx, there seem to be small differences between the GPU revs
909 * so it is probably better to actually test first on real hardware
910 * before enabling:
911 *
912 * If you have a different adreno version, feel free to add it to one
913 * of the cases below and see what happens. And if it works, please
914 * send a patch ;-)
915 */
916 switch (screen->gpu_id) {
917 case 200:
918 case 201:
919 case 205:
920 case 220:
921 fd2_screen_init(pscreen);
922 break;
923 case 305:
924 case 307:
925 case 320:
926 case 330:
927 fd3_screen_init(pscreen);
928 break;
929 case 405:
930 case 420:
931 case 430:
932 fd4_screen_init(pscreen);
933 break;
934 case 510:
935 case 530:
936 case 540:
937 fd5_screen_init(pscreen);
938 break;
939 case 618:
940 case 630:
941 case 640:
942 case 650:
943 fd6_screen_init(pscreen);
944 break;
945 default:
946 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
947 goto fail;
948 }
949
950 if (screen->gpu_id >= 600) {
951 screen->gmem_alignw = 16;
952 screen->gmem_alignh = 4;
953 screen->tile_alignw = is_a650(screen) ? 96 : 32;
954 screen->tile_alignh = 32;
955 screen->num_vsc_pipes = 32;
956 } else if (screen->gpu_id >= 500) {
957 screen->gmem_alignw = screen->tile_alignw = 64;
958 screen->gmem_alignh = screen->tile_alignh = 32;
959 screen->num_vsc_pipes = 16;
960 } else {
961 screen->gmem_alignw = screen->tile_alignw = 32;
962 screen->gmem_alignh = screen->tile_alignh = 32;
963 screen->num_vsc_pipes = 8;
964 }
965
966 if (fd_mesa_debug & FD_DBG_PERFC) {
967 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
968 &screen->num_perfcntr_groups);
969 }
970
971 /* NOTE: don't enable if we have too old of a kernel to support
972 * growable cmdstream buffers, since memory requirement for cmdstream
973 * buffers would be too much otherwise.
974 */
975 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
976 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
977
978 if (BATCH_DEBUG)
979 screen->live_batches = _mesa_pointer_set_create(NULL);
980
981 fd_bc_init(&screen->batch_cache);
982
983 list_inithead(&screen->context_list);
984
985 (void) simple_mtx_init(&screen->lock, mtx_plain);
986
987 pscreen->destroy = fd_screen_destroy;
988 pscreen->get_param = fd_screen_get_param;
989 pscreen->get_paramf = fd_screen_get_paramf;
990 pscreen->get_shader_param = fd_screen_get_shader_param;
991 pscreen->get_compute_param = fd_get_compute_param;
992 pscreen->get_compiler_options = fd_get_compiler_options;
993
994 fd_resource_screen_init(pscreen);
995 fd_query_screen_init(pscreen);
996 fd_gmem_screen_init(pscreen);
997
998 pscreen->get_name = fd_screen_get_name;
999 pscreen->get_vendor = fd_screen_get_vendor;
1000 pscreen->get_device_vendor = fd_screen_get_device_vendor;
1001
1002 pscreen->get_timestamp = fd_screen_get_timestamp;
1003
1004 pscreen->fence_reference = _fd_fence_ref;
1005 pscreen->fence_finish = fd_fence_finish;
1006 pscreen->fence_get_fd = fd_fence_get_fd;
1007
1008 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1009
1010 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1011
1012 return pscreen;
1013
1014 fail:
1015 fd_screen_destroy(pscreen);
1016 return NULL;
1017 }