src/gallium/drivers/freedreno/freedreno_screen.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35 #include "util/u_format_s3tc.h"
  36 #include "util/u_screen.h"
  37 #include "util/u_string.h"
  38 #include "util/u_debug.h"
  39
  40 #include "util/os_time.h"
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60
  61 #include "ir3/ir3_nir.h"
  62 #include "a2xx/ir2.h"
  63
  64 /* XXX this should go away */
  65 #include "state_tracker/drm_driver.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  78                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  79                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  80                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  81                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  82                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  83                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  84                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  85                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  86                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  87                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  88                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  89                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  90                 {"softpin",   FD_DBG_SOFTPIN,"Enable softpin command submission (experimental)"},
  91                 {"ubwc",      FD_DBG_UBWC,   "Enable UBWC for all internal buffers (experimental)"},
  92                 DEBUG_NAMED_VALUE_END
  93 };
  94
  95 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  96
  97 int fd_mesa_debug = 0;
  98 bool fd_binning_enabled = true;
  99 static bool glsl120 = false;
 100
 101 static const char *
 102 fd_screen_get_name(struct pipe_screen *pscreen)
 103 {
 104         static char buffer[128];
 105         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 106                         fd_screen(pscreen)->device_id);
 107         return buffer;
 108 }
 109
 110 static const char *
 111 fd_screen_get_vendor(struct pipe_screen *pscreen)
 112 {
 113         return "freedreno";
 114 }
 115
 116 static const char *
 117 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 118 {
 119         return "Qualcomm";
 120 }
 121
 122
 123 static uint64_t
 124 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 125 {
 126         struct fd_screen *screen = fd_screen(pscreen);
 127
 128         if (screen->has_timestamp) {
 129                 uint64_t n;
 130                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 131                 debug_assert(screen->max_freq > 0);
 132                 return n * 1000000000 / screen->max_freq;
 133         } else {
 134                 int64_t cpu_time = os_time_get() * 1000;
 135                 return cpu_time + screen->cpu_gpu_time_delta;
 136         }
 137
 138 }
 139
 140 static void
 141 fd_screen_destroy(struct pipe_screen *pscreen)
 142 {
 143         struct fd_screen *screen = fd_screen(pscreen);
 144
 145         if (screen->pipe)
 146                 fd_pipe_del(screen->pipe);
 147
 148         if (screen->dev)
 149                 fd_device_del(screen->dev);
 150
 151         if (screen->ro)
 152                 FREE(screen->ro);
 153
 154         fd_bc_fini(&screen->batch_cache);
 155
 156         slab_destroy_parent(&screen->transfer_pool);
 157
 158         mtx_destroy(&screen->lock);
 159
 160         ralloc_free(screen->compiler);
 161
 162         free(screen->perfcntr_queries);
 163         free(screen);
 164 }
 165
 166 /*
 167 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 168 tables for things that differ if the delta is not too much..
 169  */
 170 static int
 171 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 172 {
 173         struct fd_screen *screen = fd_screen(pscreen);
 174
 175         /* this is probably not totally correct.. but it's a start: */
 176         switch (param) {
 177         /* Supported features (boolean caps). */
 178         case PIPE_CAP_NPOT_TEXTURES:
 179         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 180         case PIPE_CAP_ANISOTROPIC_FILTER:
 181         case PIPE_CAP_POINT_SPRITE:
 182         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183         case PIPE_CAP_TEXTURE_SWIZZLE:
 184         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 185         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 186         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 187         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 188         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 190         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 191         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 192         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 193         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 194         case PIPE_CAP_STRING_MARKER:
 195         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 196         case PIPE_CAP_TEXTURE_BARRIER:
 197         case PIPE_CAP_INVALIDATE_BUFFER:
 198                 return 1;
 199
 200         case PIPE_CAP_PACKED_UNIFORMS:
 201                 return !is_a2xx(screen);
 202
 203         case PIPE_CAP_VERTEXID_NOBASE:
 204                 return is_a3xx(screen) || is_a4xx(screen);
 205
 206         case PIPE_CAP_COMPUTE:
 207                 return has_compute(screen);
 208
 209         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 210         case PIPE_CAP_PCI_GROUP:
 211         case PIPE_CAP_PCI_BUS:
 212         case PIPE_CAP_PCI_DEVICE:
 213         case PIPE_CAP_PCI_FUNCTION:
 214         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 215                 return 0;
 216
 217         case PIPE_CAP_SM3:
 218         case PIPE_CAP_PRIMITIVE_RESTART:
 219         case PIPE_CAP_TGSI_INSTANCEID:
 220         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 221         case PIPE_CAP_INDEP_BLEND_ENABLE:
 222         case PIPE_CAP_INDEP_BLEND_FUNC:
 223         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 224         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 225         case PIPE_CAP_CONDITIONAL_RENDER:
 226         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 227         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 228         case PIPE_CAP_CLIP_HALFZ:
 229                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 230
 231         case PIPE_CAP_FAKE_SW_MSAA:
 232                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 233
 234         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 235                 return is_a5xx(screen) || is_a6xx(screen);
 236
 237         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 238                 return is_a6xx(screen);
 239
 240         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 241                 return is_a3xx(screen) || is_a4xx(screen);
 242
 243         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 244                 return is_a5xx(screen) || is_a6xx(screen);
 245
 246         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 247                 if (is_a3xx(screen)) return 16;
 248                 if (is_a4xx(screen)) return 32;
 249                 if (is_a5xx(screen)) return 32;
 250                 if (is_a6xx(screen)) return 64;
 251                 return 0;
 252         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 253                 /* We could possibly emulate more by pretending 2d/rect textures and
 254                  * splitting high bits of index into 2nd dimension..
 255                  */
 256                 if (is_a3xx(screen)) return 8192;
 257                 if (is_a4xx(screen)) return 16384;
 258                 if (is_a5xx(screen)) return 16384;
 259                 if (is_a6xx(screen)) return 1 << 27;
 260                 return 0;
 261
 262         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 263         case PIPE_CAP_CUBE_MAP_ARRAY:
 264         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 265         case PIPE_CAP_TEXTURE_QUERY_LOD:
 266                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 267
 268         case PIPE_CAP_START_INSTANCE:
 269                 /* Note that a5xx can do this, it just can't (at least with
 270                  * current firmware) do draw_indirect with base_instance.
 271                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 272                  * gl42), hide base_instance on a5xx.  :-/
 273                  */
 274                 return is_a4xx(screen);
 275
 276         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 277                 return 64;
 278
 279         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 280         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 281                 if (glsl120)
 282                         return 120;
 283                 return is_ir3(screen) ? 140 : 120;
 284
 285         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 286                 /* we can probably enable 320 for a5xx too, but need to test: */
 287                 if (is_a6xx(screen)) return 320;
 288                 if (is_a5xx(screen)) return 310;
 289                 if (is_ir3(screen))  return 300;
 290                 return 120;
 291
 292         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 293                 if (is_a6xx(screen)) return 64;
 294                 if (is_a5xx(screen)) return 4;
 295                 return 0;
 296
 297         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 298                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 299                         return 4;
 300                 return 0;
 301
 302         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 303         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 304                 return 0;
 305
 306         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 307                 return 0;
 308
 309         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 310                 return screen->priority_mask;
 311
 312         case PIPE_CAP_DRAW_INDIRECT:
 313                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 314                         return 1;
 315                 return 0;
 316
 317         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 318                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 319                         return 1;
 320                 return 0;
 321
 322         case PIPE_CAP_LOAD_CONSTBUF:
 323                 /* name is confusing, but this turns on std430 packing */
 324                 if (is_ir3(screen))
 325                         return 1;
 326                 return 0;
 327
 328         case PIPE_CAP_MAX_VIEWPORTS:
 329                 return 1;
 330
 331         case PIPE_CAP_MAX_VARYINGS:
 332                 return 16;
 333
 334         case PIPE_CAP_SHAREABLE_SHADERS:
 335         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 336         /* manage the variants for these ourself, to avoid breaking precompile: */
 337         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 338         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 339                 if (is_ir3(screen))
 340                         return 1;
 341                 return 0;
 342
 343         /* Stream output. */
 344         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 345                 if (is_ir3(screen))
 346                         return PIPE_MAX_SO_BUFFERS;
 347                 return 0;
 348         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 349         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 350                 if (is_ir3(screen))
 351                         return 1;
 352                 return 0;
 353         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 354         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 355                 if (is_ir3(screen))
 356                         return 16 * 4;   /* should only be shader out limit? */
 357                 return 0;
 358
 359         /* Texturing. */
 360         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 361         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 362                 return MAX_MIP_LEVELS;
 363         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 364                 return 11;
 365
 366         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 367                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 368
 369         /* Render targets. */
 370         case PIPE_CAP_MAX_RENDER_TARGETS:
 371                 return screen->max_rts;
 372         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 373                 return is_a3xx(screen) ? 1 : 0;
 374
 375         /* Queries. */
 376         case PIPE_CAP_OCCLUSION_QUERY:
 377                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 378         case PIPE_CAP_QUERY_TIMESTAMP:
 379         case PIPE_CAP_QUERY_TIME_ELAPSED:
 380                 /* only a4xx, requires new enough kernel so we know max_freq: */
 381                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 382
 383         case PIPE_CAP_VENDOR_ID:
 384                 return 0x5143;
 385         case PIPE_CAP_DEVICE_ID:
 386                 return 0xFFFFFFFF;
 387         case PIPE_CAP_ACCELERATED:
 388                 return 1;
 389         case PIPE_CAP_VIDEO_MEMORY:
 390                 DBG("FINISHME: The value returned is incorrect\n");
 391                 return 10;
 392         case PIPE_CAP_UMA:
 393                 return 1;
 394         case PIPE_CAP_NATIVE_FENCE_FD:
 395                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 396         default:
 397                 return u_pipe_screen_get_param_defaults(pscreen, param);
 398         }
 399 }
 400
 401 static float
 402 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 403 {
 404         switch (param) {
 405         case PIPE_CAPF_MAX_LINE_WIDTH:
 406         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 407                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 408                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 409                  * uses too small of a render target size, and gets confused when
 410                  * the lines start going offscreen.
 411                  *
 412                  * See: https://code.google.com/p/android/issues/detail?id=206513
 413                  */
 414                 if (fd_mesa_debug & FD_DBG_DEQP)
 415                         return 48.0f;
 416                 return 127.0f;
 417         case PIPE_CAPF_MAX_POINT_WIDTH:
 418         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 419                 return 4092.0f;
 420         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 421                 return 16.0f;
 422         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 423                 return 15.0f;
 424         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 425         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 426         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 427                 return 0.0f;
 428         }
 429         debug_printf("unknown paramf %d\n", param);
 430         return 0;
 431 }
 432
 433 static int
 434 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 435                 enum pipe_shader_type shader,
 436                 enum pipe_shader_cap param)
 437 {
 438         struct fd_screen *screen = fd_screen(pscreen);
 439
 440         switch(shader)
 441         {
 442         case PIPE_SHADER_FRAGMENT:
 443         case PIPE_SHADER_VERTEX:
 444                 break;
 445         case PIPE_SHADER_COMPUTE:
 446                 if (has_compute(screen))
 447                         break;
 448                 return 0;
 449         case PIPE_SHADER_GEOMETRY:
 450                 /* maye we could emulate.. */
 451                 return 0;
 452         default:
 453                 DBG("unknown shader type %d", shader);
 454                 return 0;
 455         }
 456
 457         /* this is probably not totally correct.. but it's a start: */
 458         switch (param) {
 459         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 460         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 461         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 463                 return 16384;
 464         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 465                 return 8; /* XXX */
 466         case PIPE_SHADER_CAP_MAX_INPUTS:
 467         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 468                 return 16;
 469         case PIPE_SHADER_CAP_MAX_TEMPS:
 470                 return 64; /* Max native temporaries. */
 471         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 472                 /* NOTE: seems to be limit for a3xx is actually 512 but
 473                  * split between VS and FS.  Use lower limit of 256 to
 474                  * avoid getting into impossible situations:
 475                  */
 476                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 477         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 478                 return is_ir3(screen) ? 16 : 1;
 479         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 480                 return 1;
 481         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 482         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 483                 /* Technically this should be the same as for TEMP/CONST, since
 484                  * everything is just normal registers.  This is just temporary
 485                  * hack until load_input/store_output handle arrays in a similar
 486                  * way as load_var/store_var..
 487                  */
 488                 return 0;
 489         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 490         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 491                 /* a2xx compiler doesn't handle indirect: */
 492                 return is_ir3(screen) ? 1 : 0;
 493         case PIPE_SHADER_CAP_SUBROUTINES:
 494         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 495         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 496         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 497         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 498         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 499         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 500         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 501         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 502         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 503                 return 0;
 504         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 505                 return 1;
 506         case PIPE_SHADER_CAP_INTEGERS:
 507                 if (glsl120)
 508                         return 0;
 509                 return is_ir3(screen) ? 1 : 0;
 510         case PIPE_SHADER_CAP_INT64_ATOMICS:
 511                 return 0;
 512         case PIPE_SHADER_CAP_FP16:
 513                 return 0;
 514         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 515         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 516                 return 16;
 517         case PIPE_SHADER_CAP_PREFERRED_IR:
 518                 return PIPE_SHADER_IR_NIR;
 519         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 520                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 521         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 522                 return 32;
 523         case PIPE_SHADER_CAP_SCALAR_ISA:
 524                 return is_ir3(screen) ? 1 : 0;
 525         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 526         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 527                 if (is_a5xx(screen) || is_a6xx(screen)) {
 528                         /* a5xx (and a4xx for that matter) has one state-block
 529                          * for compute-shader SSBO's and another that is shared
 530                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 531                          * just advertise SSBOs for FS and CS.  We could possibly
 532                          * do what blob does, and partition the space for
 533                          * VS/HS/DS/GS/FS.  The blob advertises:
 534                          *
 535                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 536                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 537                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 538                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 539                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 540                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 541                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 542                          *
 543                          * I think that way we could avoid having to patch shaders
 544                          * for actual SSBO indexes by using a static partitioning.
 545                          *
 546                          * Note same state block is used for images and buffers,
 547                          * but images also need texture state for read access
 548                          * (isam/isam.3d)
 549                          */
 550                         switch(shader)
 551                         {
 552                         case PIPE_SHADER_FRAGMENT:
 553                         case PIPE_SHADER_COMPUTE:
 554                                 return 24;
 555                         default:
 556                                 return 0;
 557                         }
 558                 }
 559                 return 0;
 560         }
 561         debug_printf("unknown shader param %d\n", param);
 562         return 0;
 563 }
 564
 565 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 566  * into per-generation backend?
 567  */
 568 static int
 569 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 570                 enum pipe_compute_cap param, void *ret)
 571 {
 572         struct fd_screen *screen = fd_screen(pscreen);
 573         const char * const ir = "ir3";
 574
 575         if (!has_compute(screen))
 576                 return 0;
 577
 578 #define RET(x) do {                  \
 579    if (ret)                          \
 580       memcpy(ret, x, sizeof(x));     \
 581    return sizeof(x);                 \
 582 } while (0)
 583
 584         switch (param) {
 585         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 586 // don't expose 64b pointer support yet, until ir3 supports 64b
 587 // math, otherwise spir64 target is used and we get 64b pointer
 588 // calculations that we can't do yet
 589 //              if (is_a5xx(screen))
 590 //                      RET((uint32_t []){ 64 });
 591                 RET((uint32_t []){ 32 });
 592
 593         case PIPE_COMPUTE_CAP_IR_TARGET:
 594                 if (ret)
 595                         sprintf(ret, ir);
 596                 return strlen(ir) * sizeof(char);
 597
 598         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 599                 RET((uint64_t []) { 3 });
 600
 601         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 602                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 603
 604         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 605                 RET(((uint64_t []) { 1024, 1024, 64 }));
 606
 607         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 608                 RET((uint64_t []) { 1024 });
 609
 610         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 611                 RET((uint64_t []) { screen->ram_size });
 612
 613         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 614                 RET((uint64_t []) { 32768 });
 615
 616         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 617         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 618                 RET((uint64_t []) { 4096 });
 619
 620         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 621                 RET((uint64_t []) { screen->ram_size });
 622
 623         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 624                 RET((uint32_t []) { screen->max_freq / 1000000 });
 625
 626         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 627                 RET((uint32_t []) { 9999 });  // TODO
 628
 629         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 630                 RET((uint32_t []) { 1 });
 631
 632         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 633                 RET((uint32_t []) { 32 });  // TODO
 634
 635         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 636                 RET((uint64_t []) { 1024 }); // TODO
 637         }
 638
 639         return 0;
 640 }
 641
 642 static const void *
 643 fd_get_compiler_options(struct pipe_screen *pscreen,
 644                 enum pipe_shader_ir ir, unsigned shader)
 645 {
 646         struct fd_screen *screen = fd_screen(pscreen);
 647
 648         if (is_ir3(screen))
 649                 return ir3_get_compiler_options(screen->compiler);
 650
 651         return ir2_get_compiler_options();
 652 }
 653
 654 boolean
 655 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 656                 struct fd_bo *bo,
 657                 struct renderonly_scanout *scanout,
 658                 unsigned stride,
 659                 struct winsys_handle *whandle)
 660 {
 661         whandle->stride = stride;
 662
 663         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 664                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 665         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 666                 if (renderonly_get_handle(scanout, whandle))
 667                         return TRUE;
 668                 whandle->handle = fd_bo_handle(bo);
 669                 return TRUE;
 670         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 671                 whandle->handle = fd_bo_dmabuf(bo);
 672                 return TRUE;
 673         } else {
 674                 return FALSE;
 675         }
 676 }
 677
 678 static void
 679 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 680                 enum pipe_format format,
 681                 int max, uint64_t *modifiers,
 682                 unsigned int *external_only,
 683                 int *count)
 684 {
 685         struct fd_screen *screen = fd_screen(pscreen);
 686         int i, num = 0;
 687
 688         max = MIN2(max, screen->num_supported_modifiers);
 689
 690         if (!max) {
 691                 max = screen->num_supported_modifiers;
 692                 external_only = NULL;
 693                 modifiers = NULL;
 694         }
 695
 696         for (i = 0; i < max; i++) {
 697                 if (modifiers)
 698                         modifiers[num] = screen->supported_modifiers[i];
 699
 700                 if (external_only)
 701                         external_only[num] = 0;
 702
 703                 num++;
 704         }
 705
 706         *count = num;
 707 }
 708
 709 struct fd_bo *
 710 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 711                 struct winsys_handle *whandle)
 712 {
 713         struct fd_screen *screen = fd_screen(pscreen);
 714         struct fd_bo *bo;
 715
 716         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 717                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 718         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 719                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 720         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 721                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 722         } else {
 723                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 724                 return NULL;
 725         }
 726
 727         if (!bo) {
 728                 DBG("ref name 0x%08x failed", whandle->handle);
 729                 return NULL;
 730         }
 731
 732         return bo;
 733 }
 734
 735 struct pipe_screen *
 736 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 737 {
 738         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 739         struct pipe_screen *pscreen;
 740         uint64_t val;
 741
 742         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 743
 744         if (fd_mesa_debug & FD_DBG_NOBIN)
 745                 fd_binning_enabled = false;
 746
 747         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 748
 749         if (!screen)
 750                 return NULL;
 751
 752         pscreen = &screen->base;
 753
 754         screen->dev = dev;
 755         screen->refcnt = 1;
 756
 757         if (ro) {
 758                 screen->ro = renderonly_dup(ro);
 759                 if (!screen->ro) {
 760                         DBG("could not create renderonly object");
 761                         goto fail;
 762                 }
 763         }
 764
 765         // maybe this should be in context?
 766         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 767         if (!screen->pipe) {
 768                 DBG("could not create 3d pipe");
 769                 goto fail;
 770         }
 771
 772         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 773                 DBG("could not get GMEM size");
 774                 goto fail;
 775         }
 776         screen->gmemsize_bytes = val;
 777
 778         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 779                 DBG("could not get device-id");
 780                 goto fail;
 781         }
 782         screen->device_id = val;
 783
 784         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 785                 DBG("could not get gpu freq");
 786                 /* this limits what performance related queries are
 787                  * supported but is not fatal
 788                  */
 789                 screen->max_freq = 0;
 790         } else {
 791                 screen->max_freq = val;
 792                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 793                         screen->has_timestamp = true;
 794         }
 795
 796         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 797                 DBG("could not get gpu-id");
 798                 goto fail;
 799         }
 800         screen->gpu_id = val;
 801
 802         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 803                 DBG("could not get chip-id");
 804                 /* older kernels may not have this property: */
 805                 unsigned core  = screen->gpu_id / 100;
 806                 unsigned major = (screen->gpu_id % 100) / 10;
 807                 unsigned minor = screen->gpu_id % 10;
 808                 unsigned patch = 0;  /* assume the worst */
 809                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 810                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 811         }
 812         screen->chip_id = val;
 813
 814         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 815                 DBG("could not get # of rings");
 816                 screen->priority_mask = 0;
 817         } else {
 818                 /* # of rings equates to number of unique priority values: */
 819                 screen->priority_mask = (1 << val) - 1;
 820         }
 821
 822         struct sysinfo si;
 823         sysinfo(&si);
 824         screen->ram_size = si.totalram;
 825
 826         DBG("Pipe Info:");
 827         DBG(" GPU-id:          %d", screen->gpu_id);
 828         DBG(" Chip-id:         0x%08x", screen->chip_id);
 829         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 830
 831         /* explicitly checking for GPU revisions that are known to work.  This
 832          * may be overly conservative for a3xx, where spoofing the gpu_id with
 833          * the blob driver seems to generate identical cmdstream dumps.  But
 834          * on a2xx, there seem to be small differences between the GPU revs
 835          * so it is probably better to actually test first on real hardware
 836          * before enabling:
 837          *
 838          * If you have a different adreno version, feel free to add it to one
 839          * of the cases below and see what happens.  And if it works, please
 840          * send a patch ;-)
 841          */
 842         switch (screen->gpu_id) {
 843         case 200:
 844         case 201:
 845         case 205:
 846         case 220:
 847                 fd2_screen_init(pscreen);
 848                 break;
 849         case 305:
 850         case 307:
 851         case 320:
 852         case 330:
 853                 fd3_screen_init(pscreen);
 854                 break;
 855         case 420:
 856         case 430:
 857                 fd4_screen_init(pscreen);
 858                 break;
 859         case 530:
 860                 fd5_screen_init(pscreen);
 861                 break;
 862         case 630:
 863                 fd6_screen_init(pscreen);
 864                 break;
 865         default:
 866                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 867                 goto fail;
 868         }
 869
 870         if (screen->gpu_id >= 600) {
 871                 screen->gmem_alignw = 32;
 872                 screen->gmem_alignh = 32;
 873                 screen->num_vsc_pipes = 32;
 874         } else if (screen->gpu_id >= 500) {
 875                 screen->gmem_alignw = 64;
 876                 screen->gmem_alignh = 32;
 877                 screen->num_vsc_pipes = 16;
 878         } else {
 879                 screen->gmem_alignw = 32;
 880                 screen->gmem_alignh = 32;
 881                 screen->num_vsc_pipes = 8;
 882         }
 883
 884         /* NOTE: don't enable if we have too old of a kernel to support
 885          * growable cmdstream buffers, since memory requirement for cmdstream
 886          * buffers would be too much otherwise.
 887          */
 888         if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
 889                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 890
 891         fd_bc_init(&screen->batch_cache);
 892
 893         (void) mtx_init(&screen->lock, mtx_plain);
 894
 895         pscreen->destroy = fd_screen_destroy;
 896         pscreen->get_param = fd_screen_get_param;
 897         pscreen->get_paramf = fd_screen_get_paramf;
 898         pscreen->get_shader_param = fd_screen_get_shader_param;
 899         pscreen->get_compute_param = fd_get_compute_param;
 900         pscreen->get_compiler_options = fd_get_compiler_options;
 901
 902         fd_resource_screen_init(pscreen);
 903         fd_query_screen_init(pscreen);
 904
 905         pscreen->get_name = fd_screen_get_name;
 906         pscreen->get_vendor = fd_screen_get_vendor;
 907         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 908
 909         pscreen->get_timestamp = fd_screen_get_timestamp;
 910
 911         pscreen->fence_reference = fd_fence_ref;
 912         pscreen->fence_finish = fd_fence_finish;
 913         pscreen->fence_get_fd = fd_fence_get_fd;
 914
 915         pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
 916
 917         if (!screen->supported_modifiers) {
 918                 static const uint64_t supported_modifiers[] = {
 919                         DRM_FORMAT_MOD_LINEAR,
 920                 };
 921
 922                 screen->supported_modifiers = supported_modifiers;
 923                 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
 924         }
 925
 926         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 927
 928         return pscreen;
 929
 930 fail:
 931         fd_screen_destroy(pscreen);
 932         return NULL;
 933 }