src/gallium/drivers/freedreno/freedreno_screen.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35 #include "util/u_format_s3tc.h"
  36 #include "util/u_screen.h"
  37 #include "util/u_string.h"
  38 #include "util/u_debug.h"
  39
  40 #include "util/os_time.h"
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60
  61 #include "ir3/ir3_nir.h"
  62 #include "a2xx/ir2.h"
  63
  64 /* XXX this should go away */
  65 #include "state_tracker/drm_driver.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  78                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  79                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  80                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  81                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  82                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  83                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  84                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  85                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  86                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  87                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  88                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  89                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  90                 {"softpin",   FD_DBG_SOFTPIN,"Enable softpin command submission (experimental)"},
  91                 {"ubwc",      FD_DBG_UBWC,   "Enable UBWC for all internal buffers (experimental)"},
  92                 DEBUG_NAMED_VALUE_END
  93 };
  94
  95 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  96
  97 int fd_mesa_debug = 0;
  98 bool fd_binning_enabled = true;
  99 static bool glsl120 = false;
 100
 101 static const char *
 102 fd_screen_get_name(struct pipe_screen *pscreen)
 103 {
 104         static char buffer[128];
 105         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 106                         fd_screen(pscreen)->device_id);
 107         return buffer;
 108 }
 109
 110 static const char *
 111 fd_screen_get_vendor(struct pipe_screen *pscreen)
 112 {
 113         return "freedreno";
 114 }
 115
 116 static const char *
 117 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 118 {
 119         return "Qualcomm";
 120 }
 121
 122
 123 static uint64_t
 124 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 125 {
 126         struct fd_screen *screen = fd_screen(pscreen);
 127
 128         if (screen->has_timestamp) {
 129                 uint64_t n;
 130                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 131                 debug_assert(screen->max_freq > 0);
 132                 return n * 1000000000 / screen->max_freq;
 133         } else {
 134                 int64_t cpu_time = os_time_get() * 1000;
 135                 return cpu_time + screen->cpu_gpu_time_delta;
 136         }
 137
 138 }
 139
 140 static void
 141 fd_screen_destroy(struct pipe_screen *pscreen)
 142 {
 143         struct fd_screen *screen = fd_screen(pscreen);
 144
 145         if (screen->pipe)
 146                 fd_pipe_del(screen->pipe);
 147
 148         if (screen->dev)
 149                 fd_device_del(screen->dev);
 150
 151         if (screen->ro)
 152                 FREE(screen->ro);
 153
 154         fd_bc_fini(&screen->batch_cache);
 155
 156         slab_destroy_parent(&screen->transfer_pool);
 157
 158         mtx_destroy(&screen->lock);
 159
 160         ralloc_free(screen->compiler);
 161
 162         free(screen->perfcntr_queries);
 163         free(screen);
 164 }
 165
 166 /*
 167 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 168 tables for things that differ if the delta is not too much..
 169  */
 170 static int
 171 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 172 {
 173         struct fd_screen *screen = fd_screen(pscreen);
 174
 175         /* this is probably not totally correct.. but it's a start: */
 176         switch (param) {
 177         /* Supported features (boolean caps). */
 178         case PIPE_CAP_NPOT_TEXTURES:
 179         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 180         case PIPE_CAP_ANISOTROPIC_FILTER:
 181         case PIPE_CAP_POINT_SPRITE:
 182         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183         case PIPE_CAP_TEXTURE_SWIZZLE:
 184         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 185         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 186         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 187         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 188         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 190         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 191         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 192         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 193         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 194         case PIPE_CAP_STRING_MARKER:
 195         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 196         case PIPE_CAP_TEXTURE_BARRIER:
 197         case PIPE_CAP_INVALIDATE_BUFFER:
 198                 return 1;
 199
 200         case PIPE_CAP_PACKED_UNIFORMS:
 201                 return !is_a2xx(screen);
 202
 203         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 204         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 205                 return screen->has_robustness;
 206
 207         case PIPE_CAP_VERTEXID_NOBASE:
 208                 return is_a3xx(screen) || is_a4xx(screen);
 209
 210         case PIPE_CAP_COMPUTE:
 211                 return has_compute(screen);
 212
 213         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 214         case PIPE_CAP_PCI_GROUP:
 215         case PIPE_CAP_PCI_BUS:
 216         case PIPE_CAP_PCI_DEVICE:
 217         case PIPE_CAP_PCI_FUNCTION:
 218         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 219                 return 0;
 220
 221         case PIPE_CAP_SM3:
 222         case PIPE_CAP_PRIMITIVE_RESTART:
 223         case PIPE_CAP_TGSI_INSTANCEID:
 224         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 225         case PIPE_CAP_INDEP_BLEND_ENABLE:
 226         case PIPE_CAP_INDEP_BLEND_FUNC:
 227         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 228         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 229         case PIPE_CAP_CONDITIONAL_RENDER:
 230         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 231         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 232         case PIPE_CAP_CLIP_HALFZ:
 233                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 234
 235         case PIPE_CAP_FAKE_SW_MSAA:
 236                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 237
 238         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 239                 return is_a5xx(screen) || is_a6xx(screen);
 240
 241         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 242                 return is_a6xx(screen);
 243
 244         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 245                 return is_a3xx(screen) || is_a4xx(screen);
 246
 247         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 248                 return is_a5xx(screen) || is_a6xx(screen);
 249
 250         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 251                 if (is_a3xx(screen)) return 16;
 252                 if (is_a4xx(screen)) return 32;
 253                 if (is_a5xx(screen)) return 32;
 254                 if (is_a6xx(screen)) return 64;
 255                 return 0;
 256         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 257                 /* We could possibly emulate more by pretending 2d/rect textures and
 258                  * splitting high bits of index into 2nd dimension..
 259                  */
 260                 if (is_a3xx(screen)) return 8192;
 261                 if (is_a4xx(screen)) return 16384;
 262                 if (is_a5xx(screen)) return 16384;
 263                 if (is_a6xx(screen)) return 1 << 27;
 264                 return 0;
 265
 266         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 267         case PIPE_CAP_CUBE_MAP_ARRAY:
 268         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 269         case PIPE_CAP_TEXTURE_QUERY_LOD:
 270                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 271
 272         case PIPE_CAP_START_INSTANCE:
 273                 /* Note that a5xx can do this, it just can't (at least with
 274                  * current firmware) do draw_indirect with base_instance.
 275                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 276                  * gl42), hide base_instance on a5xx.  :-/
 277                  */
 278                 return is_a4xx(screen);
 279
 280         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 281                 return 64;
 282
 283         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 284         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 285                 if (glsl120)
 286                         return 120;
 287                 return is_ir3(screen) ? 140 : 120;
 288
 289         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 290                 /* we can probably enable 320 for a5xx too, but need to test: */
 291                 if (is_a6xx(screen)) return 320;
 292                 if (is_a5xx(screen)) return 310;
 293                 if (is_ir3(screen))  return 300;
 294                 return 120;
 295
 296         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 297                 if (is_a6xx(screen)) return 64;
 298                 if (is_a5xx(screen)) return 4;
 299                 return 0;
 300
 301         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 302                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 303                         return 4;
 304                 return 0;
 305
 306         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 307         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 308                 return 0;
 309
 310         case PIPE_CAP_TGSI_FS_FBFETCH:
 311                 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
 312                                 is_a6xx(screen))
 313                         return 1;
 314                 return 0;
 315         case PIPE_CAP_SAMPLE_SHADING:
 316                 if (is_a6xx(screen)) return 1;
 317                 return 0;
 318
 319         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 320                 return 0;
 321
 322         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 323                 return screen->priority_mask;
 324
 325         case PIPE_CAP_DRAW_INDIRECT:
 326                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 327                         return 1;
 328                 return 0;
 329
 330         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 331                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 332                         return 1;
 333                 return 0;
 334
 335         case PIPE_CAP_LOAD_CONSTBUF:
 336                 /* name is confusing, but this turns on std430 packing */
 337                 if (is_ir3(screen))
 338                         return 1;
 339                 return 0;
 340
 341         case PIPE_CAP_MAX_VIEWPORTS:
 342                 return 1;
 343
 344         case PIPE_CAP_MAX_VARYINGS:
 345                 return 16;
 346
 347         case PIPE_CAP_SHAREABLE_SHADERS:
 348         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 349         /* manage the variants for these ourself, to avoid breaking precompile: */
 350         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 351         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 352                 if (is_ir3(screen))
 353                         return 1;
 354                 return 0;
 355
 356         /* Stream output. */
 357         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 358                 if (is_ir3(screen))
 359                         return PIPE_MAX_SO_BUFFERS;
 360                 return 0;
 361         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 362         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 363         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 364                 if (is_ir3(screen))
 365                         return 1;
 366                 return 0;
 367         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 368         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 369                 if (is_ir3(screen))
 370                         return 16 * 4;   /* should only be shader out limit? */
 371                 return 0;
 372
 373         /* Texturing. */
 374         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 375                 return 1 << (MAX_MIP_LEVELS - 1);
 376         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 377                 return MAX_MIP_LEVELS;
 378         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 379                 return 11;
 380
 381         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 382                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 383
 384         /* Render targets. */
 385         case PIPE_CAP_MAX_RENDER_TARGETS:
 386                 return screen->max_rts;
 387         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 388                 return is_a3xx(screen) ? 1 : 0;
 389
 390         /* Queries. */
 391         case PIPE_CAP_OCCLUSION_QUERY:
 392                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 393         case PIPE_CAP_QUERY_TIMESTAMP:
 394         case PIPE_CAP_QUERY_TIME_ELAPSED:
 395                 /* only a4xx, requires new enough kernel so we know max_freq: */
 396                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 397
 398         case PIPE_CAP_VENDOR_ID:
 399                 return 0x5143;
 400         case PIPE_CAP_DEVICE_ID:
 401                 return 0xFFFFFFFF;
 402         case PIPE_CAP_ACCELERATED:
 403                 return 1;
 404         case PIPE_CAP_VIDEO_MEMORY:
 405                 DBG("FINISHME: The value returned is incorrect\n");
 406                 return 10;
 407         case PIPE_CAP_UMA:
 408                 return 1;
 409         case PIPE_CAP_NATIVE_FENCE_FD:
 410                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 411         default:
 412                 return u_pipe_screen_get_param_defaults(pscreen, param);
 413         }
 414 }
 415
 416 static float
 417 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 418 {
 419         switch (param) {
 420         case PIPE_CAPF_MAX_LINE_WIDTH:
 421         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 422                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 423                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 424                  * uses too small of a render target size, and gets confused when
 425                  * the lines start going offscreen.
 426                  *
 427                  * See: https://code.google.com/p/android/issues/detail?id=206513
 428                  */
 429                 if (fd_mesa_debug & FD_DBG_DEQP)
 430                         return 48.0f;
 431                 return 127.0f;
 432         case PIPE_CAPF_MAX_POINT_WIDTH:
 433         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 434                 return 4092.0f;
 435         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 436                 return 16.0f;
 437         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 438                 return 15.0f;
 439         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 440         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 441         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 442                 return 0.0f;
 443         }
 444         debug_printf("unknown paramf %d\n", param);
 445         return 0;
 446 }
 447
 448 static int
 449 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 450                 enum pipe_shader_type shader,
 451                 enum pipe_shader_cap param)
 452 {
 453         struct fd_screen *screen = fd_screen(pscreen);
 454
 455         switch(shader)
 456         {
 457         case PIPE_SHADER_FRAGMENT:
 458         case PIPE_SHADER_VERTEX:
 459                 break;
 460         case PIPE_SHADER_COMPUTE:
 461                 if (has_compute(screen))
 462                         break;
 463                 return 0;
 464         case PIPE_SHADER_GEOMETRY:
 465                 /* maye we could emulate.. */
 466                 return 0;
 467         default:
 468                 DBG("unknown shader type %d", shader);
 469                 return 0;
 470         }
 471
 472         /* this is probably not totally correct.. but it's a start: */
 473         switch (param) {
 474         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 475         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 476         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 477         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 478                 return 16384;
 479         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 480                 return 8; /* XXX */
 481         case PIPE_SHADER_CAP_MAX_INPUTS:
 482         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 483                 return 16;
 484         case PIPE_SHADER_CAP_MAX_TEMPS:
 485                 return 64; /* Max native temporaries. */
 486         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 487                 /* NOTE: seems to be limit for a3xx is actually 512 but
 488                  * split between VS and FS.  Use lower limit of 256 to
 489                  * avoid getting into impossible situations:
 490                  */
 491                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 492         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 493                 return is_ir3(screen) ? 16 : 1;
 494         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 495                 return 1;
 496         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 497         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 498                 /* Technically this should be the same as for TEMP/CONST, since
 499                  * everything is just normal registers.  This is just temporary
 500                  * hack until load_input/store_output handle arrays in a similar
 501                  * way as load_var/store_var..
 502                  */
 503                 return 0;
 504         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 505         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 506                 /* a2xx compiler doesn't handle indirect: */
 507                 return is_ir3(screen) ? 1 : 0;
 508         case PIPE_SHADER_CAP_SUBROUTINES:
 509         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 510         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 511         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 512         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 513         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 514         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 515         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 516         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 517         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 518                 return 0;
 519         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 520                 return 1;
 521         case PIPE_SHADER_CAP_INTEGERS:
 522                 if (glsl120)
 523                         return 0;
 524                 return is_ir3(screen) ? 1 : 0;
 525         case PIPE_SHADER_CAP_INT64_ATOMICS:
 526                 return 0;
 527         case PIPE_SHADER_CAP_FP16:
 528                 return 0;
 529         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 530         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 531                 return 16;
 532         case PIPE_SHADER_CAP_PREFERRED_IR:
 533                 return PIPE_SHADER_IR_NIR;
 534         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 535                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 536         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 537                 return 32;
 538         case PIPE_SHADER_CAP_SCALAR_ISA:
 539                 return is_ir3(screen) ? 1 : 0;
 540         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 541         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 542                 if (is_a5xx(screen) || is_a6xx(screen)) {
 543                         /* a5xx (and a4xx for that matter) has one state-block
 544                          * for compute-shader SSBO's and another that is shared
 545                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 546                          * just advertise SSBOs for FS and CS.  We could possibly
 547                          * do what blob does, and partition the space for
 548                          * VS/HS/DS/GS/FS.  The blob advertises:
 549                          *
 550                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 551                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 552                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 553                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 554                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 555                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 556                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 557                          *
 558                          * I think that way we could avoid having to patch shaders
 559                          * for actual SSBO indexes by using a static partitioning.
 560                          *
 561                          * Note same state block is used for images and buffers,
 562                          * but images also need texture state for read access
 563                          * (isam/isam.3d)
 564                          */
 565                         switch(shader)
 566                         {
 567                         case PIPE_SHADER_FRAGMENT:
 568                         case PIPE_SHADER_COMPUTE:
 569                                 return 24;
 570                         default:
 571                                 return 0;
 572                         }
 573                 }
 574                 return 0;
 575         }
 576         debug_printf("unknown shader param %d\n", param);
 577         return 0;
 578 }
 579
 580 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 581  * into per-generation backend?
 582  */
 583 static int
 584 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 585                 enum pipe_compute_cap param, void *ret)
 586 {
 587         struct fd_screen *screen = fd_screen(pscreen);
 588         const char * const ir = "ir3";
 589
 590         if (!has_compute(screen))
 591                 return 0;
 592
 593 #define RET(x) do {                  \
 594    if (ret)                          \
 595       memcpy(ret, x, sizeof(x));     \
 596    return sizeof(x);                 \
 597 } while (0)
 598
 599         switch (param) {
 600         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 601 // don't expose 64b pointer support yet, until ir3 supports 64b
 602 // math, otherwise spir64 target is used and we get 64b pointer
 603 // calculations that we can't do yet
 604 //              if (is_a5xx(screen))
 605 //                      RET((uint32_t []){ 64 });
 606                 RET((uint32_t []){ 32 });
 607
 608         case PIPE_COMPUTE_CAP_IR_TARGET:
 609                 if (ret)
 610                         sprintf(ret, ir);
 611                 return strlen(ir) * sizeof(char);
 612
 613         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 614                 RET((uint64_t []) { 3 });
 615
 616         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 617                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 618
 619         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 620                 RET(((uint64_t []) { 1024, 1024, 64 }));
 621
 622         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 623                 RET((uint64_t []) { 1024 });
 624
 625         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 626                 RET((uint64_t []) { screen->ram_size });
 627
 628         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 629                 RET((uint64_t []) { 32768 });
 630
 631         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 632         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 633                 RET((uint64_t []) { 4096 });
 634
 635         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 636                 RET((uint64_t []) { screen->ram_size });
 637
 638         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 639                 RET((uint32_t []) { screen->max_freq / 1000000 });
 640
 641         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 642                 RET((uint32_t []) { 9999 });  // TODO
 643
 644         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 645                 RET((uint32_t []) { 1 });
 646
 647         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 648                 RET((uint32_t []) { 32 });  // TODO
 649
 650         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 651                 RET((uint64_t []) { 1024 }); // TODO
 652         }
 653
 654         return 0;
 655 }
 656
 657 static const void *
 658 fd_get_compiler_options(struct pipe_screen *pscreen,
 659                 enum pipe_shader_ir ir, unsigned shader)
 660 {
 661         struct fd_screen *screen = fd_screen(pscreen);
 662
 663         if (is_ir3(screen))
 664                 return ir3_get_compiler_options(screen->compiler);
 665
 666         return ir2_get_compiler_options();
 667 }
 668
 669 boolean
 670 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 671                 struct fd_bo *bo,
 672                 struct renderonly_scanout *scanout,
 673                 unsigned stride,
 674                 struct winsys_handle *whandle)
 675 {
 676         whandle->stride = stride;
 677
 678         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 679                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 680         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 681                 if (renderonly_get_handle(scanout, whandle))
 682                         return TRUE;
 683                 whandle->handle = fd_bo_handle(bo);
 684                 return TRUE;
 685         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 686                 whandle->handle = fd_bo_dmabuf(bo);
 687                 return TRUE;
 688         } else {
 689                 return FALSE;
 690         }
 691 }
 692
 693 static void
 694 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 695                 enum pipe_format format,
 696                 int max, uint64_t *modifiers,
 697                 unsigned int *external_only,
 698                 int *count)
 699 {
 700         struct fd_screen *screen = fd_screen(pscreen);
 701         int i, num = 0;
 702
 703         max = MIN2(max, screen->num_supported_modifiers);
 704
 705         if (!max) {
 706                 max = screen->num_supported_modifiers;
 707                 external_only = NULL;
 708                 modifiers = NULL;
 709         }
 710
 711         for (i = 0; i < max; i++) {
 712                 if (modifiers)
 713                         modifiers[num] = screen->supported_modifiers[i];
 714
 715                 if (external_only)
 716                         external_only[num] = 0;
 717
 718                 num++;
 719         }
 720
 721         *count = num;
 722 }
 723
 724 struct fd_bo *
 725 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 726                 struct winsys_handle *whandle)
 727 {
 728         struct fd_screen *screen = fd_screen(pscreen);
 729         struct fd_bo *bo;
 730
 731         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 732                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 733         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 734                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 735         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 736                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 737         } else {
 738                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 739                 return NULL;
 740         }
 741
 742         if (!bo) {
 743                 DBG("ref name 0x%08x failed", whandle->handle);
 744                 return NULL;
 745         }
 746
 747         return bo;
 748 }
 749
 750 struct pipe_screen *
 751 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 752 {
 753         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 754         struct pipe_screen *pscreen;
 755         uint64_t val;
 756
 757         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 758
 759         if (fd_mesa_debug & FD_DBG_NOBIN)
 760                 fd_binning_enabled = false;
 761
 762         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 763
 764         if (!screen)
 765                 return NULL;
 766
 767         pscreen = &screen->base;
 768
 769         screen->dev = dev;
 770         screen->refcnt = 1;
 771
 772         if (ro) {
 773                 screen->ro = renderonly_dup(ro);
 774                 if (!screen->ro) {
 775                         DBG("could not create renderonly object");
 776                         goto fail;
 777                 }
 778         }
 779
 780         // maybe this should be in context?
 781         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 782         if (!screen->pipe) {
 783                 DBG("could not create 3d pipe");
 784                 goto fail;
 785         }
 786
 787         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 788                 DBG("could not get GMEM size");
 789                 goto fail;
 790         }
 791         screen->gmemsize_bytes = val;
 792
 793         if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
 794                 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
 795         }
 796
 797         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 798                 DBG("could not get device-id");
 799                 goto fail;
 800         }
 801         screen->device_id = val;
 802
 803         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 804                 DBG("could not get gpu freq");
 805                 /* this limits what performance related queries are
 806                  * supported but is not fatal
 807                  */
 808                 screen->max_freq = 0;
 809         } else {
 810                 screen->max_freq = val;
 811                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 812                         screen->has_timestamp = true;
 813         }
 814
 815         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 816                 DBG("could not get gpu-id");
 817                 goto fail;
 818         }
 819         screen->gpu_id = val;
 820
 821         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 822                 DBG("could not get chip-id");
 823                 /* older kernels may not have this property: */
 824                 unsigned core  = screen->gpu_id / 100;
 825                 unsigned major = (screen->gpu_id % 100) / 10;
 826                 unsigned minor = screen->gpu_id % 10;
 827                 unsigned patch = 0;  /* assume the worst */
 828                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 829                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 830         }
 831         screen->chip_id = val;
 832
 833         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 834                 DBG("could not get # of rings");
 835                 screen->priority_mask = 0;
 836         } else {
 837                 /* # of rings equates to number of unique priority values: */
 838                 screen->priority_mask = (1 << val) - 1;
 839         }
 840
 841         if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
 842                         (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
 843                 screen->has_robustness = val;
 844         }
 845
 846         struct sysinfo si;
 847         sysinfo(&si);
 848         screen->ram_size = si.totalram;
 849
 850         DBG("Pipe Info:");
 851         DBG(" GPU-id:          %d", screen->gpu_id);
 852         DBG(" Chip-id:         0x%08x", screen->chip_id);
 853         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 854
 855         /* explicitly checking for GPU revisions that are known to work.  This
 856          * may be overly conservative for a3xx, where spoofing the gpu_id with
 857          * the blob driver seems to generate identical cmdstream dumps.  But
 858          * on a2xx, there seem to be small differences between the GPU revs
 859          * so it is probably better to actually test first on real hardware
 860          * before enabling:
 861          *
 862          * If you have a different adreno version, feel free to add it to one
 863          * of the cases below and see what happens.  And if it works, please
 864          * send a patch ;-)
 865          */
 866         switch (screen->gpu_id) {
 867         case 200:
 868         case 201:
 869         case 205:
 870         case 220:
 871                 fd2_screen_init(pscreen);
 872                 break;
 873         case 305:
 874         case 307:
 875         case 320:
 876         case 330:
 877                 fd3_screen_init(pscreen);
 878                 break;
 879         case 420:
 880         case 430:
 881                 fd4_screen_init(pscreen);
 882                 break;
 883         case 530:
 884                 fd5_screen_init(pscreen);
 885                 break;
 886         case 630:
 887                 fd6_screen_init(pscreen);
 888                 break;
 889         default:
 890                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 891                 goto fail;
 892         }
 893
 894         if (screen->gpu_id >= 600) {
 895                 screen->gmem_alignw = 32;
 896                 screen->gmem_alignh = 32;
 897                 screen->num_vsc_pipes = 32;
 898         } else if (screen->gpu_id >= 500) {
 899                 screen->gmem_alignw = 64;
 900                 screen->gmem_alignh = 32;
 901                 screen->num_vsc_pipes = 16;
 902         } else {
 903                 screen->gmem_alignw = 32;
 904                 screen->gmem_alignh = 32;
 905                 screen->num_vsc_pipes = 8;
 906         }
 907
 908         /* NOTE: don't enable if we have too old of a kernel to support
 909          * growable cmdstream buffers, since memory requirement for cmdstream
 910          * buffers would be too much otherwise.
 911          */
 912         if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
 913                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 914
 915         fd_bc_init(&screen->batch_cache);
 916
 917         (void) mtx_init(&screen->lock, mtx_plain);
 918
 919         pscreen->destroy = fd_screen_destroy;
 920         pscreen->get_param = fd_screen_get_param;
 921         pscreen->get_paramf = fd_screen_get_paramf;
 922         pscreen->get_shader_param = fd_screen_get_shader_param;
 923         pscreen->get_compute_param = fd_get_compute_param;
 924         pscreen->get_compiler_options = fd_get_compiler_options;
 925
 926         fd_resource_screen_init(pscreen);
 927         fd_query_screen_init(pscreen);
 928
 929         pscreen->get_name = fd_screen_get_name;
 930         pscreen->get_vendor = fd_screen_get_vendor;
 931         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 932
 933         pscreen->get_timestamp = fd_screen_get_timestamp;
 934
 935         pscreen->fence_reference = fd_fence_ref;
 936         pscreen->fence_finish = fd_fence_finish;
 937         pscreen->fence_get_fd = fd_fence_get_fd;
 938
 939         pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
 940
 941         if (!screen->supported_modifiers) {
 942                 static const uint64_t supported_modifiers[] = {
 943                         DRM_FORMAT_MOD_LINEAR,
 944                 };
 945
 946                 screen->supported_modifiers = supported_modifiers;
 947                 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
 948         }
 949
 950         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 951
 952         return pscreen;
 953
 954 fail:
 955         fd_screen_destroy(pscreen);
 956         return NULL;
 957 }