src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58
  59 #include "ir3/ir3_nir.h"
  60
  61 /* XXX this should go away */
  62 #include "state_tracker/drm_driver.h"
  63
  64 static const struct debug_named_value debug_options[] = {
  65                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  66                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  67                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  68                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  69                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  70                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  71                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  72                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  73                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  74                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  75                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  76                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  77                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  78                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  79                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  82                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  83                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  84                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  85                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  86                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  87                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  88                 DEBUG_NAMED_VALUE_END
  89 };
  90
  91 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  92
  93 int fd_mesa_debug = 0;
  94 bool fd_binning_enabled = true;
  95 static bool glsl120 = false;
  96
  97 static const struct debug_named_value shader_debug_options[] = {
  98                 {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
  99                 {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
 100                 {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
 101                 DEBUG_NAMED_VALUE_END
 102 };
 103
 104 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
 105
 106 enum fd_shader_debug fd_shader_debug = 0;
 107
 108 static const char *
 109 fd_screen_get_name(struct pipe_screen *pscreen)
 110 {
 111         static char buffer[128];
 112         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 113                         fd_screen(pscreen)->device_id);
 114         return buffer;
 115 }
 116
 117 static const char *
 118 fd_screen_get_vendor(struct pipe_screen *pscreen)
 119 {
 120         return "freedreno";
 121 }
 122
 123 static const char *
 124 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 125 {
 126         return "Qualcomm";
 127 }
 128
 129
 130 static uint64_t
 131 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 132 {
 133         struct fd_screen *screen = fd_screen(pscreen);
 134
 135         if (screen->has_timestamp) {
 136                 uint64_t n;
 137                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 138                 debug_assert(screen->max_freq > 0);
 139                 return n * 1000000000 / screen->max_freq;
 140         } else {
 141                 int64_t cpu_time = os_time_get() * 1000;
 142                 return cpu_time + screen->cpu_gpu_time_delta;
 143         }
 144
 145 }
 146
 147 static void
 148 fd_screen_destroy(struct pipe_screen *pscreen)
 149 {
 150         struct fd_screen *screen = fd_screen(pscreen);
 151
 152         if (screen->pipe)
 153                 fd_pipe_del(screen->pipe);
 154
 155         if (screen->dev)
 156                 fd_device_del(screen->dev);
 157
 158         fd_bc_fini(&screen->batch_cache);
 159
 160         slab_destroy_parent(&screen->transfer_pool);
 161
 162         mtx_destroy(&screen->lock);
 163
 164         ralloc_free(screen->compiler);
 165
 166         free(screen->perfcntr_queries);
 167         free(screen);
 168 }
 169
 170 /*
 171 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 172 tables for things that differ if the delta is not too much..
 173  */
 174 static int
 175 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 176 {
 177         struct fd_screen *screen = fd_screen(pscreen);
 178
 179         /* this is probably not totally correct.. but it's a start: */
 180         switch (param) {
 181         /* Supported features (boolean caps). */
 182         case PIPE_CAP_NPOT_TEXTURES:
 183         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 184         case PIPE_CAP_ANISOTROPIC_FILTER:
 185         case PIPE_CAP_POINT_SPRITE:
 186         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 187         case PIPE_CAP_TEXTURE_SWIZZLE:
 188         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 189         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 190         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 191         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 192         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 193         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 194         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 195         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 196         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 197         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198         case PIPE_CAP_STRING_MARKER:
 199         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 200         case PIPE_CAP_TEXTURE_BARRIER:
 201         case PIPE_CAP_INVALIDATE_BUFFER:
 202                 return 1;
 203
 204         case PIPE_CAP_VERTEXID_NOBASE:
 205                 return is_a3xx(screen) || is_a4xx(screen);
 206
 207         case PIPE_CAP_COMPUTE:
 208                 return has_compute(screen);
 209
 210         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 211         case PIPE_CAP_TGSI_TEXCOORD:
 212         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 213         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 214         case PIPE_CAP_QUERY_MEMORY_INFO:
 215         case PIPE_CAP_PCI_GROUP:
 216         case PIPE_CAP_PCI_BUS:
 217         case PIPE_CAP_PCI_DEVICE:
 218         case PIPE_CAP_PCI_FUNCTION:
 219                 return 0;
 220
 221         case PIPE_CAP_SM3:
 222         case PIPE_CAP_PRIMITIVE_RESTART:
 223         case PIPE_CAP_TGSI_INSTANCEID:
 224         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 225         case PIPE_CAP_INDEP_BLEND_ENABLE:
 226         case PIPE_CAP_INDEP_BLEND_FUNC:
 227         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 228         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 229         case PIPE_CAP_CONDITIONAL_RENDER:
 230         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 231         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 232         case PIPE_CAP_CLIP_HALFZ:
 233                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 234
 235         case PIPE_CAP_FAKE_SW_MSAA:
 236                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 237
 238         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 239                 return is_a5xx(screen);
 240
 241         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 242                 return is_a3xx(screen) || is_a4xx(screen);
 243
 244         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 245                 return is_a5xx(screen);
 246
 247         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 248                 return 0;
 249         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 250                 if (is_a3xx(screen)) return 16;
 251                 if (is_a4xx(screen)) return 32;
 252                 if (is_a5xx(screen)) return 32;
 253                 return 0;
 254         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 255                 /* We could possibly emulate more by pretending 2d/rect textures and
 256                  * splitting high bits of index into 2nd dimension..
 257                  */
 258                 if (is_a3xx(screen)) return 8192;
 259                 if (is_a4xx(screen)) return 16384;
 260                 if (is_a5xx(screen)) return 16384;
 261                 return 0;
 262
 263         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 264         case PIPE_CAP_CUBE_MAP_ARRAY:
 265         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 266         case PIPE_CAP_TEXTURE_QUERY_LOD:
 267                 return is_a4xx(screen) || is_a5xx(screen);
 268
 269         case PIPE_CAP_START_INSTANCE:
 270                 /* Note that a5xx can do this, it just can't (at least with
 271                  * current firmware) do draw_indirect with base_instance.
 272                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 273                  * gl42), hide base_instance on a5xx.  :-/
 274                  */
 275                 return is_a4xx(screen);
 276
 277         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 278                 return 64;
 279
 280         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 281         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 282                 if (glsl120)
 283                         return 120;
 284                 return is_ir3(screen) ? 140 : 120;
 285
 286         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 287                 if (is_a5xx(screen))
 288                         return 4;
 289                 return 0;
 290
 291         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 292                 if (is_a4xx(screen) || is_a5xx(screen))
 293                         return 4;
 294                 return 0;
 295
 296         /* Unsupported features. */
 297         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 298         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 299         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 300         case PIPE_CAP_USER_VERTEX_BUFFERS:
 301         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 302         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 303         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 304         case PIPE_CAP_TEXTURE_GATHER_SM5:
 305         case PIPE_CAP_SAMPLE_SHADING:
 306         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 307         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 308         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 309         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 310         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 311         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 312         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 313         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 314         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 315         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 316         case PIPE_CAP_TGSI_TXQS:
 317         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 318         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 319         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 320         case PIPE_CAP_CLEAR_TEXTURE:
 321         case PIPE_CAP_DRAW_PARAMETERS:
 322         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 323         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 324         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 325         case PIPE_CAP_GENERATE_MIPMAP:
 326         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 327         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 328         case PIPE_CAP_CULL_DISTANCE:
 329         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 330         case PIPE_CAP_TGSI_VOTE:
 331         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 332         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 333         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 334         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 335         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 336         case PIPE_CAP_TGSI_FS_FBFETCH:
 337         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 338         case PIPE_CAP_DOUBLES:
 339         case PIPE_CAP_INT64:
 340         case PIPE_CAP_INT64_DIVMOD:
 341         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 342         case PIPE_CAP_TGSI_CLOCK:
 343         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 344         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 345         case PIPE_CAP_TGSI_BALLOT:
 346         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 347         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 348         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 349         case PIPE_CAP_POST_DEPTH_COVERAGE:
 350         case PIPE_CAP_BINDLESS_TEXTURE:
 351         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 352         case PIPE_CAP_QUERY_SO_OVERFLOW:
 353         case PIPE_CAP_MEMOBJ:
 354         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 355         case PIPE_CAP_TILE_RASTER_ORDER:
 356         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 357         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 358         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 359         case PIPE_CAP_FENCE_SIGNAL:
 360         case PIPE_CAP_CONSTBUF0_FLAGS:
 361         case PIPE_CAP_PACKED_UNIFORMS:
 362         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 363         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 364         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 365         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 366         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 367         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 368         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 369                 return 0;
 370
 371         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 372                 return screen->priority_mask;
 373
 374         case PIPE_CAP_DRAW_INDIRECT:
 375                 if (is_a4xx(screen) || is_a5xx(screen))
 376                         return 1;
 377                 return 0;
 378
 379         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 380                 if (is_a4xx(screen) || is_a5xx(screen))
 381                         return 1;
 382                 return 0;
 383
 384         case PIPE_CAP_LOAD_CONSTBUF:
 385                 /* name is confusing, but this turns on std430 packing */
 386                 if (is_ir3(screen))
 387                         return 1;
 388                 return 0;
 389
 390         case PIPE_CAP_MAX_VIEWPORTS:
 391                 return 1;
 392
 393         case PIPE_CAP_SHAREABLE_SHADERS:
 394         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 395         /* manage the variants for these ourself, to avoid breaking precompile: */
 396         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 397         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 398                 if (is_ir3(screen))
 399                         return 1;
 400                 return 0;
 401
 402         /* Stream output. */
 403         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 404                 if (is_ir3(screen))
 405                         return PIPE_MAX_SO_BUFFERS;
 406                 return 0;
 407         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 408         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 409                 if (is_ir3(screen))
 410                         return 1;
 411                 return 0;
 412         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 413         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 414                 if (is_ir3(screen))
 415                         return 16 * 4;   /* should only be shader out limit? */
 416                 return 0;
 417
 418         /* Geometry shader output, unsupported. */
 419         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 420         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 421         case PIPE_CAP_MAX_VERTEX_STREAMS:
 422                 return 0;
 423
 424         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 425                 return 2048;
 426
 427         /* Texturing. */
 428         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 429         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 430                 return MAX_MIP_LEVELS;
 431         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 432                 return 11;
 433
 434         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 435                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 436
 437         /* Render targets. */
 438         case PIPE_CAP_MAX_RENDER_TARGETS:
 439                 return screen->max_rts;
 440         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 441                 return is_a3xx(screen) ? 1 : 0;
 442
 443         /* Queries. */
 444         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 445                 return 0;
 446         case PIPE_CAP_OCCLUSION_QUERY:
 447                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 448         case PIPE_CAP_QUERY_TIMESTAMP:
 449         case PIPE_CAP_QUERY_TIME_ELAPSED:
 450                 /* only a4xx, requires new enough kernel so we know max_freq: */
 451                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 452
 453         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 454         case PIPE_CAP_MIN_TEXEL_OFFSET:
 455                 return -8;
 456
 457         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 458         case PIPE_CAP_MAX_TEXEL_OFFSET:
 459                 return 7;
 460
 461         case PIPE_CAP_ENDIANNESS:
 462                 return PIPE_ENDIAN_LITTLE;
 463
 464         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 465                 return 64;
 466
 467         case PIPE_CAP_VENDOR_ID:
 468                 return 0x5143;
 469         case PIPE_CAP_DEVICE_ID:
 470                 return 0xFFFFFFFF;
 471         case PIPE_CAP_ACCELERATED:
 472                 return 1;
 473         case PIPE_CAP_VIDEO_MEMORY:
 474                 DBG("FINISHME: The value returned is incorrect\n");
 475                 return 10;
 476         case PIPE_CAP_UMA:
 477                 return 1;
 478         case PIPE_CAP_NATIVE_FENCE_FD:
 479                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 480         }
 481         debug_printf("unknown param %d\n", param);
 482         return 0;
 483 }
 484
 485 static float
 486 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 487 {
 488         switch (param) {
 489         case PIPE_CAPF_MAX_LINE_WIDTH:
 490         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 491                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 492                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 493                  * uses too small of a render target size, and gets confused when
 494                  * the lines start going offscreen.
 495                  *
 496                  * See: https://code.google.com/p/android/issues/detail?id=206513
 497                  */
 498                 if (fd_mesa_debug & FD_DBG_DEQP)
 499                         return 48.0f;
 500                 return 127.0f;
 501         case PIPE_CAPF_MAX_POINT_WIDTH:
 502         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 503                 return 4092.0f;
 504         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 505                 return 16.0f;
 506         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 507                 return 15.0f;
 508         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 509         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 510         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 511                 return 0.0f;
 512         }
 513         debug_printf("unknown paramf %d\n", param);
 514         return 0;
 515 }
 516
 517 static int
 518 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 519                 enum pipe_shader_type shader,
 520                 enum pipe_shader_cap param)
 521 {
 522         struct fd_screen *screen = fd_screen(pscreen);
 523
 524         switch(shader)
 525         {
 526         case PIPE_SHADER_FRAGMENT:
 527         case PIPE_SHADER_VERTEX:
 528                 break;
 529         case PIPE_SHADER_COMPUTE:
 530                 if (has_compute(screen))
 531                         break;
 532                 return 0;
 533         case PIPE_SHADER_GEOMETRY:
 534                 /* maye we could emulate.. */
 535                 return 0;
 536         default:
 537                 DBG("unknown shader type %d", shader);
 538                 return 0;
 539         }
 540
 541         /* this is probably not totally correct.. but it's a start: */
 542         switch (param) {
 543         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 544         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 545         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 546         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 547                 return 16384;
 548         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 549                 return 8; /* XXX */
 550         case PIPE_SHADER_CAP_MAX_INPUTS:
 551         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 552                 return 16;
 553         case PIPE_SHADER_CAP_MAX_TEMPS:
 554                 return 64; /* Max native temporaries. */
 555         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 556                 /* NOTE: seems to be limit for a3xx is actually 512 but
 557                  * split between VS and FS.  Use lower limit of 256 to
 558                  * avoid getting into impossible situations:
 559                  */
 560                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 561         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 562                 return is_ir3(screen) ? 16 : 1;
 563         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 564                 return 1;
 565         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 566         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 567                 /* Technically this should be the same as for TEMP/CONST, since
 568                  * everything is just normal registers.  This is just temporary
 569                  * hack until load_input/store_output handle arrays in a similar
 570                  * way as load_var/store_var..
 571                  */
 572                 return 0;
 573         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 574         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 575                 /* a2xx compiler doesn't handle indirect: */
 576                 return is_ir3(screen) ? 1 : 0;
 577         case PIPE_SHADER_CAP_SUBROUTINES:
 578         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 579         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 580         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 581         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 582         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 583         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 584         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 585         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 586         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 587                 return 0;
 588         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 589                 return 1;
 590         case PIPE_SHADER_CAP_INTEGERS:
 591                 if (glsl120)
 592                         return 0;
 593                 return is_ir3(screen) ? 1 : 0;
 594         case PIPE_SHADER_CAP_INT64_ATOMICS:
 595                 return 0;
 596         case PIPE_SHADER_CAP_FP16:
 597                 return 0;
 598         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 599         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 600                 return 16;
 601         case PIPE_SHADER_CAP_PREFERRED_IR:
 602                 if (is_ir3(screen))
 603                         return PIPE_SHADER_IR_NIR;
 604                 return PIPE_SHADER_IR_TGSI;
 605         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 606                 if (is_ir3(screen)) {
 607                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 608                 } else {
 609                         return (1 << PIPE_SHADER_IR_TGSI);
 610                 }
 611                 return 0;
 612         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 613                 return 32;
 614         case PIPE_SHADER_CAP_SCALAR_ISA:
 615                 return is_ir3(screen) ? 1 : 0;
 616         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 617         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 618                 if (is_a5xx(screen)) {
 619                         /* a5xx (and a4xx for that matter) has one state-block
 620                          * for compute-shader SSBO's and another that is shared
 621                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 622                          * just advertise SSBOs for FS and CS.  We could possibly
 623                          * do what blob does, and partition the space for
 624                          * VS/HS/DS/GS/FS.  The blob advertises:
 625                          *
 626                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 627                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 628                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 629                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 630                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 631                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 632                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 633                          *
 634                          * I think that way we could avoid having to patch shaders
 635                          * for actual SSBO indexes by using a static partitioning.
 636                          *
 637                          * Note same state block is used for images and buffers,
 638                          * but images also need texture state for read access
 639                          * (isam/isam.3d)
 640                          */
 641                         switch(shader)
 642                         {
 643                         case PIPE_SHADER_FRAGMENT:
 644                         case PIPE_SHADER_COMPUTE:
 645                                 return 24;
 646                         default:
 647                                 return 0;
 648                         }
 649                 }
 650                 return 0;
 651         }
 652         debug_printf("unknown shader param %d\n", param);
 653         return 0;
 654 }
 655
 656 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 657  * into per-generation backend?
 658  */
 659 static int
 660 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 661                 enum pipe_compute_cap param, void *ret)
 662 {
 663         struct fd_screen *screen = fd_screen(pscreen);
 664         const char * const ir = "ir3";
 665
 666         if (!has_compute(screen))
 667                 return 0;
 668
 669 #define RET(x) do {                  \
 670    if (ret)                          \
 671       memcpy(ret, x, sizeof(x));     \
 672    return sizeof(x);                 \
 673 } while (0)
 674
 675         switch (param) {
 676         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 677 // don't expose 64b pointer support yet, until ir3 supports 64b
 678 // math, otherwise spir64 target is used and we get 64b pointer
 679 // calculations that we can't do yet
 680 //              if (is_a5xx(screen))
 681 //                      RET((uint32_t []){ 64 });
 682                 RET((uint32_t []){ 32 });
 683
 684         case PIPE_COMPUTE_CAP_IR_TARGET:
 685                 if (ret)
 686                         sprintf(ret, ir);
 687                 return strlen(ir) * sizeof(char);
 688
 689         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 690                 RET((uint64_t []) { 3 });
 691
 692         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 693                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 694
 695         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 696                 RET(((uint64_t []) { 1024, 1024, 64 }));
 697
 698         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 699                 RET((uint64_t []) { 1024 });
 700
 701         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 702                 RET((uint64_t []) { screen->ram_size });
 703
 704         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 705                 RET((uint64_t []) { 32768 });
 706
 707         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 708         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 709                 RET((uint64_t []) { 4096 });
 710
 711         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 712                 RET((uint64_t []) { screen->ram_size });
 713
 714         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 715                 RET((uint32_t []) { screen->max_freq / 1000000 });
 716
 717         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 718                 RET((uint32_t []) { 9999 });  // TODO
 719
 720         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 721                 RET((uint32_t []) { 1 });
 722
 723         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 724                 RET((uint32_t []) { 32 });  // TODO
 725
 726         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 727                 RET((uint64_t []) { 1024 }); // TODO
 728         }
 729
 730         return 0;
 731 }
 732
 733 static const void *
 734 fd_get_compiler_options(struct pipe_screen *pscreen,
 735                 enum pipe_shader_ir ir, unsigned shader)
 736 {
 737         struct fd_screen *screen = fd_screen(pscreen);
 738
 739         if (is_ir3(screen))
 740                 return ir3_get_compiler_options(screen->compiler);
 741
 742         return NULL;
 743 }
 744
 745 boolean
 746 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 747                 struct fd_bo *bo,
 748                 unsigned stride,
 749                 struct winsys_handle *whandle)
 750 {
 751         whandle->stride = stride;
 752
 753         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 754                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 755         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 756                 whandle->handle = fd_bo_handle(bo);
 757                 return TRUE;
 758         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 759                 whandle->handle = fd_bo_dmabuf(bo);
 760                 return TRUE;
 761         } else {
 762                 return FALSE;
 763         }
 764 }
 765
 766 struct fd_bo *
 767 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 768                 struct winsys_handle *whandle)
 769 {
 770         struct fd_screen *screen = fd_screen(pscreen);
 771         struct fd_bo *bo;
 772
 773         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 774                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 775         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 776                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 777         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 778                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 779         } else {
 780                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 781                 return NULL;
 782         }
 783
 784         if (!bo) {
 785                 DBG("ref name 0x%08x failed", whandle->handle);
 786                 return NULL;
 787         }
 788
 789         return bo;
 790 }
 791
 792 struct pipe_screen *
 793 fd_screen_create(struct fd_device *dev)
 794 {
 795         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 796         struct pipe_screen *pscreen;
 797         uint64_t val;
 798
 799         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 800         fd_shader_debug = debug_get_option_fd_shader_debug();
 801
 802         if (fd_mesa_debug & FD_DBG_NOBIN)
 803                 fd_binning_enabled = false;
 804
 805         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 806
 807         if (!screen)
 808                 return NULL;
 809
 810         pscreen = &screen->base;
 811
 812         screen->dev = dev;
 813         screen->refcnt = 1;
 814
 815         // maybe this should be in context?
 816         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 817         if (!screen->pipe) {
 818                 DBG("could not create 3d pipe");
 819                 goto fail;
 820         }
 821
 822         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 823                 DBG("could not get GMEM size");
 824                 goto fail;
 825         }
 826         screen->gmemsize_bytes = val;
 827
 828         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 829                 DBG("could not get device-id");
 830                 goto fail;
 831         }
 832         screen->device_id = val;
 833
 834         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 835                 DBG("could not get gpu freq");
 836                 /* this limits what performance related queries are
 837                  * supported but is not fatal
 838                  */
 839                 screen->max_freq = 0;
 840         } else {
 841                 screen->max_freq = val;
 842                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 843                         screen->has_timestamp = true;
 844         }
 845
 846         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 847                 DBG("could not get gpu-id");
 848                 goto fail;
 849         }
 850         screen->gpu_id = val;
 851
 852         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 853                 DBG("could not get chip-id");
 854                 /* older kernels may not have this property: */
 855                 unsigned core  = screen->gpu_id / 100;
 856                 unsigned major = (screen->gpu_id % 100) / 10;
 857                 unsigned minor = screen->gpu_id % 10;
 858                 unsigned patch = 0;  /* assume the worst */
 859                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 860                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 861         }
 862         screen->chip_id = val;
 863
 864         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 865                 DBG("could not get # of rings");
 866                 screen->priority_mask = 0;
 867         } else {
 868                 /* # of rings equates to number of unique priority values: */
 869                 screen->priority_mask = (1 << val) - 1;
 870         }
 871
 872         struct sysinfo si;
 873         sysinfo(&si);
 874         screen->ram_size = si.totalram;
 875
 876         DBG("Pipe Info:");
 877         DBG(" GPU-id:          %d", screen->gpu_id);
 878         DBG(" Chip-id:         0x%08x", screen->chip_id);
 879         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 880
 881         /* explicitly checking for GPU revisions that are known to work.  This
 882          * may be overly conservative for a3xx, where spoofing the gpu_id with
 883          * the blob driver seems to generate identical cmdstream dumps.  But
 884          * on a2xx, there seem to be small differences between the GPU revs
 885          * so it is probably better to actually test first on real hardware
 886          * before enabling:
 887          *
 888          * If you have a different adreno version, feel free to add it to one
 889          * of the cases below and see what happens.  And if it works, please
 890          * send a patch ;-)
 891          */
 892         switch (screen->gpu_id) {
 893         case 205:
 894         case 220:
 895                 fd2_screen_init(pscreen);
 896                 break;
 897         case 305:
 898         case 307:
 899         case 320:
 900         case 330:
 901                 fd3_screen_init(pscreen);
 902                 break;
 903         case 420:
 904         case 430:
 905                 fd4_screen_init(pscreen);
 906                 break;
 907         case 530:
 908                 fd5_screen_init(pscreen);
 909                 break;
 910         default:
 911                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 912                 goto fail;
 913         }
 914
 915         if (screen->gpu_id >= 500) {
 916                 screen->gmem_alignw = 64;
 917                 screen->gmem_alignh = 32;
 918                 screen->num_vsc_pipes = 16;
 919         } else {
 920                 screen->gmem_alignw = 32;
 921                 screen->gmem_alignh = 32;
 922                 screen->num_vsc_pipes = 8;
 923         }
 924
 925         /* NOTE: don't enable reordering on a2xx, since completely untested.
 926          * Also, don't enable if we have too old of a kernel to support
 927          * growable cmdstream buffers, since memory requirement for cmdstream
 928          * buffers would be too much otherwise.
 929          */
 930         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 931                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 932
 933         fd_bc_init(&screen->batch_cache);
 934
 935         (void) mtx_init(&screen->lock, mtx_plain);
 936
 937         pscreen->destroy = fd_screen_destroy;
 938         pscreen->get_param = fd_screen_get_param;
 939         pscreen->get_paramf = fd_screen_get_paramf;
 940         pscreen->get_shader_param = fd_screen_get_shader_param;
 941         pscreen->get_compute_param = fd_get_compute_param;
 942         pscreen->get_compiler_options = fd_get_compiler_options;
 943
 944         fd_resource_screen_init(pscreen);
 945         fd_query_screen_init(pscreen);
 946
 947         pscreen->get_name = fd_screen_get_name;
 948         pscreen->get_vendor = fd_screen_get_vendor;
 949         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 950
 951         pscreen->get_timestamp = fd_screen_get_timestamp;
 952
 953         pscreen->fence_reference = fd_fence_ref;
 954         pscreen->fence_finish = fd_fence_finish;
 955         pscreen->fence_get_fd = fd_fence_get_fd;
 956
 957         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 958
 959         return pscreen;
 960
 961 fail:
 962         fd_screen_destroy(pscreen);
 963         return NULL;
 964 }