2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
45 #include <sys/sysinfo.h>
47 #include "freedreno_screen.h"
48 #include "freedreno_resource.h"
49 #include "freedreno_fence.h"
50 #include "freedreno_query.h"
51 #include "freedreno_util.h"
53 #include "a2xx/fd2_screen.h"
54 #include "a3xx/fd3_screen.h"
55 #include "a4xx/fd4_screen.h"
56 #include "a5xx/fd5_screen.h"
57 #include "a6xx/fd6_screen.h"
60 #include "ir3/ir3_nir.h"
62 /* XXX this should go away */
63 #include "state_tracker/drm_driver.h"
65 static const struct debug_named_value debug_options
[] = {
66 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
67 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
68 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
69 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
70 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
71 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
72 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
73 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
74 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
75 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
76 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
77 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
78 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
79 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
83 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
84 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
85 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
86 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a5xx)"},
87 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
88 {"softpin", FD_DBG_SOFTPIN
,"Enable softpin command submission (experimental)"},
92 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
94 int fd_mesa_debug
= 0;
95 bool fd_binning_enabled
= true;
96 static bool glsl120
= false;
99 fd_screen_get_name(struct pipe_screen
*pscreen
)
101 static char buffer
[128];
102 util_snprintf(buffer
, sizeof(buffer
), "FD%03d",
103 fd_screen(pscreen
)->device_id
);
108 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
114 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
121 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
123 struct fd_screen
*screen
= fd_screen(pscreen
);
125 if (screen
->has_timestamp
) {
127 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
128 debug_assert(screen
->max_freq
> 0);
129 return n
* 1000000000 / screen
->max_freq
;
131 int64_t cpu_time
= os_time_get() * 1000;
132 return cpu_time
+ screen
->cpu_gpu_time_delta
;
138 fd_screen_destroy(struct pipe_screen
*pscreen
)
140 struct fd_screen
*screen
= fd_screen(pscreen
);
143 fd_pipe_del(screen
->pipe
);
146 fd_device_del(screen
->dev
);
148 fd_bc_fini(&screen
->batch_cache
);
150 slab_destroy_parent(&screen
->transfer_pool
);
152 mtx_destroy(&screen
->lock
);
154 ralloc_free(screen
->compiler
);
156 free(screen
->perfcntr_queries
);
161 TODO either move caps to a2xx/a3xx specific code, or maybe have some
162 tables for things that differ if the delta is not too much..
165 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
167 struct fd_screen
*screen
= fd_screen(pscreen
);
169 /* this is probably not totally correct.. but it's a start: */
171 /* Supported features (boolean caps). */
172 case PIPE_CAP_NPOT_TEXTURES
:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
174 case PIPE_CAP_ANISOTROPIC_FILTER
:
175 case PIPE_CAP_POINT_SPRITE
:
176 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
177 case PIPE_CAP_TEXTURE_SWIZZLE
:
178 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
179 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
180 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
181 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
182 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
183 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
184 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
185 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
186 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
187 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
188 case PIPE_CAP_STRING_MARKER
:
189 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
190 case PIPE_CAP_TEXTURE_BARRIER
:
191 case PIPE_CAP_INVALIDATE_BUFFER
:
194 case PIPE_CAP_VERTEXID_NOBASE
:
195 return is_a3xx(screen
) || is_a4xx(screen
);
197 case PIPE_CAP_COMPUTE
:
198 return has_compute(screen
);
200 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
201 case PIPE_CAP_PCI_GROUP
:
202 case PIPE_CAP_PCI_BUS
:
203 case PIPE_CAP_PCI_DEVICE
:
204 case PIPE_CAP_PCI_FUNCTION
:
205 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
209 case PIPE_CAP_PRIMITIVE_RESTART
:
210 case PIPE_CAP_TGSI_INSTANCEID
:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
212 case PIPE_CAP_INDEP_BLEND_ENABLE
:
213 case PIPE_CAP_INDEP_BLEND_FUNC
:
214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
215 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
216 case PIPE_CAP_CONDITIONAL_RENDER
:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
218 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
219 case PIPE_CAP_CLIP_HALFZ
:
220 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
222 case PIPE_CAP_FAKE_SW_MSAA
:
223 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
225 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
226 return is_a5xx(screen
) || is_a6xx(screen
);
228 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
229 return is_a6xx(screen
);
231 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
232 return is_a3xx(screen
) || is_a4xx(screen
);
234 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
235 return is_a5xx(screen
) || is_a6xx(screen
);
237 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
238 if (is_a3xx(screen
)) return 16;
239 if (is_a4xx(screen
)) return 32;
240 if (is_a5xx(screen
)) return 32;
241 if (is_a6xx(screen
)) return 32;
243 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
244 /* We could possibly emulate more by pretending 2d/rect textures and
245 * splitting high bits of index into 2nd dimension..
247 if (is_a3xx(screen
)) return 8192;
248 if (is_a4xx(screen
)) return 16384;
249 if (is_a5xx(screen
)) return 16384;
250 if (is_a6xx(screen
)) return 16384;
253 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
254 case PIPE_CAP_CUBE_MAP_ARRAY
:
255 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
256 case PIPE_CAP_TEXTURE_QUERY_LOD
:
257 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
259 case PIPE_CAP_START_INSTANCE
:
260 /* Note that a5xx can do this, it just can't (at least with
261 * current firmware) do draw_indirect with base_instance.
262 * Since draw_indirect is needed sooner (gles31 and gl40 vs
263 * gl42), hide base_instance on a5xx. :-/
265 return is_a4xx(screen
);
267 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
270 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
271 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
274 return is_ir3(screen
) ? 140 : 120;
276 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
277 if (is_a5xx(screen
) || is_a6xx(screen
))
281 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
282 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
286 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
287 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
290 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
293 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
294 return screen
->priority_mask
;
296 case PIPE_CAP_DRAW_INDIRECT
:
297 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
301 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
302 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
306 case PIPE_CAP_LOAD_CONSTBUF
:
307 /* name is confusing, but this turns on std430 packing */
312 case PIPE_CAP_MAX_VIEWPORTS
:
315 case PIPE_CAP_SHAREABLE_SHADERS
:
316 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
317 /* manage the variants for these ourself, to avoid breaking precompile: */
318 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
319 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
325 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
327 return PIPE_MAX_SO_BUFFERS
;
329 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
330 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
334 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
335 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
337 return 16 * 4; /* should only be shader out limit? */
341 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
342 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
343 return MAX_MIP_LEVELS
;
344 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
347 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
348 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
350 /* Render targets. */
351 case PIPE_CAP_MAX_RENDER_TARGETS
:
352 return screen
->max_rts
;
353 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
354 return is_a3xx(screen
) ? 1 : 0;
357 case PIPE_CAP_OCCLUSION_QUERY
:
358 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
359 case PIPE_CAP_QUERY_TIMESTAMP
:
360 case PIPE_CAP_QUERY_TIME_ELAPSED
:
361 /* only a4xx, requires new enough kernel so we know max_freq: */
362 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
364 case PIPE_CAP_VENDOR_ID
:
366 case PIPE_CAP_DEVICE_ID
:
368 case PIPE_CAP_ACCELERATED
:
370 case PIPE_CAP_VIDEO_MEMORY
:
371 DBG("FINISHME: The value returned is incorrect\n");
375 case PIPE_CAP_NATIVE_FENCE_FD
:
376 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
378 return u_pipe_screen_get_param_defaults(pscreen
, param
);
383 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
386 case PIPE_CAPF_MAX_LINE_WIDTH
:
387 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
388 /* NOTE: actual value is 127.0f, but this is working around a deqp
389 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
390 * uses too small of a render target size, and gets confused when
391 * the lines start going offscreen.
393 * See: https://code.google.com/p/android/issues/detail?id=206513
395 if (fd_mesa_debug
& FD_DBG_DEQP
)
398 case PIPE_CAPF_MAX_POINT_WIDTH
:
399 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
401 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
403 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
405 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
406 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
407 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
410 debug_printf("unknown paramf %d\n", param
);
415 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
416 enum pipe_shader_type shader
,
417 enum pipe_shader_cap param
)
419 struct fd_screen
*screen
= fd_screen(pscreen
);
423 case PIPE_SHADER_FRAGMENT
:
424 case PIPE_SHADER_VERTEX
:
426 case PIPE_SHADER_COMPUTE
:
427 if (has_compute(screen
))
430 case PIPE_SHADER_GEOMETRY
:
431 /* maye we could emulate.. */
434 DBG("unknown shader type %d", shader
);
438 /* this is probably not totally correct.. but it's a start: */
440 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
441 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
442 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
443 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
445 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
447 case PIPE_SHADER_CAP_MAX_INPUTS
:
448 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
450 case PIPE_SHADER_CAP_MAX_TEMPS
:
451 return 64; /* Max native temporaries. */
452 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
453 /* NOTE: seems to be limit for a3xx is actually 512 but
454 * split between VS and FS. Use lower limit of 256 to
455 * avoid getting into impossible situations:
457 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
458 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
459 return is_ir3(screen
) ? 16 : 1;
460 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
462 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
463 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
464 /* Technically this should be the same as for TEMP/CONST, since
465 * everything is just normal registers. This is just temporary
466 * hack until load_input/store_output handle arrays in a similar
467 * way as load_var/store_var..
470 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
471 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
472 /* a2xx compiler doesn't handle indirect: */
473 return is_ir3(screen
) ? 1 : 0;
474 case PIPE_SHADER_CAP_SUBROUTINES
:
475 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
476 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
477 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
478 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
479 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
480 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
481 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
482 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
483 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
485 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
487 case PIPE_SHADER_CAP_INTEGERS
:
490 return is_ir3(screen
) ? 1 : 0;
491 case PIPE_SHADER_CAP_INT64_ATOMICS
:
493 case PIPE_SHADER_CAP_FP16
:
495 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
496 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
498 case PIPE_SHADER_CAP_PREFERRED_IR
:
500 return PIPE_SHADER_IR_NIR
;
501 return PIPE_SHADER_IR_TGSI
;
502 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
503 if (is_ir3(screen
)) {
504 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
506 return (1 << PIPE_SHADER_IR_TGSI
);
509 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
511 case PIPE_SHADER_CAP_SCALAR_ISA
:
512 return is_ir3(screen
) ? 1 : 0;
513 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
514 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
515 if (is_a5xx(screen
) || is_a6xx(screen
)) {
516 /* a5xx (and a4xx for that matter) has one state-block
517 * for compute-shader SSBO's and another that is shared
518 * by VS/HS/DS/GS/FS.. so to simplify things for now
519 * just advertise SSBOs for FS and CS. We could possibly
520 * do what blob does, and partition the space for
521 * VS/HS/DS/GS/FS. The blob advertises:
523 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
524 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
525 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
526 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
527 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
528 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
529 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
531 * I think that way we could avoid having to patch shaders
532 * for actual SSBO indexes by using a static partitioning.
534 * Note same state block is used for images and buffers,
535 * but images also need texture state for read access
540 case PIPE_SHADER_FRAGMENT
:
541 case PIPE_SHADER_COMPUTE
:
549 debug_printf("unknown shader param %d\n", param
);
553 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
554 * into per-generation backend?
557 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
558 enum pipe_compute_cap param
, void *ret
)
560 struct fd_screen
*screen
= fd_screen(pscreen
);
561 const char * const ir
= "ir3";
563 if (!has_compute(screen
))
566 #define RET(x) do { \
568 memcpy(ret, x, sizeof(x)); \
573 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
574 // don't expose 64b pointer support yet, until ir3 supports 64b
575 // math, otherwise spir64 target is used and we get 64b pointer
576 // calculations that we can't do yet
577 // if (is_a5xx(screen))
578 // RET((uint32_t []){ 64 });
579 RET((uint32_t []){ 32 });
581 case PIPE_COMPUTE_CAP_IR_TARGET
:
584 return strlen(ir
) * sizeof(char);
586 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
587 RET((uint64_t []) { 3 });
589 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
590 RET(((uint64_t []) { 65535, 65535, 65535 }));
592 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
593 RET(((uint64_t []) { 1024, 1024, 64 }));
595 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
596 RET((uint64_t []) { 1024 });
598 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
599 RET((uint64_t []) { screen
->ram_size
});
601 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
602 RET((uint64_t []) { 32768 });
604 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
605 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
606 RET((uint64_t []) { 4096 });
608 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
609 RET((uint64_t []) { screen
->ram_size
});
611 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
612 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
614 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
615 RET((uint32_t []) { 9999 }); // TODO
617 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
618 RET((uint32_t []) { 1 });
620 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
621 RET((uint32_t []) { 32 }); // TODO
623 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
624 RET((uint64_t []) { 1024 }); // TODO
631 fd_get_compiler_options(struct pipe_screen
*pscreen
,
632 enum pipe_shader_ir ir
, unsigned shader
)
634 struct fd_screen
*screen
= fd_screen(pscreen
);
637 return ir3_get_compiler_options(screen
->compiler
);
643 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
646 struct winsys_handle
*whandle
)
648 whandle
->stride
= stride
;
650 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
651 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
652 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
653 whandle
->handle
= fd_bo_handle(bo
);
655 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
656 whandle
->handle
= fd_bo_dmabuf(bo
);
664 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
665 struct winsys_handle
*whandle
)
667 struct fd_screen
*screen
= fd_screen(pscreen
);
670 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
671 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
672 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
673 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
674 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
675 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
677 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
682 DBG("ref name 0x%08x failed", whandle
->handle
);
690 fd_screen_create(struct fd_device
*dev
)
692 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
693 struct pipe_screen
*pscreen
;
696 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
698 if (fd_mesa_debug
& FD_DBG_NOBIN
)
699 fd_binning_enabled
= false;
701 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
706 pscreen
= &screen
->base
;
711 // maybe this should be in context?
712 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
714 DBG("could not create 3d pipe");
718 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
719 DBG("could not get GMEM size");
722 screen
->gmemsize_bytes
= val
;
724 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
725 DBG("could not get device-id");
728 screen
->device_id
= val
;
730 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
731 DBG("could not get gpu freq");
732 /* this limits what performance related queries are
733 * supported but is not fatal
735 screen
->max_freq
= 0;
737 screen
->max_freq
= val
;
738 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
739 screen
->has_timestamp
= true;
742 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
743 DBG("could not get gpu-id");
746 screen
->gpu_id
= val
;
748 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
749 DBG("could not get chip-id");
750 /* older kernels may not have this property: */
751 unsigned core
= screen
->gpu_id
/ 100;
752 unsigned major
= (screen
->gpu_id
% 100) / 10;
753 unsigned minor
= screen
->gpu_id
% 10;
754 unsigned patch
= 0; /* assume the worst */
755 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
756 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
758 screen
->chip_id
= val
;
760 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
761 DBG("could not get # of rings");
762 screen
->priority_mask
= 0;
764 /* # of rings equates to number of unique priority values: */
765 screen
->priority_mask
= (1 << val
) - 1;
770 screen
->ram_size
= si
.totalram
;
773 DBG(" GPU-id: %d", screen
->gpu_id
);
774 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
775 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
777 /* explicitly checking for GPU revisions that are known to work. This
778 * may be overly conservative for a3xx, where spoofing the gpu_id with
779 * the blob driver seems to generate identical cmdstream dumps. But
780 * on a2xx, there seem to be small differences between the GPU revs
781 * so it is probably better to actually test first on real hardware
784 * If you have a different adreno version, feel free to add it to one
785 * of the cases below and see what happens. And if it works, please
788 switch (screen
->gpu_id
) {
793 fd2_screen_init(pscreen
);
799 fd3_screen_init(pscreen
);
803 fd4_screen_init(pscreen
);
806 fd5_screen_init(pscreen
);
809 fd6_screen_init(pscreen
);
812 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
816 if (screen
->gpu_id
>= 600) {
817 screen
->gmem_alignw
= 32;
818 screen
->gmem_alignh
= 32;
819 screen
->num_vsc_pipes
= 32;
820 } else if (screen
->gpu_id
>= 500) {
821 screen
->gmem_alignw
= 64;
822 screen
->gmem_alignh
= 32;
823 screen
->num_vsc_pipes
= 16;
825 screen
->gmem_alignw
= 32;
826 screen
->gmem_alignh
= 32;
827 screen
->num_vsc_pipes
= 8;
830 /* NOTE: don't enable reordering on a2xx, since completely untested.
831 * Also, don't enable if we have too old of a kernel to support
832 * growable cmdstream buffers, since memory requirement for cmdstream
833 * buffers would be too much otherwise.
835 if ((screen
->gpu_id
>= 300) && (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
))
836 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
838 fd_bc_init(&screen
->batch_cache
);
840 (void) mtx_init(&screen
->lock
, mtx_plain
);
842 pscreen
->destroy
= fd_screen_destroy
;
843 pscreen
->get_param
= fd_screen_get_param
;
844 pscreen
->get_paramf
= fd_screen_get_paramf
;
845 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
846 pscreen
->get_compute_param
= fd_get_compute_param
;
847 pscreen
->get_compiler_options
= fd_get_compiler_options
;
849 fd_resource_screen_init(pscreen
);
850 fd_query_screen_init(pscreen
);
852 pscreen
->get_name
= fd_screen_get_name
;
853 pscreen
->get_vendor
= fd_screen_get_vendor
;
854 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
856 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
858 pscreen
->fence_reference
= fd_fence_ref
;
859 pscreen
->fence_finish
= fd_fence_finish
;
860 pscreen
->fence_get_fd
= fd_fence_get_fd
;
862 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
867 fd_screen_destroy(pscreen
);