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gallium: Add pipe cap for primitive restart with fixed index
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60
61 #include "ir3/ir3_nir.h"
62 #include "a2xx/ir2.h"
63
64 static const struct debug_named_value debug_options[] = {
65 {"msgs", FD_DBG_MSGS, "Print debug messages"},
66 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
67 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
68 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
69 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
70 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
71 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
72 {"log", FD_DBG_LOG, "Enable GPU timestamp based logging (a6xx+)"},
73 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
74 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
75 /* BIT(10) */
76 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
77 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
78 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
79 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
80 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
81 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
82 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
83 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
84 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
85 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
86 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
87 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
88 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
89 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
90 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
91 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
92 {"nofp16", FD_DBG_NOFP16, "Disable mediump precision lowering"},
93 {"nohw", FD_DBG_NOHW, "Disable submitting commands to the HW"},
94 DEBUG_NAMED_VALUE_END
95 };
96
97 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
98
99 int fd_mesa_debug = 0;
100 bool fd_binning_enabled = true;
101
102 static const char *
103 fd_screen_get_name(struct pipe_screen *pscreen)
104 {
105 static char buffer[128];
106 snprintf(buffer, sizeof(buffer), "FD%03d",
107 fd_screen(pscreen)->device_id);
108 return buffer;
109 }
110
111 static const char *
112 fd_screen_get_vendor(struct pipe_screen *pscreen)
113 {
114 return "freedreno";
115 }
116
117 static const char *
118 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
119 {
120 return "Qualcomm";
121 }
122
123
124 static uint64_t
125 fd_screen_get_timestamp(struct pipe_screen *pscreen)
126 {
127 struct fd_screen *screen = fd_screen(pscreen);
128
129 if (screen->has_timestamp) {
130 uint64_t n;
131 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
132 debug_assert(screen->max_freq > 0);
133 return n * 1000000000 / screen->max_freq;
134 } else {
135 int64_t cpu_time = os_time_get() * 1000;
136 return cpu_time + screen->cpu_gpu_time_delta;
137 }
138
139 }
140
141 static void
142 fd_screen_destroy(struct pipe_screen *pscreen)
143 {
144 struct fd_screen *screen = fd_screen(pscreen);
145
146 if (screen->pipe)
147 fd_pipe_del(screen->pipe);
148
149 if (screen->dev)
150 fd_device_del(screen->dev);
151
152 if (screen->ro)
153 FREE(screen->ro);
154
155 fd_bc_fini(&screen->batch_cache);
156 fd_gmem_screen_fini(pscreen);
157
158 slab_destroy_parent(&screen->transfer_pool);
159
160 simple_mtx_destroy(&screen->lock);
161
162 ralloc_free(screen->compiler);
163 ralloc_free(screen->live_batches);
164
165 free(screen->perfcntr_queries);
166 free(screen);
167 }
168
169 /*
170 TODO either move caps to a2xx/a3xx specific code, or maybe have some
171 tables for things that differ if the delta is not too much..
172 */
173 static int
174 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
175 {
176 struct fd_screen *screen = fd_screen(pscreen);
177
178 /* this is probably not totally correct.. but it's a start: */
179 switch (param) {
180 /* Supported features (boolean caps). */
181 case PIPE_CAP_NPOT_TEXTURES:
182 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_POINT_SPRITE:
185 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
186 case PIPE_CAP_TEXTURE_SWIZZLE:
187 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
188 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
189 case PIPE_CAP_SEAMLESS_CUBE_MAP:
190 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
191 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
192 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
193 case PIPE_CAP_STRING_MARKER:
194 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
195 case PIPE_CAP_TEXTURE_BARRIER:
196 case PIPE_CAP_INVALIDATE_BUFFER:
197 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
198 return 1;
199
200 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
201 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
202 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
203 return !is_a2xx(screen);
204
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
206 return is_a2xx(screen);
207 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
208 return !is_a2xx(screen);
209
210 case PIPE_CAP_PACKED_UNIFORMS:
211 return !is_a2xx(screen);
212
213 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
214 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
215 return screen->has_robustness;
216
217 case PIPE_CAP_VERTEXID_NOBASE:
218 return is_a3xx(screen) || is_a4xx(screen);
219
220 case PIPE_CAP_COMPUTE:
221 return has_compute(screen);
222
223 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
224 case PIPE_CAP_PCI_GROUP:
225 case PIPE_CAP_PCI_BUS:
226 case PIPE_CAP_PCI_DEVICE:
227 case PIPE_CAP_PCI_FUNCTION:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
229 return 0;
230
231 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
232 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
233 case PIPE_CAP_VERTEX_SHADER_SATURATE:
234 case PIPE_CAP_PRIMITIVE_RESTART:
235 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
236 case PIPE_CAP_TGSI_INSTANCEID:
237 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
238 case PIPE_CAP_INDEP_BLEND_ENABLE:
239 case PIPE_CAP_INDEP_BLEND_FUNC:
240 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
241 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
242 case PIPE_CAP_CONDITIONAL_RENDER:
243 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
244 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
245 case PIPE_CAP_CLIP_HALFZ:
246 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
247
248 case PIPE_CAP_FAKE_SW_MSAA:
249 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
250
251 case PIPE_CAP_TEXTURE_MULTISAMPLE:
252 return is_a5xx(screen) || is_a6xx(screen);
253
254 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
255 return is_a6xx(screen);
256
257 case PIPE_CAP_DEPTH_CLIP_DISABLE:
258 return is_a3xx(screen) || is_a4xx(screen);
259
260 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
261 return is_a5xx(screen) || is_a6xx(screen);
262
263 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
264 if (is_a3xx(screen)) return 16;
265 if (is_a4xx(screen)) return 32;
266 if (is_a5xx(screen)) return 32;
267 if (is_a6xx(screen)) return 64;
268 return 0;
269 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
270 /* We could possibly emulate more by pretending 2d/rect textures and
271 * splitting high bits of index into 2nd dimension..
272 */
273 if (is_a3xx(screen)) return 8192;
274 if (is_a4xx(screen)) return 16384;
275 if (is_a5xx(screen)) return 16384;
276 if (is_a6xx(screen)) return 1 << 27;
277 return 0;
278
279 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
280 case PIPE_CAP_CUBE_MAP_ARRAY:
281 case PIPE_CAP_SAMPLER_VIEW_TARGET:
282 case PIPE_CAP_TEXTURE_QUERY_LOD:
283 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
284
285 case PIPE_CAP_START_INSTANCE:
286 /* Note that a5xx can do this, it just can't (at least with
287 * current firmware) do draw_indirect with base_instance.
288 * Since draw_indirect is needed sooner (gles31 and gl40 vs
289 * gl42), hide base_instance on a5xx. :-/
290 */
291 return is_a4xx(screen);
292
293 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
294 return 64;
295
296 case PIPE_CAP_GLSL_FEATURE_LEVEL:
297 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
298 return is_ir3(screen) ? 140 : 120;
299
300 case PIPE_CAP_ESSL_FEATURE_LEVEL:
301 /* we can probably enable 320 for a5xx too, but need to test: */
302 if (is_a6xx(screen)) return 320;
303 if (is_a5xx(screen)) return 310;
304 if (is_ir3(screen)) return 300;
305 return 120;
306
307 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
308 if (is_a6xx(screen)) return 64;
309 if (is_a5xx(screen)) return 4;
310 return 0;
311
312 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
313 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
314 return 4;
315 return 0;
316
317 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
318 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
319 return 0;
320
321 case PIPE_CAP_FBFETCH:
322 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
323 is_a6xx(screen))
324 return 1;
325 return 0;
326 case PIPE_CAP_SAMPLE_SHADING:
327 if (is_a6xx(screen)) return 1;
328 return 0;
329
330 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
331 return screen->priority_mask;
332
333 case PIPE_CAP_DRAW_INDIRECT:
334 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
335 return 1;
336 return 0;
337
338 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
339 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
340 return 1;
341 return 0;
342
343 case PIPE_CAP_LOAD_CONSTBUF:
344 /* name is confusing, but this turns on std430 packing */
345 if (is_ir3(screen))
346 return 1;
347 return 0;
348
349 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
350 return 0;
351
352 case PIPE_CAP_MAX_VIEWPORTS:
353 return 1;
354
355 case PIPE_CAP_MAX_VARYINGS:
356 return 16;
357
358 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
359 /* We don't really have a limit on this, it all goes into the main
360 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
361 * for GL_MAX_TESS_PATCH_COMPONENTS).
362 */
363 return 128;
364
365 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
366 return 64 * 1024 * 1024;
367
368 case PIPE_CAP_SHAREABLE_SHADERS:
369 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
370 /* manage the variants for these ourself, to avoid breaking precompile: */
371 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
372 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
373 if (is_ir3(screen))
374 return 1;
375 return 0;
376
377 /* Geometry shaders.. */
378 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
379 return 512;
380 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
381 return 2048;
382 case PIPE_CAP_MAX_GS_INVOCATIONS:
383 return 32;
384
385 /* Stream output. */
386 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
387 if (is_ir3(screen))
388 return PIPE_MAX_SO_BUFFERS;
389 return 0;
390 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
391 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
392 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
393 if (is_ir3(screen))
394 return 1;
395 return 0;
396 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
397 return 1;
398 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
399 return is_a2xx(screen);
400 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
401 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
402 if (is_ir3(screen))
403 return 16 * 4; /* should only be shader out limit? */
404 return 0;
405
406 /* Texturing. */
407 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
408 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
409 return 16384;
410 else
411 return 8192;
412 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
413 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
414 return 15;
415 else
416 return 14;
417 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
418 return 11;
419
420 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
421 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
422
423 /* Render targets. */
424 case PIPE_CAP_MAX_RENDER_TARGETS:
425 return screen->max_rts;
426 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
427 return is_a3xx(screen) ? 1 : 0;
428
429 /* Queries. */
430 case PIPE_CAP_OCCLUSION_QUERY:
431 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
432 case PIPE_CAP_QUERY_TIMESTAMP:
433 case PIPE_CAP_QUERY_TIME_ELAPSED:
434 /* only a4xx, requires new enough kernel so we know max_freq: */
435 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
436
437 case PIPE_CAP_VENDOR_ID:
438 return 0x5143;
439 case PIPE_CAP_DEVICE_ID:
440 return 0xFFFFFFFF;
441 case PIPE_CAP_ACCELERATED:
442 return 1;
443 case PIPE_CAP_VIDEO_MEMORY:
444 DBG("FINISHME: The value returned is incorrect\n");
445 return 10;
446 case PIPE_CAP_UMA:
447 return 1;
448 case PIPE_CAP_NATIVE_FENCE_FD:
449 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
450 default:
451 return u_pipe_screen_get_param_defaults(pscreen, param);
452 }
453 }
454
455 static float
456 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
457 {
458 switch (param) {
459 case PIPE_CAPF_MAX_LINE_WIDTH:
460 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
461 /* NOTE: actual value is 127.0f, but this is working around a deqp
462 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
463 * uses too small of a render target size, and gets confused when
464 * the lines start going offscreen.
465 *
466 * See: https://code.google.com/p/android/issues/detail?id=206513
467 */
468 if (fd_mesa_debug & FD_DBG_DEQP)
469 return 48.0f;
470 return 127.0f;
471 case PIPE_CAPF_MAX_POINT_WIDTH:
472 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
473 return 4092.0f;
474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
475 return 16.0f;
476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
477 return 15.0f;
478 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
479 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
480 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
481 return 0.0f;
482 }
483 debug_printf("unknown paramf %d\n", param);
484 return 0;
485 }
486
487 static int
488 fd_screen_get_shader_param(struct pipe_screen *pscreen,
489 enum pipe_shader_type shader,
490 enum pipe_shader_cap param)
491 {
492 struct fd_screen *screen = fd_screen(pscreen);
493
494 switch(shader)
495 {
496 case PIPE_SHADER_FRAGMENT:
497 case PIPE_SHADER_VERTEX:
498 break;
499 case PIPE_SHADER_TESS_CTRL:
500 case PIPE_SHADER_TESS_EVAL:
501 case PIPE_SHADER_GEOMETRY:
502 if (is_a6xx(screen))
503 break;
504 return 0;
505 case PIPE_SHADER_COMPUTE:
506 if (has_compute(screen))
507 break;
508 return 0;
509 default:
510 DBG("unknown shader type %d", shader);
511 return 0;
512 }
513
514 /* this is probably not totally correct.. but it's a start: */
515 switch (param) {
516 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
517 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
518 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
519 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
520 return 16384;
521 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
522 return 8; /* XXX */
523 case PIPE_SHADER_CAP_MAX_INPUTS:
524 case PIPE_SHADER_CAP_MAX_OUTPUTS:
525 return 16;
526 case PIPE_SHADER_CAP_MAX_TEMPS:
527 return 64; /* Max native temporaries. */
528 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
529 /* NOTE: seems to be limit for a3xx is actually 512 but
530 * split between VS and FS. Use lower limit of 256 to
531 * avoid getting into impossible situations:
532 */
533 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
534 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
535 return is_ir3(screen) ? 16 : 1;
536 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
537 return 1;
538 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
539 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
540 /* Technically this should be the same as for TEMP/CONST, since
541 * everything is just normal registers. This is just temporary
542 * hack until load_input/store_output handle arrays in a similar
543 * way as load_var/store_var..
544 *
545 * For tessellation stages, inputs are loaded using ldlw or ldg, both
546 * of which support indirection.
547 */
548 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
549 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
550 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
551 /* a2xx compiler doesn't handle indirect: */
552 return is_ir3(screen) ? 1 : 0;
553 case PIPE_SHADER_CAP_SUBROUTINES:
554 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
555 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
556 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
557 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
558 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
559 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
560 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
561 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
562 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
563 return 0;
564 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
565 return 1;
566 case PIPE_SHADER_CAP_INTEGERS:
567 return is_ir3(screen) ? 1 : 0;
568 case PIPE_SHADER_CAP_INT64_ATOMICS:
569 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
570 case PIPE_SHADER_CAP_INT16:
571 return 0;
572 case PIPE_SHADER_CAP_FP16:
573 return ((is_a5xx(screen) || is_a6xx(screen)) &&
574 (shader == PIPE_SHADER_COMPUTE ||
575 shader == PIPE_SHADER_FRAGMENT) &&
576 !(fd_mesa_debug & FD_DBG_NOFP16));
577 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
578 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
579 return 16;
580 case PIPE_SHADER_CAP_PREFERRED_IR:
581 return PIPE_SHADER_IR_NIR;
582 case PIPE_SHADER_CAP_SUPPORTED_IRS:
583 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
584 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
585 return 32;
586 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
587 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
588 if (is_a5xx(screen) || is_a6xx(screen)) {
589 /* a5xx (and a4xx for that matter) has one state-block
590 * for compute-shader SSBO's and another that is shared
591 * by VS/HS/DS/GS/FS.. so to simplify things for now
592 * just advertise SSBOs for FS and CS. We could possibly
593 * do what blob does, and partition the space for
594 * VS/HS/DS/GS/FS. The blob advertises:
595 *
596 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
597 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
598 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
599 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
600 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
601 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
602 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
603 *
604 * I think that way we could avoid having to patch shaders
605 * for actual SSBO indexes by using a static partitioning.
606 *
607 * Note same state block is used for images and buffers,
608 * but images also need texture state for read access
609 * (isam/isam.3d)
610 */
611 switch(shader)
612 {
613 case PIPE_SHADER_FRAGMENT:
614 case PIPE_SHADER_COMPUTE:
615 return 24;
616 default:
617 return 0;
618 }
619 }
620 return 0;
621 }
622 debug_printf("unknown shader param %d\n", param);
623 return 0;
624 }
625
626 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
627 * into per-generation backend?
628 */
629 static int
630 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
631 enum pipe_compute_cap param, void *ret)
632 {
633 struct fd_screen *screen = fd_screen(pscreen);
634 const char * const ir = "ir3";
635
636 if (!has_compute(screen))
637 return 0;
638
639 #define RET(x) do { \
640 if (ret) \
641 memcpy(ret, x, sizeof(x)); \
642 return sizeof(x); \
643 } while (0)
644
645 switch (param) {
646 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
647 // don't expose 64b pointer support yet, until ir3 supports 64b
648 // math, otherwise spir64 target is used and we get 64b pointer
649 // calculations that we can't do yet
650 // if (is_a5xx(screen))
651 // RET((uint32_t []){ 64 });
652 RET((uint32_t []){ 32 });
653
654 case PIPE_COMPUTE_CAP_IR_TARGET:
655 if (ret)
656 sprintf(ret, "%s", ir);
657 return strlen(ir) * sizeof(char);
658
659 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
660 RET((uint64_t []) { 3 });
661
662 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
663 RET(((uint64_t []) { 65535, 65535, 65535 }));
664
665 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
666 RET(((uint64_t []) { 1024, 1024, 64 }));
667
668 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
669 RET((uint64_t []) { 1024 });
670
671 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
672 RET((uint64_t []) { screen->ram_size });
673
674 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
675 RET((uint64_t []) { 32768 });
676
677 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
678 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
679 RET((uint64_t []) { 4096 });
680
681 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
682 RET((uint64_t []) { screen->ram_size });
683
684 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
685 RET((uint32_t []) { screen->max_freq / 1000000 });
686
687 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
688 RET((uint32_t []) { 9999 }); // TODO
689
690 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
691 RET((uint32_t []) { 1 });
692
693 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
694 RET((uint32_t []) { 32 }); // TODO
695
696 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
697 RET((uint64_t []) { 1024 }); // TODO
698 }
699
700 return 0;
701 }
702
703 static const void *
704 fd_get_compiler_options(struct pipe_screen *pscreen,
705 enum pipe_shader_ir ir, unsigned shader)
706 {
707 struct fd_screen *screen = fd_screen(pscreen);
708
709 if (is_ir3(screen))
710 return ir3_get_compiler_options(screen->compiler);
711
712 return ir2_get_compiler_options();
713 }
714
715 bool
716 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
717 struct fd_bo *bo,
718 struct renderonly_scanout *scanout,
719 unsigned stride,
720 struct winsys_handle *whandle)
721 {
722 whandle->stride = stride;
723
724 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
725 return fd_bo_get_name(bo, &whandle->handle) == 0;
726 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
727 if (renderonly_get_handle(scanout, whandle))
728 return true;
729 whandle->handle = fd_bo_handle(bo);
730 return true;
731 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
732 whandle->handle = fd_bo_dmabuf(bo);
733 return true;
734 } else {
735 return false;
736 }
737 }
738
739 static void
740 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
741 enum pipe_format format,
742 int max, uint64_t *modifiers,
743 unsigned int *external_only,
744 int *count)
745 {
746 struct fd_screen *screen = fd_screen(pscreen);
747 int i, num = 0;
748
749 max = MIN2(max, screen->num_supported_modifiers);
750
751 if (!max) {
752 max = screen->num_supported_modifiers;
753 external_only = NULL;
754 modifiers = NULL;
755 }
756
757 for (i = 0; i < max; i++) {
758 if (modifiers)
759 modifiers[num] = screen->supported_modifiers[i];
760
761 if (external_only)
762 external_only[num] = 0;
763
764 num++;
765 }
766
767 *count = num;
768 }
769
770 struct fd_bo *
771 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
772 struct winsys_handle *whandle)
773 {
774 struct fd_screen *screen = fd_screen(pscreen);
775 struct fd_bo *bo;
776
777 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
778 bo = fd_bo_from_name(screen->dev, whandle->handle);
779 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
780 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
781 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
782 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
783 } else {
784 DBG("Attempt to import unsupported handle type %d", whandle->type);
785 return NULL;
786 }
787
788 if (!bo) {
789 DBG("ref name 0x%08x failed", whandle->handle);
790 return NULL;
791 }
792
793 return bo;
794 }
795
796 static void _fd_fence_ref(struct pipe_screen *pscreen,
797 struct pipe_fence_handle **ptr,
798 struct pipe_fence_handle *pfence)
799 {
800 fd_fence_ref(ptr, pfence);
801 }
802
803 struct pipe_screen *
804 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
805 {
806 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
807 struct pipe_screen *pscreen;
808 uint64_t val;
809
810 fd_mesa_debug = debug_get_option_fd_mesa_debug();
811
812 if (fd_mesa_debug & FD_DBG_NOBIN)
813 fd_binning_enabled = false;
814
815 if (!screen)
816 return NULL;
817
818 pscreen = &screen->base;
819
820 screen->dev = dev;
821 screen->refcnt = 1;
822
823 if (ro) {
824 screen->ro = renderonly_dup(ro);
825 if (!screen->ro) {
826 DBG("could not create renderonly object");
827 goto fail;
828 }
829 }
830
831 // maybe this should be in context?
832 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
833 if (!screen->pipe) {
834 DBG("could not create 3d pipe");
835 goto fail;
836 }
837
838 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
839 DBG("could not get GMEM size");
840 goto fail;
841 }
842 screen->gmemsize_bytes = val;
843
844 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
845 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
846 }
847
848 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
849 DBG("could not get device-id");
850 goto fail;
851 }
852 screen->device_id = val;
853
854 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
855 DBG("could not get gpu freq");
856 /* this limits what performance related queries are
857 * supported but is not fatal
858 */
859 screen->max_freq = 0;
860 } else {
861 screen->max_freq = val;
862 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
863 screen->has_timestamp = true;
864 }
865
866 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
867 DBG("could not get gpu-id");
868 goto fail;
869 }
870 screen->gpu_id = val;
871
872 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
873 DBG("could not get chip-id");
874 /* older kernels may not have this property: */
875 unsigned core = screen->gpu_id / 100;
876 unsigned major = (screen->gpu_id % 100) / 10;
877 unsigned minor = screen->gpu_id % 10;
878 unsigned patch = 0; /* assume the worst */
879 val = (patch & 0xff) | ((minor & 0xff) << 8) |
880 ((major & 0xff) << 16) | ((core & 0xff) << 24);
881 }
882 screen->chip_id = val;
883
884 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
885 DBG("could not get # of rings");
886 screen->priority_mask = 0;
887 } else {
888 /* # of rings equates to number of unique priority values: */
889 screen->priority_mask = (1 << val) - 1;
890 }
891
892 if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
893 screen->has_robustness = true;
894
895 struct sysinfo si;
896 sysinfo(&si);
897 screen->ram_size = si.totalram;
898
899 DBG("Pipe Info:");
900 DBG(" GPU-id: %d", screen->gpu_id);
901 DBG(" Chip-id: 0x%08x", screen->chip_id);
902 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
903
904 /* explicitly checking for GPU revisions that are known to work. This
905 * may be overly conservative for a3xx, where spoofing the gpu_id with
906 * the blob driver seems to generate identical cmdstream dumps. But
907 * on a2xx, there seem to be small differences between the GPU revs
908 * so it is probably better to actually test first on real hardware
909 * before enabling:
910 *
911 * If you have a different adreno version, feel free to add it to one
912 * of the cases below and see what happens. And if it works, please
913 * send a patch ;-)
914 */
915 switch (screen->gpu_id) {
916 case 200:
917 case 201:
918 case 205:
919 case 220:
920 fd2_screen_init(pscreen);
921 break;
922 case 305:
923 case 307:
924 case 320:
925 case 330:
926 fd3_screen_init(pscreen);
927 break;
928 case 405:
929 case 420:
930 case 430:
931 fd4_screen_init(pscreen);
932 break;
933 case 510:
934 case 530:
935 case 540:
936 fd5_screen_init(pscreen);
937 break;
938 case 618:
939 case 630:
940 case 640:
941 case 650:
942 fd6_screen_init(pscreen);
943 break;
944 default:
945 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
946 goto fail;
947 }
948
949 if (screen->gpu_id >= 600) {
950 screen->gmem_alignw = 16;
951 screen->gmem_alignh = 4;
952 screen->tile_alignw = is_a650(screen) ? 96 : 32;
953 screen->tile_alignh = 32;
954 screen->num_vsc_pipes = 32;
955 } else if (screen->gpu_id >= 500) {
956 screen->gmem_alignw = screen->tile_alignw = 64;
957 screen->gmem_alignh = screen->tile_alignh = 32;
958 screen->num_vsc_pipes = 16;
959 } else {
960 screen->gmem_alignw = screen->tile_alignw = 32;
961 screen->gmem_alignh = screen->tile_alignh = 32;
962 screen->num_vsc_pipes = 8;
963 }
964
965 if (fd_mesa_debug & FD_DBG_PERFC) {
966 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
967 &screen->num_perfcntr_groups);
968 }
969
970 /* NOTE: don't enable if we have too old of a kernel to support
971 * growable cmdstream buffers, since memory requirement for cmdstream
972 * buffers would be too much otherwise.
973 */
974 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
975 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
976
977 if (BATCH_DEBUG)
978 screen->live_batches = _mesa_pointer_set_create(NULL);
979
980 fd_bc_init(&screen->batch_cache);
981
982 list_inithead(&screen->context_list);
983
984 (void) simple_mtx_init(&screen->lock, mtx_plain);
985
986 pscreen->destroy = fd_screen_destroy;
987 pscreen->get_param = fd_screen_get_param;
988 pscreen->get_paramf = fd_screen_get_paramf;
989 pscreen->get_shader_param = fd_screen_get_shader_param;
990 pscreen->get_compute_param = fd_get_compute_param;
991 pscreen->get_compiler_options = fd_get_compiler_options;
992
993 fd_resource_screen_init(pscreen);
994 fd_query_screen_init(pscreen);
995 fd_gmem_screen_init(pscreen);
996
997 pscreen->get_name = fd_screen_get_name;
998 pscreen->get_vendor = fd_screen_get_vendor;
999 pscreen->get_device_vendor = fd_screen_get_device_vendor;
1000
1001 pscreen->get_timestamp = fd_screen_get_timestamp;
1002
1003 pscreen->fence_reference = _fd_fence_ref;
1004 pscreen->fence_finish = fd_fence_finish;
1005 pscreen->fence_get_fd = fd_fence_get_fd;
1006
1007 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1008
1009 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1010
1011 return pscreen;
1012
1013 fail:
1014 fd_screen_destroy(pscreen);
1015 return NULL;
1016 }