src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58
  59 #include "ir3/ir3_nir.h"
  60
  61 /* XXX this should go away */
  62 #include "state_tracker/drm_driver.h"
  63
  64 static const struct debug_named_value debug_options[] = {
  65                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  66                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  67                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  68                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  69                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  70                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  71                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  72                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  73                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  74                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  75                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  76                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  77                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  78                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  79                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  82                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  83                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  84                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  85                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  86                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  87                 DEBUG_NAMED_VALUE_END
  88 };
  89
  90 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  91
  92 int fd_mesa_debug = 0;
  93 bool fd_binning_enabled = true;
  94 static bool glsl120 = false;
  95
  96 static const char *
  97 fd_screen_get_name(struct pipe_screen *pscreen)
  98 {
  99         static char buffer[128];
 100         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 101                         fd_screen(pscreen)->device_id);
 102         return buffer;
 103 }
 104
 105 static const char *
 106 fd_screen_get_vendor(struct pipe_screen *pscreen)
 107 {
 108         return "freedreno";
 109 }
 110
 111 static const char *
 112 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 113 {
 114         return "Qualcomm";
 115 }
 116
 117
 118 static uint64_t
 119 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 120 {
 121         struct fd_screen *screen = fd_screen(pscreen);
 122
 123         if (screen->has_timestamp) {
 124                 uint64_t n;
 125                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 126                 debug_assert(screen->max_freq > 0);
 127                 return n * 1000000000 / screen->max_freq;
 128         } else {
 129                 int64_t cpu_time = os_time_get() * 1000;
 130                 return cpu_time + screen->cpu_gpu_time_delta;
 131         }
 132
 133 }
 134
 135 static void
 136 fd_screen_destroy(struct pipe_screen *pscreen)
 137 {
 138         struct fd_screen *screen = fd_screen(pscreen);
 139
 140         if (screen->pipe)
 141                 fd_pipe_del(screen->pipe);
 142
 143         if (screen->dev)
 144                 fd_device_del(screen->dev);
 145
 146         fd_bc_fini(&screen->batch_cache);
 147
 148         slab_destroy_parent(&screen->transfer_pool);
 149
 150         mtx_destroy(&screen->lock);
 151
 152         ralloc_free(screen->compiler);
 153
 154         free(screen);
 155 }
 156
 157 /*
 158 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 159 tables for things that differ if the delta is not too much..
 160  */
 161 static int
 162 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 163 {
 164         struct fd_screen *screen = fd_screen(pscreen);
 165
 166         /* this is probably not totally correct.. but it's a start: */
 167         switch (param) {
 168         /* Supported features (boolean caps). */
 169         case PIPE_CAP_NPOT_TEXTURES:
 170         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 171         case PIPE_CAP_ANISOTROPIC_FILTER:
 172         case PIPE_CAP_POINT_SPRITE:
 173         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 174         case PIPE_CAP_TEXTURE_SWIZZLE:
 175         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 176         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 177         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 178         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 179         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 180         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 181         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 182         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 183         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 184         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 185         case PIPE_CAP_STRING_MARKER:
 186         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 187         case PIPE_CAP_TEXTURE_BARRIER:
 188         case PIPE_CAP_INVALIDATE_BUFFER:
 189                 return 1;
 190
 191         case PIPE_CAP_VERTEXID_NOBASE:
 192                 return is_a3xx(screen) || is_a4xx(screen);
 193
 194         case PIPE_CAP_COMPUTE:
 195                 return has_compute(screen);
 196
 197         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 198         case PIPE_CAP_TGSI_TEXCOORD:
 199         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 200         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 201         case PIPE_CAP_QUERY_MEMORY_INFO:
 202         case PIPE_CAP_PCI_GROUP:
 203         case PIPE_CAP_PCI_BUS:
 204         case PIPE_CAP_PCI_DEVICE:
 205         case PIPE_CAP_PCI_FUNCTION:
 206                 return 0;
 207
 208         case PIPE_CAP_SM3:
 209         case PIPE_CAP_PRIMITIVE_RESTART:
 210         case PIPE_CAP_TGSI_INSTANCEID:
 211         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 212         case PIPE_CAP_INDEP_BLEND_ENABLE:
 213         case PIPE_CAP_INDEP_BLEND_FUNC:
 214         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216         case PIPE_CAP_CONDITIONAL_RENDER:
 217         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 218         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 219         case PIPE_CAP_CLIP_HALFZ:
 220                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 221
 222         case PIPE_CAP_FAKE_SW_MSAA:
 223                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 224
 225         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 226                 return is_a5xx(screen);
 227
 228         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 229                 return is_a3xx(screen) || is_a4xx(screen);
 230
 231         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 232                 return is_a5xx(screen);
 233
 234         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 235                 return 0;
 236         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 237                 if (is_a3xx(screen)) return 16;
 238                 if (is_a4xx(screen)) return 32;
 239                 if (is_a5xx(screen)) return 32;
 240                 return 0;
 241         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 242                 /* We could possibly emulate more by pretending 2d/rect textures and
 243                  * splitting high bits of index into 2nd dimension..
 244                  */
 245                 if (is_a3xx(screen)) return 8192;
 246                 if (is_a4xx(screen)) return 16384;
 247                 if (is_a5xx(screen)) return 16384;
 248                 return 0;
 249
 250         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 251         case PIPE_CAP_CUBE_MAP_ARRAY:
 252         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 253         case PIPE_CAP_TEXTURE_QUERY_LOD:
 254                 return is_a4xx(screen) || is_a5xx(screen);
 255
 256         case PIPE_CAP_START_INSTANCE:
 257                 /* Note that a5xx can do this, it just can't (at least with
 258                  * current firmware) do draw_indirect with base_instance.
 259                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 260                  * gl42), hide base_instance on a5xx.  :-/
 261                  */
 262                 return is_a4xx(screen);
 263
 264         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 265                 return 64;
 266
 267         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 268         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 269                 if (glsl120)
 270                         return 120;
 271                 return is_ir3(screen) ? 140 : 120;
 272
 273         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 274                 if (is_a5xx(screen))
 275                         return 4;
 276                 return 0;
 277
 278         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 279                 if (is_a4xx(screen) || is_a5xx(screen))
 280                         return 4;
 281                 return 0;
 282
 283         /* Unsupported features. */
 284         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 285         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 286         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 287         case PIPE_CAP_USER_VERTEX_BUFFERS:
 288         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 289         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 290         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 291         case PIPE_CAP_TEXTURE_GATHER_SM5:
 292         case PIPE_CAP_SAMPLE_SHADING:
 293         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 294         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 295         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 296         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 297         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 298         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 299         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 300         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 301         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 302         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 303         case PIPE_CAP_TGSI_TXQS:
 304         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 305         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 306         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 307         case PIPE_CAP_CLEAR_TEXTURE:
 308         case PIPE_CAP_DRAW_PARAMETERS:
 309         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 310         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 311         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 312         case PIPE_CAP_GENERATE_MIPMAP:
 313         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 314         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 315         case PIPE_CAP_CULL_DISTANCE:
 316         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 317         case PIPE_CAP_TGSI_VOTE:
 318         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 319         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 320         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 321         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 322         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 323         case PIPE_CAP_TGSI_FS_FBFETCH:
 324         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 325         case PIPE_CAP_DOUBLES:
 326         case PIPE_CAP_INT64:
 327         case PIPE_CAP_INT64_DIVMOD:
 328         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 329         case PIPE_CAP_TGSI_CLOCK:
 330         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 331         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 332         case PIPE_CAP_TGSI_BALLOT:
 333         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 334         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 335         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 336         case PIPE_CAP_POST_DEPTH_COVERAGE:
 337         case PIPE_CAP_BINDLESS_TEXTURE:
 338         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 339         case PIPE_CAP_QUERY_SO_OVERFLOW:
 340         case PIPE_CAP_MEMOBJ:
 341         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 342         case PIPE_CAP_TILE_RASTER_ORDER:
 343         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 344         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 345         case PIPE_CAP_FENCE_SIGNAL:
 346         case PIPE_CAP_CONSTBUF0_FLAGS:
 347         case PIPE_CAP_PACKED_UNIFORMS:
 348         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 349         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 350         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 351         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 352         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 353         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 354         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 355                 return 0;
 356
 357         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 358                 return screen->priority_mask;
 359
 360         case PIPE_CAP_DRAW_INDIRECT:
 361                 if (is_a4xx(screen) || is_a5xx(screen))
 362                         return 1;
 363                 return 0;
 364
 365         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 366                 if (is_a4xx(screen) || is_a5xx(screen))
 367                         return 1;
 368                 return 0;
 369
 370         case PIPE_CAP_LOAD_CONSTBUF:
 371                 /* name is confusing, but this turns on std430 packing */
 372                 if (is_ir3(screen))
 373                         return 1;
 374                 return 0;
 375
 376         case PIPE_CAP_MAX_VIEWPORTS:
 377                 return 1;
 378
 379         case PIPE_CAP_SHAREABLE_SHADERS:
 380         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 381         /* manage the variants for these ourself, to avoid breaking precompile: */
 382         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 383         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 384                 if (is_ir3(screen))
 385                         return 1;
 386                 return 0;
 387
 388         /* Stream output. */
 389         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 390                 if (is_ir3(screen))
 391                         return PIPE_MAX_SO_BUFFERS;
 392                 return 0;
 393         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 394         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 395                 if (is_ir3(screen))
 396                         return 1;
 397                 return 0;
 398         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 399         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 400                 if (is_ir3(screen))
 401                         return 16 * 4;   /* should only be shader out limit? */
 402                 return 0;
 403
 404         /* Geometry shader output, unsupported. */
 405         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 406         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 407         case PIPE_CAP_MAX_VERTEX_STREAMS:
 408                 return 0;
 409
 410         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 411                 return 2048;
 412
 413         /* Texturing. */
 414         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 415         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 416                 return MAX_MIP_LEVELS;
 417         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 418                 return 11;
 419
 420         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 421                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 422
 423         /* Render targets. */
 424         case PIPE_CAP_MAX_RENDER_TARGETS:
 425                 return screen->max_rts;
 426         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 427                 return is_a3xx(screen) ? 1 : 0;
 428
 429         /* Queries. */
 430         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 431                 return 0;
 432         case PIPE_CAP_OCCLUSION_QUERY:
 433                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 434         case PIPE_CAP_QUERY_TIMESTAMP:
 435         case PIPE_CAP_QUERY_TIME_ELAPSED:
 436                 /* only a4xx, requires new enough kernel so we know max_freq: */
 437                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 438
 439         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 440         case PIPE_CAP_MIN_TEXEL_OFFSET:
 441                 return -8;
 442
 443         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 444         case PIPE_CAP_MAX_TEXEL_OFFSET:
 445                 return 7;
 446
 447         case PIPE_CAP_ENDIANNESS:
 448                 return PIPE_ENDIAN_LITTLE;
 449
 450         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 451                 return 64;
 452
 453         case PIPE_CAP_VENDOR_ID:
 454                 return 0x5143;
 455         case PIPE_CAP_DEVICE_ID:
 456                 return 0xFFFFFFFF;
 457         case PIPE_CAP_ACCELERATED:
 458                 return 1;
 459         case PIPE_CAP_VIDEO_MEMORY:
 460                 DBG("FINISHME: The value returned is incorrect\n");
 461                 return 10;
 462         case PIPE_CAP_UMA:
 463                 return 1;
 464         case PIPE_CAP_NATIVE_FENCE_FD:
 465                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 466         }
 467         debug_printf("unknown param %d\n", param);
 468         return 0;
 469 }
 470
 471 static float
 472 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 473 {
 474         switch (param) {
 475         case PIPE_CAPF_MAX_LINE_WIDTH:
 476         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 477                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 478                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 479                  * uses too small of a render target size, and gets confused when
 480                  * the lines start going offscreen.
 481                  *
 482                  * See: https://code.google.com/p/android/issues/detail?id=206513
 483                  */
 484                 if (fd_mesa_debug & FD_DBG_DEQP)
 485                         return 48.0f;
 486                 return 127.0f;
 487         case PIPE_CAPF_MAX_POINT_WIDTH:
 488         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 489                 return 4092.0f;
 490         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 491                 return 16.0f;
 492         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 493                 return 15.0f;
 494         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 495         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 496         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 497                 return 0.0f;
 498         }
 499         debug_printf("unknown paramf %d\n", param);
 500         return 0;
 501 }
 502
 503 static int
 504 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 505                 enum pipe_shader_type shader,
 506                 enum pipe_shader_cap param)
 507 {
 508         struct fd_screen *screen = fd_screen(pscreen);
 509
 510         switch(shader)
 511         {
 512         case PIPE_SHADER_FRAGMENT:
 513         case PIPE_SHADER_VERTEX:
 514                 break;
 515         case PIPE_SHADER_COMPUTE:
 516                 if (has_compute(screen))
 517                         break;
 518                 return 0;
 519         case PIPE_SHADER_GEOMETRY:
 520                 /* maye we could emulate.. */
 521                 return 0;
 522         default:
 523                 DBG("unknown shader type %d", shader);
 524                 return 0;
 525         }
 526
 527         /* this is probably not totally correct.. but it's a start: */
 528         switch (param) {
 529         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 530         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 531         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 532         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 533                 return 16384;
 534         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 535                 return 8; /* XXX */
 536         case PIPE_SHADER_CAP_MAX_INPUTS:
 537         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 538                 return 16;
 539         case PIPE_SHADER_CAP_MAX_TEMPS:
 540                 return 64; /* Max native temporaries. */
 541         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 542                 /* NOTE: seems to be limit for a3xx is actually 512 but
 543                  * split between VS and FS.  Use lower limit of 256 to
 544                  * avoid getting into impossible situations:
 545                  */
 546                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 547         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 548                 return is_ir3(screen) ? 16 : 1;
 549         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 550                 return 1;
 551         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 552         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 553                 /* Technically this should be the same as for TEMP/CONST, since
 554                  * everything is just normal registers.  This is just temporary
 555                  * hack until load_input/store_output handle arrays in a similar
 556                  * way as load_var/store_var..
 557                  */
 558                 return 0;
 559         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 560         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 561                 /* a2xx compiler doesn't handle indirect: */
 562                 return is_ir3(screen) ? 1 : 0;
 563         case PIPE_SHADER_CAP_SUBROUTINES:
 564         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 565         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 566         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 567         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 568         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 569                 return 0;
 570         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 571                 return 1;
 572         case PIPE_SHADER_CAP_INTEGERS:
 573                 if (glsl120)
 574                         return 0;
 575                 return is_ir3(screen) ? 1 : 0;
 576         case PIPE_SHADER_CAP_INT64_ATOMICS:
 577                 return 0;
 578         case PIPE_SHADER_CAP_FP16:
 579                 return 0;
 580         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 581         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 582                 return 16;
 583         case PIPE_SHADER_CAP_PREFERRED_IR:
 584                 if (is_ir3(screen))
 585                         return PIPE_SHADER_IR_NIR;
 586                 return PIPE_SHADER_IR_TGSI;
 587         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 588                 if (is_ir3(screen)) {
 589                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 590                 } else {
 591                         return (1 << PIPE_SHADER_IR_TGSI);
 592                 }
 593                 return 0;
 594         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 595                 return 32;
 596         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 597         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 598         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 599         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 600         case PIPE_SHADER_CAP_SCALAR_ISA:
 601                 return 1;
 602         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 603         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 604                 if (is_a5xx(screen)) {
 605                         /* a5xx (and a4xx for that matter) has one state-block
 606                          * for compute-shader SSBO's and another that is shared
 607                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 608                          * just advertise SSBOs for FS and CS.  We could possibly
 609                          * do what blob does, and partition the space for
 610                          * VS/HS/DS/GS/FS.  The blob advertises:
 611                          *
 612                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 613                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 614                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 615                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 616                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 617                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 618                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 619                          *
 620                          * I think that way we could avoid having to patch shaders
 621                          * for actual SSBO indexes by using a static partitioning.
 622                          *
 623                          * Note same state block is used for images and buffers,
 624                          * but images also need texture state for read access
 625                          * (isam/isam.3d)
 626                          */
 627                         switch(shader)
 628                         {
 629                         case PIPE_SHADER_FRAGMENT:
 630                         case PIPE_SHADER_COMPUTE:
 631                                 return 24;
 632                         default:
 633                                 return 0;
 634                         }
 635                 }
 636                 return 0;
 637         }
 638         debug_printf("unknown shader param %d\n", param);
 639         return 0;
 640 }
 641
 642 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 643  * into per-generation backend?
 644  */
 645 static int
 646 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 647                 enum pipe_compute_cap param, void *ret)
 648 {
 649         struct fd_screen *screen = fd_screen(pscreen);
 650         const char * const ir = "ir3";
 651
 652         if (!has_compute(screen))
 653                 return 0;
 654
 655 #define RET(x) do {                  \
 656    if (ret)                          \
 657       memcpy(ret, x, sizeof(x));     \
 658    return sizeof(x);                 \
 659 } while (0)
 660
 661         switch (param) {
 662         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 663 // don't expose 64b pointer support yet, until ir3 supports 64b
 664 // math, otherwise spir64 target is used and we get 64b pointer
 665 // calculations that we can't do yet
 666 //              if (is_a5xx(screen))
 667 //                      RET((uint32_t []){ 64 });
 668                 RET((uint32_t []){ 32 });
 669
 670         case PIPE_COMPUTE_CAP_IR_TARGET:
 671                 if (ret)
 672                         sprintf(ret, ir);
 673                 return strlen(ir) * sizeof(char);
 674
 675         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 676                 RET((uint64_t []) { 3 });
 677
 678         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 679                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 680
 681         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 682                 RET(((uint64_t []) { 1024, 1024, 64 }));
 683
 684         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 685                 RET((uint64_t []) { 1024 });
 686
 687         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 688                 RET((uint64_t []) { screen->ram_size });
 689
 690         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 691                 RET((uint64_t []) { 32768 });
 692
 693         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 694         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 695                 RET((uint64_t []) { 4096 });
 696
 697         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 698                 RET((uint64_t []) { screen->ram_size });
 699
 700         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 701                 RET((uint32_t []) { screen->max_freq / 1000000 });
 702
 703         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 704                 RET((uint32_t []) { 9999 });  // TODO
 705
 706         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 707                 RET((uint32_t []) { 1 });
 708
 709         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 710                 RET((uint32_t []) { 32 });  // TODO
 711
 712         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 713                 RET((uint64_t []) { 1024 }); // TODO
 714         }
 715
 716         return 0;
 717 }
 718
 719 static const void *
 720 fd_get_compiler_options(struct pipe_screen *pscreen,
 721                 enum pipe_shader_ir ir, unsigned shader)
 722 {
 723         struct fd_screen *screen = fd_screen(pscreen);
 724
 725         if (is_ir3(screen))
 726                 return ir3_get_compiler_options(screen->compiler);
 727
 728         return NULL;
 729 }
 730
 731 boolean
 732 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 733                 struct fd_bo *bo,
 734                 unsigned stride,
 735                 struct winsys_handle *whandle)
 736 {
 737         whandle->stride = stride;
 738
 739         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 740                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 741         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 742                 whandle->handle = fd_bo_handle(bo);
 743                 return TRUE;
 744         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 745                 whandle->handle = fd_bo_dmabuf(bo);
 746                 return TRUE;
 747         } else {
 748                 return FALSE;
 749         }
 750 }
 751
 752 struct fd_bo *
 753 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 754                 struct winsys_handle *whandle)
 755 {
 756         struct fd_screen *screen = fd_screen(pscreen);
 757         struct fd_bo *bo;
 758
 759         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 760                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 761         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 762                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 763         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 764                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 765         } else {
 766                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 767                 return NULL;
 768         }
 769
 770         if (!bo) {
 771                 DBG("ref name 0x%08x failed", whandle->handle);
 772                 return NULL;
 773         }
 774
 775         return bo;
 776 }
 777
 778 struct pipe_screen *
 779 fd_screen_create(struct fd_device *dev)
 780 {
 781         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 782         struct pipe_screen *pscreen;
 783         uint64_t val;
 784
 785         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 786
 787         if (fd_mesa_debug & FD_DBG_NOBIN)
 788                 fd_binning_enabled = false;
 789
 790         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 791
 792         if (!screen)
 793                 return NULL;
 794
 795         pscreen = &screen->base;
 796
 797         screen->dev = dev;
 798         screen->refcnt = 1;
 799
 800         // maybe this should be in context?
 801         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 802         if (!screen->pipe) {
 803                 DBG("could not create 3d pipe");
 804                 goto fail;
 805         }
 806
 807         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 808                 DBG("could not get GMEM size");
 809                 goto fail;
 810         }
 811         screen->gmemsize_bytes = val;
 812
 813         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 814                 DBG("could not get device-id");
 815                 goto fail;
 816         }
 817         screen->device_id = val;
 818
 819         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 820                 DBG("could not get gpu freq");
 821                 /* this limits what performance related queries are
 822                  * supported but is not fatal
 823                  */
 824                 screen->max_freq = 0;
 825         } else {
 826                 screen->max_freq = val;
 827                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 828                         screen->has_timestamp = true;
 829         }
 830
 831         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 832                 DBG("could not get gpu-id");
 833                 goto fail;
 834         }
 835         screen->gpu_id = val;
 836
 837         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 838                 DBG("could not get chip-id");
 839                 /* older kernels may not have this property: */
 840                 unsigned core  = screen->gpu_id / 100;
 841                 unsigned major = (screen->gpu_id % 100) / 10;
 842                 unsigned minor = screen->gpu_id % 10;
 843                 unsigned patch = 0;  /* assume the worst */
 844                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 845                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 846         }
 847         screen->chip_id = val;
 848
 849         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 850                 DBG("could not get # of rings");
 851                 screen->priority_mask = 0;
 852         } else {
 853                 /* # of rings equates to number of unique priority values: */
 854                 screen->priority_mask = (1 << val) - 1;
 855         }
 856
 857         struct sysinfo si;
 858         sysinfo(&si);
 859         screen->ram_size = si.totalram;
 860
 861         DBG("Pipe Info:");
 862         DBG(" GPU-id:          %d", screen->gpu_id);
 863         DBG(" Chip-id:         0x%08x", screen->chip_id);
 864         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 865
 866         /* explicitly checking for GPU revisions that are known to work.  This
 867          * may be overly conservative for a3xx, where spoofing the gpu_id with
 868          * the blob driver seems to generate identical cmdstream dumps.  But
 869          * on a2xx, there seem to be small differences between the GPU revs
 870          * so it is probably better to actually test first on real hardware
 871          * before enabling:
 872          *
 873          * If you have a different adreno version, feel free to add it to one
 874          * of the cases below and see what happens.  And if it works, please
 875          * send a patch ;-)
 876          */
 877         switch (screen->gpu_id) {
 878         case 220:
 879                 fd2_screen_init(pscreen);
 880                 break;
 881         case 305:
 882         case 307:
 883         case 320:
 884         case 330:
 885                 fd3_screen_init(pscreen);
 886                 break;
 887         case 420:
 888         case 430:
 889                 fd4_screen_init(pscreen);
 890                 break;
 891         case 530:
 892                 fd5_screen_init(pscreen);
 893                 break;
 894         default:
 895                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 896                 goto fail;
 897         }
 898
 899         if (screen->gpu_id >= 500) {
 900                 screen->gmem_alignw = 64;
 901                 screen->gmem_alignh = 32;
 902                 screen->num_vsc_pipes = 16;
 903         } else {
 904                 screen->gmem_alignw = 32;
 905                 screen->gmem_alignh = 32;
 906                 screen->num_vsc_pipes = 8;
 907         }
 908
 909         /* NOTE: don't enable reordering on a2xx, since completely untested.
 910          * Also, don't enable if we have too old of a kernel to support
 911          * growable cmdstream buffers, since memory requirement for cmdstream
 912          * buffers would be too much otherwise.
 913          */
 914         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 915                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 916
 917         fd_bc_init(&screen->batch_cache);
 918
 919         (void) mtx_init(&screen->lock, mtx_plain);
 920
 921         pscreen->destroy = fd_screen_destroy;
 922         pscreen->get_param = fd_screen_get_param;
 923         pscreen->get_paramf = fd_screen_get_paramf;
 924         pscreen->get_shader_param = fd_screen_get_shader_param;
 925         pscreen->get_compute_param = fd_get_compute_param;
 926         pscreen->get_compiler_options = fd_get_compiler_options;
 927
 928         fd_resource_screen_init(pscreen);
 929         fd_query_screen_init(pscreen);
 930
 931         pscreen->get_name = fd_screen_get_name;
 932         pscreen->get_vendor = fd_screen_get_vendor;
 933         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 934
 935         pscreen->get_timestamp = fd_screen_get_timestamp;
 936
 937         pscreen->fence_reference = fd_fence_ref;
 938         pscreen->fence_finish = fd_fence_finish;
 939         pscreen->fence_get_fd = fd_fence_get_fd;
 940
 941         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 942
 943         return pscreen;
 944
 945 fail:
 946         fd_screen_destroy(pscreen);
 947         return NULL;
 948 }