2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
42 #include "drm-uapi/drm_fourcc.h"
46 #include <sys/sysinfo.h>
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
61 #include "ir3/ir3_nir.h"
64 /* XXX this should go away */
65 #include "state_tracker/drm_driver.h"
67 static const struct debug_named_value debug_options
[] = {
68 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
75 {"fraghalf", FD_DBG_FRAGHALF
, "Use half-precision in fragment shader"},
76 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
77 {"glsl120", FD_DBG_GLSL120
,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
78 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
79 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
80 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
81 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
82 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
83 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
84 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx+)"},
85 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
86 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
87 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
88 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a5xx)"},
89 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
90 {"noubwc", FD_DBG_NOUBWC
, "Disable UBWC for all internal buffers"},
94 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
96 int fd_mesa_debug
= 0;
97 bool fd_binning_enabled
= true;
98 static bool glsl120
= false;
101 fd_screen_get_name(struct pipe_screen
*pscreen
)
103 static char buffer
[128];
104 snprintf(buffer
, sizeof(buffer
), "FD%03d",
105 fd_screen(pscreen
)->device_id
);
110 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
116 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
123 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
125 struct fd_screen
*screen
= fd_screen(pscreen
);
127 if (screen
->has_timestamp
) {
129 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
130 debug_assert(screen
->max_freq
> 0);
131 return n
* 1000000000 / screen
->max_freq
;
133 int64_t cpu_time
= os_time_get() * 1000;
134 return cpu_time
+ screen
->cpu_gpu_time_delta
;
140 fd_screen_destroy(struct pipe_screen
*pscreen
)
142 struct fd_screen
*screen
= fd_screen(pscreen
);
145 fd_pipe_del(screen
->pipe
);
148 fd_device_del(screen
->dev
);
153 fd_bc_fini(&screen
->batch_cache
);
155 slab_destroy_parent(&screen
->transfer_pool
);
157 mtx_destroy(&screen
->lock
);
159 ralloc_free(screen
->compiler
);
161 free(screen
->perfcntr_queries
);
166 TODO either move caps to a2xx/a3xx specific code, or maybe have some
167 tables for things that differ if the delta is not too much..
170 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
172 struct fd_screen
*screen
= fd_screen(pscreen
);
174 /* this is probably not totally correct.. but it's a start: */
176 /* Supported features (boolean caps). */
177 case PIPE_CAP_NPOT_TEXTURES
:
178 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
179 case PIPE_CAP_ANISOTROPIC_FILTER
:
180 case PIPE_CAP_POINT_SPRITE
:
181 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
182 case PIPE_CAP_TEXTURE_SWIZZLE
:
183 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
184 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
185 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
186 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
187 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
188 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
189 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
190 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
191 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
192 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
193 case PIPE_CAP_STRING_MARKER
:
194 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
195 case PIPE_CAP_TEXTURE_BARRIER
:
196 case PIPE_CAP_INVALIDATE_BUFFER
:
199 case PIPE_CAP_PACKED_UNIFORMS
:
200 return !is_a2xx(screen
);
202 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
203 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
204 return screen
->has_robustness
;
206 case PIPE_CAP_VERTEXID_NOBASE
:
207 return is_a3xx(screen
) || is_a4xx(screen
);
209 case PIPE_CAP_COMPUTE
:
210 return has_compute(screen
);
212 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
213 case PIPE_CAP_PCI_GROUP
:
214 case PIPE_CAP_PCI_BUS
:
215 case PIPE_CAP_PCI_DEVICE
:
216 case PIPE_CAP_PCI_FUNCTION
:
217 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
220 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
221 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
222 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
223 case PIPE_CAP_PRIMITIVE_RESTART
:
224 case PIPE_CAP_TGSI_INSTANCEID
:
225 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
226 case PIPE_CAP_INDEP_BLEND_ENABLE
:
227 case PIPE_CAP_INDEP_BLEND_FUNC
:
228 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
229 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
230 case PIPE_CAP_CONDITIONAL_RENDER
:
231 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
233 case PIPE_CAP_CLIP_HALFZ
:
234 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
236 case PIPE_CAP_FAKE_SW_MSAA
:
237 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
239 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
240 return is_a5xx(screen
) || is_a6xx(screen
);
242 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
243 return is_a6xx(screen
);
245 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
246 return is_a3xx(screen
) || is_a4xx(screen
);
248 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
249 return is_a5xx(screen
) || is_a6xx(screen
);
251 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
252 if (is_a3xx(screen
)) return 16;
253 if (is_a4xx(screen
)) return 32;
254 if (is_a5xx(screen
)) return 32;
255 if (is_a6xx(screen
)) return 64;
257 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
258 /* We could possibly emulate more by pretending 2d/rect textures and
259 * splitting high bits of index into 2nd dimension..
261 if (is_a3xx(screen
)) return 8192;
262 if (is_a4xx(screen
)) return 16384;
263 if (is_a5xx(screen
)) return 16384;
264 if (is_a6xx(screen
)) return 1 << 27;
267 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
268 case PIPE_CAP_CUBE_MAP_ARRAY
:
269 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
270 case PIPE_CAP_TEXTURE_QUERY_LOD
:
271 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
273 case PIPE_CAP_START_INSTANCE
:
274 /* Note that a5xx can do this, it just can't (at least with
275 * current firmware) do draw_indirect with base_instance.
276 * Since draw_indirect is needed sooner (gles31 and gl40 vs
277 * gl42), hide base_instance on a5xx. :-/
279 return is_a4xx(screen
);
281 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
284 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
285 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
288 return is_ir3(screen
) ? 140 : 120;
290 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
291 /* we can probably enable 320 for a5xx too, but need to test: */
292 if (is_a6xx(screen
)) return 320;
293 if (is_a5xx(screen
)) return 310;
294 if (is_ir3(screen
)) return 300;
297 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
298 if (is_a6xx(screen
)) return 64;
299 if (is_a5xx(screen
)) return 4;
302 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
303 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
307 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
308 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
311 case PIPE_CAP_FBFETCH
:
312 if (fd_device_version(screen
->dev
) >= FD_VERSION_GMEM_BASE
&&
316 case PIPE_CAP_SAMPLE_SHADING
:
317 if (is_a6xx(screen
)) return 1;
320 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
323 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
324 return screen
->priority_mask
;
326 case PIPE_CAP_DRAW_INDIRECT
:
327 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
331 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
332 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
336 case PIPE_CAP_LOAD_CONSTBUF
:
337 /* name is confusing, but this turns on std430 packing */
342 case PIPE_CAP_MAX_VIEWPORTS
:
345 case PIPE_CAP_MAX_VARYINGS
:
348 case PIPE_CAP_SHAREABLE_SHADERS
:
349 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
350 /* manage the variants for these ourself, to avoid breaking precompile: */
351 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
352 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
358 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
360 return PIPE_MAX_SO_BUFFERS
;
362 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
363 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
364 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
368 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
369 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
371 return 16 * 4; /* should only be shader out limit? */
375 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
376 return 1 << (MAX_MIP_LEVELS
- 1);
377 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
378 return MAX_MIP_LEVELS
;
379 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
382 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
383 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
385 /* Render targets. */
386 case PIPE_CAP_MAX_RENDER_TARGETS
:
387 return screen
->max_rts
;
388 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
389 return is_a3xx(screen
) ? 1 : 0;
392 case PIPE_CAP_OCCLUSION_QUERY
:
393 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
394 case PIPE_CAP_QUERY_TIMESTAMP
:
395 case PIPE_CAP_QUERY_TIME_ELAPSED
:
396 /* only a4xx, requires new enough kernel so we know max_freq: */
397 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
399 case PIPE_CAP_VENDOR_ID
:
401 case PIPE_CAP_DEVICE_ID
:
403 case PIPE_CAP_ACCELERATED
:
405 case PIPE_CAP_VIDEO_MEMORY
:
406 DBG("FINISHME: The value returned is incorrect\n");
410 case PIPE_CAP_NATIVE_FENCE_FD
:
411 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
413 return u_pipe_screen_get_param_defaults(pscreen
, param
);
418 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
421 case PIPE_CAPF_MAX_LINE_WIDTH
:
422 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
423 /* NOTE: actual value is 127.0f, but this is working around a deqp
424 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
425 * uses too small of a render target size, and gets confused when
426 * the lines start going offscreen.
428 * See: https://code.google.com/p/android/issues/detail?id=206513
430 if (fd_mesa_debug
& FD_DBG_DEQP
)
433 case PIPE_CAPF_MAX_POINT_WIDTH
:
434 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
436 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
438 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
440 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
441 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
442 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
445 debug_printf("unknown paramf %d\n", param
);
450 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
451 enum pipe_shader_type shader
,
452 enum pipe_shader_cap param
)
454 struct fd_screen
*screen
= fd_screen(pscreen
);
458 case PIPE_SHADER_FRAGMENT
:
459 case PIPE_SHADER_VERTEX
:
461 case PIPE_SHADER_COMPUTE
:
462 if (has_compute(screen
))
465 case PIPE_SHADER_GEOMETRY
:
466 /* maye we could emulate.. */
469 DBG("unknown shader type %d", shader
);
473 /* this is probably not totally correct.. but it's a start: */
475 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
476 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
477 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
478 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
480 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
482 case PIPE_SHADER_CAP_MAX_INPUTS
:
483 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
485 case PIPE_SHADER_CAP_MAX_TEMPS
:
486 return 64; /* Max native temporaries. */
487 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
488 /* NOTE: seems to be limit for a3xx is actually 512 but
489 * split between VS and FS. Use lower limit of 256 to
490 * avoid getting into impossible situations:
492 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
493 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
494 return is_ir3(screen
) ? 16 : 1;
495 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
497 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
498 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
499 /* Technically this should be the same as for TEMP/CONST, since
500 * everything is just normal registers. This is just temporary
501 * hack until load_input/store_output handle arrays in a similar
502 * way as load_var/store_var..
505 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
506 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
507 /* a2xx compiler doesn't handle indirect: */
508 return is_ir3(screen
) ? 1 : 0;
509 case PIPE_SHADER_CAP_SUBROUTINES
:
510 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
511 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
512 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
513 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
514 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
515 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
516 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
517 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
518 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
520 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
522 case PIPE_SHADER_CAP_INTEGERS
:
525 return is_ir3(screen
) ? 1 : 0;
526 case PIPE_SHADER_CAP_INT64_ATOMICS
:
528 case PIPE_SHADER_CAP_FP16
:
530 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
531 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
533 case PIPE_SHADER_CAP_PREFERRED_IR
:
534 return PIPE_SHADER_IR_NIR
;
535 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
536 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
537 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
539 case PIPE_SHADER_CAP_SCALAR_ISA
:
540 return is_ir3(screen
) ? 1 : 0;
541 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
542 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
543 if (is_a5xx(screen
) || is_a6xx(screen
)) {
544 /* a5xx (and a4xx for that matter) has one state-block
545 * for compute-shader SSBO's and another that is shared
546 * by VS/HS/DS/GS/FS.. so to simplify things for now
547 * just advertise SSBOs for FS and CS. We could possibly
548 * do what blob does, and partition the space for
549 * VS/HS/DS/GS/FS. The blob advertises:
551 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
552 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
553 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
554 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
555 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
556 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
557 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
559 * I think that way we could avoid having to patch shaders
560 * for actual SSBO indexes by using a static partitioning.
562 * Note same state block is used for images and buffers,
563 * but images also need texture state for read access
568 case PIPE_SHADER_FRAGMENT
:
569 case PIPE_SHADER_COMPUTE
:
577 debug_printf("unknown shader param %d\n", param
);
581 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
582 * into per-generation backend?
585 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
586 enum pipe_compute_cap param
, void *ret
)
588 struct fd_screen
*screen
= fd_screen(pscreen
);
589 const char * const ir
= "ir3";
591 if (!has_compute(screen
))
594 #define RET(x) do { \
596 memcpy(ret, x, sizeof(x)); \
601 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
602 // don't expose 64b pointer support yet, until ir3 supports 64b
603 // math, otherwise spir64 target is used and we get 64b pointer
604 // calculations that we can't do yet
605 // if (is_a5xx(screen))
606 // RET((uint32_t []){ 64 });
607 RET((uint32_t []){ 32 });
609 case PIPE_COMPUTE_CAP_IR_TARGET
:
611 sprintf(ret
, "%s", ir
);
612 return strlen(ir
) * sizeof(char);
614 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
615 RET((uint64_t []) { 3 });
617 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
618 RET(((uint64_t []) { 65535, 65535, 65535 }));
620 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
621 RET(((uint64_t []) { 1024, 1024, 64 }));
623 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
624 RET((uint64_t []) { 1024 });
626 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
627 RET((uint64_t []) { screen
->ram_size
});
629 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
630 RET((uint64_t []) { 32768 });
632 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
633 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
634 RET((uint64_t []) { 4096 });
636 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
637 RET((uint64_t []) { screen
->ram_size
});
639 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
640 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
642 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
643 RET((uint32_t []) { 9999 }); // TODO
645 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
646 RET((uint32_t []) { 1 });
648 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
649 RET((uint32_t []) { 32 }); // TODO
651 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
652 RET((uint64_t []) { 1024 }); // TODO
659 fd_get_compiler_options(struct pipe_screen
*pscreen
,
660 enum pipe_shader_ir ir
, unsigned shader
)
662 struct fd_screen
*screen
= fd_screen(pscreen
);
665 return ir3_get_compiler_options(screen
->compiler
);
667 return ir2_get_compiler_options();
671 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
673 struct renderonly_scanout
*scanout
,
675 struct winsys_handle
*whandle
)
677 whandle
->stride
= stride
;
679 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
680 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
681 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
682 if (renderonly_get_handle(scanout
, whandle
))
684 whandle
->handle
= fd_bo_handle(bo
);
686 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
687 whandle
->handle
= fd_bo_dmabuf(bo
);
695 fd_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
696 enum pipe_format format
,
697 int max
, uint64_t *modifiers
,
698 unsigned int *external_only
,
701 struct fd_screen
*screen
= fd_screen(pscreen
);
704 max
= MIN2(max
, screen
->num_supported_modifiers
);
707 max
= screen
->num_supported_modifiers
;
708 external_only
= NULL
;
712 for (i
= 0; i
< max
; i
++) {
714 modifiers
[num
] = screen
->supported_modifiers
[i
];
717 external_only
[num
] = 0;
726 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
727 struct winsys_handle
*whandle
)
729 struct fd_screen
*screen
= fd_screen(pscreen
);
732 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
733 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
734 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
735 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
736 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
737 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
739 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
744 DBG("ref name 0x%08x failed", whandle
->handle
);
752 fd_screen_create(struct fd_device
*dev
, struct renderonly
*ro
)
754 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
755 struct pipe_screen
*pscreen
;
758 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
760 if (fd_mesa_debug
& FD_DBG_NOBIN
)
761 fd_binning_enabled
= false;
763 glsl120
= !!(fd_mesa_debug
& FD_DBG_GLSL120
);
768 pscreen
= &screen
->base
;
774 screen
->ro
= renderonly_dup(ro
);
776 DBG("could not create renderonly object");
781 // maybe this should be in context?
782 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
784 DBG("could not create 3d pipe");
788 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
789 DBG("could not get GMEM size");
792 screen
->gmemsize_bytes
= val
;
794 if (fd_device_version(dev
) >= FD_VERSION_GMEM_BASE
) {
795 fd_pipe_get_param(screen
->pipe
, FD_GMEM_BASE
, &screen
->gmem_base
);
798 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
799 DBG("could not get device-id");
802 screen
->device_id
= val
;
804 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
805 DBG("could not get gpu freq");
806 /* this limits what performance related queries are
807 * supported but is not fatal
809 screen
->max_freq
= 0;
811 screen
->max_freq
= val
;
812 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
813 screen
->has_timestamp
= true;
816 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
817 DBG("could not get gpu-id");
820 screen
->gpu_id
= val
;
822 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
823 DBG("could not get chip-id");
824 /* older kernels may not have this property: */
825 unsigned core
= screen
->gpu_id
/ 100;
826 unsigned major
= (screen
->gpu_id
% 100) / 10;
827 unsigned minor
= screen
->gpu_id
% 10;
828 unsigned patch
= 0; /* assume the worst */
829 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
830 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
832 screen
->chip_id
= val
;
834 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
835 DBG("could not get # of rings");
836 screen
->priority_mask
= 0;
838 /* # of rings equates to number of unique priority values: */
839 screen
->priority_mask
= (1 << val
) - 1;
842 if ((fd_device_version(dev
) >= FD_VERSION_ROBUSTNESS
) &&
843 (fd_pipe_get_param(screen
->pipe
, FD_PP_PGTABLE
, &val
) == 0)) {
844 screen
->has_robustness
= val
;
849 screen
->ram_size
= si
.totalram
;
852 DBG(" GPU-id: %d", screen
->gpu_id
);
853 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
854 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
856 /* explicitly checking for GPU revisions that are known to work. This
857 * may be overly conservative for a3xx, where spoofing the gpu_id with
858 * the blob driver seems to generate identical cmdstream dumps. But
859 * on a2xx, there seem to be small differences between the GPU revs
860 * so it is probably better to actually test first on real hardware
863 * If you have a different adreno version, feel free to add it to one
864 * of the cases below and see what happens. And if it works, please
867 switch (screen
->gpu_id
) {
872 fd2_screen_init(pscreen
);
878 fd3_screen_init(pscreen
);
882 fd4_screen_init(pscreen
);
886 fd5_screen_init(pscreen
);
889 fd6_screen_init(pscreen
);
892 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
896 if (screen
->gpu_id
>= 600) {
897 screen
->gmem_alignw
= 32;
898 screen
->gmem_alignh
= 32;
899 screen
->num_vsc_pipes
= 32;
900 } else if (screen
->gpu_id
>= 500) {
901 screen
->gmem_alignw
= 64;
902 screen
->gmem_alignh
= 32;
903 screen
->num_vsc_pipes
= 16;
905 screen
->gmem_alignw
= 32;
906 screen
->gmem_alignh
= 32;
907 screen
->num_vsc_pipes
= 8;
910 /* NOTE: don't enable if we have too old of a kernel to support
911 * growable cmdstream buffers, since memory requirement for cmdstream
912 * buffers would be too much otherwise.
914 if (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
)
915 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
917 fd_bc_init(&screen
->batch_cache
);
919 (void) mtx_init(&screen
->lock
, mtx_plain
);
921 pscreen
->destroy
= fd_screen_destroy
;
922 pscreen
->get_param
= fd_screen_get_param
;
923 pscreen
->get_paramf
= fd_screen_get_paramf
;
924 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
925 pscreen
->get_compute_param
= fd_get_compute_param
;
926 pscreen
->get_compiler_options
= fd_get_compiler_options
;
928 fd_resource_screen_init(pscreen
);
929 fd_query_screen_init(pscreen
);
931 pscreen
->get_name
= fd_screen_get_name
;
932 pscreen
->get_vendor
= fd_screen_get_vendor
;
933 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
935 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
937 pscreen
->fence_reference
= fd_fence_ref
;
938 pscreen
->fence_finish
= fd_fence_finish
;
939 pscreen
->fence_get_fd
= fd_fence_get_fd
;
941 pscreen
->query_dmabuf_modifiers
= fd_screen_query_dmabuf_modifiers
;
943 if (!screen
->supported_modifiers
) {
944 static const uint64_t supported_modifiers
[] = {
945 DRM_FORMAT_MOD_LINEAR
,
948 screen
->supported_modifiers
= supported_modifiers
;
949 screen
->num_supported_modifiers
= ARRAY_SIZE(supported_modifiers
);
952 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
957 fd_screen_destroy(pscreen
);