src/gallium/drivers/freedreno/freedreno_screen.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35 #include "util/u_format_s3tc.h"
  36 #include "util/u_screen.h"
  37 #include "util/u_string.h"
  38 #include "util/u_debug.h"
  39
  40 #include "util/os_time.h"
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60
  61 #include "ir3/ir3_nir.h"
  62 #include "a2xx/ir2.h"
  63
  64 /* XXX this should go away */
  65 #include "state_tracker/drm_driver.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  78                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  79                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  80                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  81                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  82                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  83                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  84                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  85                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  86                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  87                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  88                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  89                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  90                 {"softpin",   FD_DBG_SOFTPIN,"Enable softpin command submission (experimental)"},
  91                 {"ubwc",      FD_DBG_UBWC,   "Enable UBWC for all internal buffers (experimental)"},
  92                 DEBUG_NAMED_VALUE_END
  93 };
  94
  95 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  96
  97 int fd_mesa_debug = 0;
  98 bool fd_binning_enabled = true;
  99 static bool glsl120 = false;
 100
 101 static const char *
 102 fd_screen_get_name(struct pipe_screen *pscreen)
 103 {
 104         static char buffer[128];
 105         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 106                         fd_screen(pscreen)->device_id);
 107         return buffer;
 108 }
 109
 110 static const char *
 111 fd_screen_get_vendor(struct pipe_screen *pscreen)
 112 {
 113         return "freedreno";
 114 }
 115
 116 static const char *
 117 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 118 {
 119         return "Qualcomm";
 120 }
 121
 122
 123 static uint64_t
 124 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 125 {
 126         struct fd_screen *screen = fd_screen(pscreen);
 127
 128         if (screen->has_timestamp) {
 129                 uint64_t n;
 130                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 131                 debug_assert(screen->max_freq > 0);
 132                 return n * 1000000000 / screen->max_freq;
 133         } else {
 134                 int64_t cpu_time = os_time_get() * 1000;
 135                 return cpu_time + screen->cpu_gpu_time_delta;
 136         }
 137
 138 }
 139
 140 static void
 141 fd_screen_destroy(struct pipe_screen *pscreen)
 142 {
 143         struct fd_screen *screen = fd_screen(pscreen);
 144
 145         if (screen->pipe)
 146                 fd_pipe_del(screen->pipe);
 147
 148         if (screen->dev)
 149                 fd_device_del(screen->dev);
 150
 151         if (screen->ro)
 152                 FREE(screen->ro);
 153
 154         fd_bc_fini(&screen->batch_cache);
 155
 156         slab_destroy_parent(&screen->transfer_pool);
 157
 158         mtx_destroy(&screen->lock);
 159
 160         ralloc_free(screen->compiler);
 161
 162         free(screen->perfcntr_queries);
 163         free(screen);
 164 }
 165
 166 /*
 167 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 168 tables for things that differ if the delta is not too much..
 169  */
 170 static int
 171 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 172 {
 173         struct fd_screen *screen = fd_screen(pscreen);
 174
 175         /* this is probably not totally correct.. but it's a start: */
 176         switch (param) {
 177         /* Supported features (boolean caps). */
 178         case PIPE_CAP_NPOT_TEXTURES:
 179         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 180         case PIPE_CAP_ANISOTROPIC_FILTER:
 181         case PIPE_CAP_POINT_SPRITE:
 182         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183         case PIPE_CAP_TEXTURE_SWIZZLE:
 184         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 185         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 186         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 187         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 188         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 190         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 191         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 192         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 193         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 194         case PIPE_CAP_STRING_MARKER:
 195         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 196         case PIPE_CAP_TEXTURE_BARRIER:
 197         case PIPE_CAP_INVALIDATE_BUFFER:
 198         case PIPE_CAP_PACKED_UNIFORMS:
 199                 return 1;
 200
 201         case PIPE_CAP_VERTEXID_NOBASE:
 202                 return is_a3xx(screen) || is_a4xx(screen);
 203
 204         case PIPE_CAP_COMPUTE:
 205                 return has_compute(screen);
 206
 207         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 208         case PIPE_CAP_PCI_GROUP:
 209         case PIPE_CAP_PCI_BUS:
 210         case PIPE_CAP_PCI_DEVICE:
 211         case PIPE_CAP_PCI_FUNCTION:
 212         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 213                 return 0;
 214
 215         case PIPE_CAP_SM3:
 216         case PIPE_CAP_PRIMITIVE_RESTART:
 217         case PIPE_CAP_TGSI_INSTANCEID:
 218         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 219         case PIPE_CAP_INDEP_BLEND_ENABLE:
 220         case PIPE_CAP_INDEP_BLEND_FUNC:
 221         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 222         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 223         case PIPE_CAP_CONDITIONAL_RENDER:
 224         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 225         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 226         case PIPE_CAP_CLIP_HALFZ:
 227                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 228
 229         case PIPE_CAP_FAKE_SW_MSAA:
 230                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 231
 232         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 233                 return is_a5xx(screen) || is_a6xx(screen);
 234
 235         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 236                 return is_a6xx(screen);
 237
 238         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 239                 return is_a3xx(screen) || is_a4xx(screen);
 240
 241         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 242                 return is_a5xx(screen) || is_a6xx(screen);
 243
 244         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 245                 if (is_a3xx(screen)) return 16;
 246                 if (is_a4xx(screen)) return 32;
 247                 if (is_a5xx(screen)) return 32;
 248                 if (is_a6xx(screen)) return 64;
 249                 return 0;
 250         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 251                 /* We could possibly emulate more by pretending 2d/rect textures and
 252                  * splitting high bits of index into 2nd dimension..
 253                  */
 254                 if (is_a3xx(screen)) return 8192;
 255                 if (is_a4xx(screen)) return 16384;
 256                 if (is_a5xx(screen)) return 16384;
 257                 if (is_a6xx(screen)) return 1 << 27;
 258                 return 0;
 259
 260         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 261         case PIPE_CAP_CUBE_MAP_ARRAY:
 262         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 263         case PIPE_CAP_TEXTURE_QUERY_LOD:
 264                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 265
 266         case PIPE_CAP_START_INSTANCE:
 267                 /* Note that a5xx can do this, it just can't (at least with
 268                  * current firmware) do draw_indirect with base_instance.
 269                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 270                  * gl42), hide base_instance on a5xx.  :-/
 271                  */
 272                 return is_a4xx(screen);
 273
 274         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 275                 return 64;
 276
 277         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 278         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 279                 if (glsl120)
 280                         return 120;
 281                 return is_ir3(screen) ? 140 : 120;
 282
 283         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 284                 /* we can probably enable 320 for a5xx too, but need to test: */
 285                 if (is_a6xx(screen)) return 320;
 286                 if (is_a5xx(screen)) return 310;
 287                 if (is_ir3(screen))  return 300;
 288                 return 120;
 289
 290         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 291                 if (is_a6xx(screen)) return 64;
 292                 if (is_a5xx(screen)) return 4;
 293                 return 0;
 294
 295         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 296                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 297                         return 4;
 298                 return 0;
 299
 300         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 301         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 302                 return 0;
 303
 304         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 305                 return 0;
 306
 307         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 308                 return screen->priority_mask;
 309
 310         case PIPE_CAP_DRAW_INDIRECT:
 311                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 312                         return 1;
 313                 return 0;
 314
 315         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 316                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 317                         return 1;
 318                 return 0;
 319
 320         case PIPE_CAP_LOAD_CONSTBUF:
 321                 /* name is confusing, but this turns on std430 packing */
 322                 if (is_ir3(screen))
 323                         return 1;
 324                 return 0;
 325
 326         case PIPE_CAP_MAX_VIEWPORTS:
 327                 return 1;
 328
 329         case PIPE_CAP_MAX_VARYINGS:
 330                 return 16;
 331
 332         case PIPE_CAP_SHAREABLE_SHADERS:
 333         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 334         /* manage the variants for these ourself, to avoid breaking precompile: */
 335         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 336         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 337                 if (is_ir3(screen))
 338                         return 1;
 339                 return 0;
 340
 341         /* Stream output. */
 342         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 343                 if (is_ir3(screen))
 344                         return PIPE_MAX_SO_BUFFERS;
 345                 return 0;
 346         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 347         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 348                 if (is_ir3(screen))
 349                         return 1;
 350                 return 0;
 351         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 352         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 353                 if (is_ir3(screen))
 354                         return 16 * 4;   /* should only be shader out limit? */
 355                 return 0;
 356
 357         /* Texturing. */
 358         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 359         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 360                 return MAX_MIP_LEVELS;
 361         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 362                 return 11;
 363
 364         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 365                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 366
 367         /* Render targets. */
 368         case PIPE_CAP_MAX_RENDER_TARGETS:
 369                 return screen->max_rts;
 370         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 371                 return is_a3xx(screen) ? 1 : 0;
 372
 373         /* Queries. */
 374         case PIPE_CAP_OCCLUSION_QUERY:
 375                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 376         case PIPE_CAP_QUERY_TIMESTAMP:
 377         case PIPE_CAP_QUERY_TIME_ELAPSED:
 378                 /* only a4xx, requires new enough kernel so we know max_freq: */
 379                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 380
 381         case PIPE_CAP_VENDOR_ID:
 382                 return 0x5143;
 383         case PIPE_CAP_DEVICE_ID:
 384                 return 0xFFFFFFFF;
 385         case PIPE_CAP_ACCELERATED:
 386                 return 1;
 387         case PIPE_CAP_VIDEO_MEMORY:
 388                 DBG("FINISHME: The value returned is incorrect\n");
 389                 return 10;
 390         case PIPE_CAP_UMA:
 391                 return 1;
 392         case PIPE_CAP_NATIVE_FENCE_FD:
 393                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 394         default:
 395                 return u_pipe_screen_get_param_defaults(pscreen, param);
 396         }
 397 }
 398
 399 static float
 400 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 401 {
 402         switch (param) {
 403         case PIPE_CAPF_MAX_LINE_WIDTH:
 404         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 405                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 406                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 407                  * uses too small of a render target size, and gets confused when
 408                  * the lines start going offscreen.
 409                  *
 410                  * See: https://code.google.com/p/android/issues/detail?id=206513
 411                  */
 412                 if (fd_mesa_debug & FD_DBG_DEQP)
 413                         return 48.0f;
 414                 return 127.0f;
 415         case PIPE_CAPF_MAX_POINT_WIDTH:
 416         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 417                 return 4092.0f;
 418         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 419                 return 16.0f;
 420         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 421                 return 15.0f;
 422         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 423         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 424         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 425                 return 0.0f;
 426         }
 427         debug_printf("unknown paramf %d\n", param);
 428         return 0;
 429 }
 430
 431 static int
 432 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 433                 enum pipe_shader_type shader,
 434                 enum pipe_shader_cap param)
 435 {
 436         struct fd_screen *screen = fd_screen(pscreen);
 437
 438         switch(shader)
 439         {
 440         case PIPE_SHADER_FRAGMENT:
 441         case PIPE_SHADER_VERTEX:
 442                 break;
 443         case PIPE_SHADER_COMPUTE:
 444                 if (has_compute(screen))
 445                         break;
 446                 return 0;
 447         case PIPE_SHADER_GEOMETRY:
 448                 /* maye we could emulate.. */
 449                 return 0;
 450         default:
 451                 DBG("unknown shader type %d", shader);
 452                 return 0;
 453         }
 454
 455         /* this is probably not totally correct.. but it's a start: */
 456         switch (param) {
 457         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 458         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 459         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 460         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 461                 return 16384;
 462         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 463                 return 8; /* XXX */
 464         case PIPE_SHADER_CAP_MAX_INPUTS:
 465         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 466                 return 16;
 467         case PIPE_SHADER_CAP_MAX_TEMPS:
 468                 return 64; /* Max native temporaries. */
 469         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 470                 /* NOTE: seems to be limit for a3xx is actually 512 but
 471                  * split between VS and FS.  Use lower limit of 256 to
 472                  * avoid getting into impossible situations:
 473                  */
 474                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 475         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 476                 return is_ir3(screen) ? 16 : 1;
 477         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 478                 return 1;
 479         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 480         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 481                 /* Technically this should be the same as for TEMP/CONST, since
 482                  * everything is just normal registers.  This is just temporary
 483                  * hack until load_input/store_output handle arrays in a similar
 484                  * way as load_var/store_var..
 485                  */
 486                 return 0;
 487         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 488         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 489                 /* a2xx compiler doesn't handle indirect: */
 490                 return is_ir3(screen) ? 1 : 0;
 491         case PIPE_SHADER_CAP_SUBROUTINES:
 492         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 493         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 494         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 495         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 496         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 497         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 498         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 499         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 500         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 501                 return 0;
 502         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 503                 return 1;
 504         case PIPE_SHADER_CAP_INTEGERS:
 505                 if (glsl120)
 506                         return 0;
 507                 return is_ir3(screen) ? 1 : 0;
 508         case PIPE_SHADER_CAP_INT64_ATOMICS:
 509                 return 0;
 510         case PIPE_SHADER_CAP_FP16:
 511                 return 0;
 512         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 513         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 514                 return 16;
 515         case PIPE_SHADER_CAP_PREFERRED_IR:
 516                 return PIPE_SHADER_IR_NIR;
 517         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 518                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 519         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 520                 return 32;
 521         case PIPE_SHADER_CAP_SCALAR_ISA:
 522                 return is_ir3(screen) ? 1 : 0;
 523         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 524         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 525                 if (is_a5xx(screen) || is_a6xx(screen)) {
 526                         /* a5xx (and a4xx for that matter) has one state-block
 527                          * for compute-shader SSBO's and another that is shared
 528                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 529                          * just advertise SSBOs for FS and CS.  We could possibly
 530                          * do what blob does, and partition the space for
 531                          * VS/HS/DS/GS/FS.  The blob advertises:
 532                          *
 533                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 534                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 535                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 536                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 537                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 538                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 539                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 540                          *
 541                          * I think that way we could avoid having to patch shaders
 542                          * for actual SSBO indexes by using a static partitioning.
 543                          *
 544                          * Note same state block is used for images and buffers,
 545                          * but images also need texture state for read access
 546                          * (isam/isam.3d)
 547                          */
 548                         switch(shader)
 549                         {
 550                         case PIPE_SHADER_FRAGMENT:
 551                         case PIPE_SHADER_COMPUTE:
 552                                 return 24;
 553                         default:
 554                                 return 0;
 555                         }
 556                 }
 557                 return 0;
 558         }
 559         debug_printf("unknown shader param %d\n", param);
 560         return 0;
 561 }
 562
 563 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 564  * into per-generation backend?
 565  */
 566 static int
 567 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 568                 enum pipe_compute_cap param, void *ret)
 569 {
 570         struct fd_screen *screen = fd_screen(pscreen);
 571         const char * const ir = "ir3";
 572
 573         if (!has_compute(screen))
 574                 return 0;
 575
 576 #define RET(x) do {                  \
 577    if (ret)                          \
 578       memcpy(ret, x, sizeof(x));     \
 579    return sizeof(x);                 \
 580 } while (0)
 581
 582         switch (param) {
 583         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 584 // don't expose 64b pointer support yet, until ir3 supports 64b
 585 // math, otherwise spir64 target is used and we get 64b pointer
 586 // calculations that we can't do yet
 587 //              if (is_a5xx(screen))
 588 //                      RET((uint32_t []){ 64 });
 589                 RET((uint32_t []){ 32 });
 590
 591         case PIPE_COMPUTE_CAP_IR_TARGET:
 592                 if (ret)
 593                         sprintf(ret, ir);
 594                 return strlen(ir) * sizeof(char);
 595
 596         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 597                 RET((uint64_t []) { 3 });
 598
 599         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 600                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 601
 602         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 603                 RET(((uint64_t []) { 1024, 1024, 64 }));
 604
 605         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 606                 RET((uint64_t []) { 1024 });
 607
 608         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 609                 RET((uint64_t []) { screen->ram_size });
 610
 611         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 612                 RET((uint64_t []) { 32768 });
 613
 614         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 615         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 616                 RET((uint64_t []) { 4096 });
 617
 618         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 619                 RET((uint64_t []) { screen->ram_size });
 620
 621         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 622                 RET((uint32_t []) { screen->max_freq / 1000000 });
 623
 624         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 625                 RET((uint32_t []) { 9999 });  // TODO
 626
 627         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 628                 RET((uint32_t []) { 1 });
 629
 630         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 631                 RET((uint32_t []) { 32 });  // TODO
 632
 633         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 634                 RET((uint64_t []) { 1024 }); // TODO
 635         }
 636
 637         return 0;
 638 }
 639
 640 static const void *
 641 fd_get_compiler_options(struct pipe_screen *pscreen,
 642                 enum pipe_shader_ir ir, unsigned shader)
 643 {
 644         struct fd_screen *screen = fd_screen(pscreen);
 645
 646         if (is_ir3(screen))
 647                 return ir3_get_compiler_options(screen->compiler);
 648
 649         return ir2_get_compiler_options();
 650 }
 651
 652 boolean
 653 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 654                 struct fd_bo *bo,
 655                 struct renderonly_scanout *scanout,
 656                 unsigned stride,
 657                 struct winsys_handle *whandle)
 658 {
 659         whandle->stride = stride;
 660
 661         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 662                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 663         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 664                 if (renderonly_get_handle(scanout, whandle))
 665                         return TRUE;
 666                 whandle->handle = fd_bo_handle(bo);
 667                 return TRUE;
 668         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 669                 whandle->handle = fd_bo_dmabuf(bo);
 670                 return TRUE;
 671         } else {
 672                 return FALSE;
 673         }
 674 }
 675
 676 static void
 677 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 678                 enum pipe_format format,
 679                 int max, uint64_t *modifiers,
 680                 unsigned int *external_only,
 681                 int *count)
 682 {
 683         struct fd_screen *screen = fd_screen(pscreen);
 684         int i, num = 0;
 685
 686         max = MIN2(max, screen->num_supported_modifiers);
 687
 688         if (!max) {
 689                 max = screen->num_supported_modifiers;
 690                 external_only = NULL;
 691                 modifiers = NULL;
 692         }
 693
 694         for (i = 0; i < max; i++) {
 695                 if (modifiers)
 696                         modifiers[num] = screen->supported_modifiers[i];
 697
 698                 if (external_only)
 699                         external_only[num] = 0;
 700
 701                 num++;
 702         }
 703
 704         *count = num;
 705 }
 706
 707 struct fd_bo *
 708 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 709                 struct winsys_handle *whandle)
 710 {
 711         struct fd_screen *screen = fd_screen(pscreen);
 712         struct fd_bo *bo;
 713
 714         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 715                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 716         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 717                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 718         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 719                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 720         } else {
 721                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 722                 return NULL;
 723         }
 724
 725         if (!bo) {
 726                 DBG("ref name 0x%08x failed", whandle->handle);
 727                 return NULL;
 728         }
 729
 730         return bo;
 731 }
 732
 733 struct pipe_screen *
 734 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 735 {
 736         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 737         struct pipe_screen *pscreen;
 738         uint64_t val;
 739
 740         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 741
 742         if (fd_mesa_debug & FD_DBG_NOBIN)
 743                 fd_binning_enabled = false;
 744
 745         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 746
 747         if (!screen)
 748                 return NULL;
 749
 750         pscreen = &screen->base;
 751
 752         screen->dev = dev;
 753         screen->refcnt = 1;
 754
 755         if (ro) {
 756                 screen->ro = renderonly_dup(ro);
 757                 if (!screen->ro) {
 758                         DBG("could not create renderonly object");
 759                         goto fail;
 760                 }
 761         }
 762
 763         // maybe this should be in context?
 764         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 765         if (!screen->pipe) {
 766                 DBG("could not create 3d pipe");
 767                 goto fail;
 768         }
 769
 770         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 771                 DBG("could not get GMEM size");
 772                 goto fail;
 773         }
 774         screen->gmemsize_bytes = val;
 775
 776         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 777                 DBG("could not get device-id");
 778                 goto fail;
 779         }
 780         screen->device_id = val;
 781
 782         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 783                 DBG("could not get gpu freq");
 784                 /* this limits what performance related queries are
 785                  * supported but is not fatal
 786                  */
 787                 screen->max_freq = 0;
 788         } else {
 789                 screen->max_freq = val;
 790                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 791                         screen->has_timestamp = true;
 792         }
 793
 794         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 795                 DBG("could not get gpu-id");
 796                 goto fail;
 797         }
 798         screen->gpu_id = val;
 799
 800         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 801                 DBG("could not get chip-id");
 802                 /* older kernels may not have this property: */
 803                 unsigned core  = screen->gpu_id / 100;
 804                 unsigned major = (screen->gpu_id % 100) / 10;
 805                 unsigned minor = screen->gpu_id % 10;
 806                 unsigned patch = 0;  /* assume the worst */
 807                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 808                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 809         }
 810         screen->chip_id = val;
 811
 812         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 813                 DBG("could not get # of rings");
 814                 screen->priority_mask = 0;
 815         } else {
 816                 /* # of rings equates to number of unique priority values: */
 817                 screen->priority_mask = (1 << val) - 1;
 818         }
 819
 820         struct sysinfo si;
 821         sysinfo(&si);
 822         screen->ram_size = si.totalram;
 823
 824         DBG("Pipe Info:");
 825         DBG(" GPU-id:          %d", screen->gpu_id);
 826         DBG(" Chip-id:         0x%08x", screen->chip_id);
 827         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 828
 829         /* explicitly checking for GPU revisions that are known to work.  This
 830          * may be overly conservative for a3xx, where spoofing the gpu_id with
 831          * the blob driver seems to generate identical cmdstream dumps.  But
 832          * on a2xx, there seem to be small differences between the GPU revs
 833          * so it is probably better to actually test first on real hardware
 834          * before enabling:
 835          *
 836          * If you have a different adreno version, feel free to add it to one
 837          * of the cases below and see what happens.  And if it works, please
 838          * send a patch ;-)
 839          */
 840         switch (screen->gpu_id) {
 841         case 200:
 842         case 201:
 843         case 205:
 844         case 220:
 845                 fd2_screen_init(pscreen);
 846                 break;
 847         case 305:
 848         case 307:
 849         case 320:
 850         case 330:
 851                 fd3_screen_init(pscreen);
 852                 break;
 853         case 420:
 854         case 430:
 855                 fd4_screen_init(pscreen);
 856                 break;
 857         case 530:
 858                 fd5_screen_init(pscreen);
 859                 break;
 860         case 630:
 861                 fd6_screen_init(pscreen);
 862                 break;
 863         default:
 864                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 865                 goto fail;
 866         }
 867
 868         if (screen->gpu_id >= 600) {
 869                 screen->gmem_alignw = 32;
 870                 screen->gmem_alignh = 32;
 871                 screen->num_vsc_pipes = 32;
 872         } else if (screen->gpu_id >= 500) {
 873                 screen->gmem_alignw = 64;
 874                 screen->gmem_alignh = 32;
 875                 screen->num_vsc_pipes = 16;
 876         } else {
 877                 screen->gmem_alignw = 32;
 878                 screen->gmem_alignh = 32;
 879                 screen->num_vsc_pipes = 8;
 880         }
 881
 882         /* NOTE: don't enable reordering on a2xx, since completely untested.
 883          * Also, don't enable if we have too old of a kernel to support
 884          * growable cmdstream buffers, since memory requirement for cmdstream
 885          * buffers would be too much otherwise.
 886          */
 887         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 888                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 889
 890         fd_bc_init(&screen->batch_cache);
 891
 892         (void) mtx_init(&screen->lock, mtx_plain);
 893
 894         pscreen->destroy = fd_screen_destroy;
 895         pscreen->get_param = fd_screen_get_param;
 896         pscreen->get_paramf = fd_screen_get_paramf;
 897         pscreen->get_shader_param = fd_screen_get_shader_param;
 898         pscreen->get_compute_param = fd_get_compute_param;
 899         pscreen->get_compiler_options = fd_get_compiler_options;
 900
 901         fd_resource_screen_init(pscreen);
 902         fd_query_screen_init(pscreen);
 903
 904         pscreen->get_name = fd_screen_get_name;
 905         pscreen->get_vendor = fd_screen_get_vendor;
 906         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 907
 908         pscreen->get_timestamp = fd_screen_get_timestamp;
 909
 910         pscreen->fence_reference = fd_fence_ref;
 911         pscreen->fence_finish = fd_fence_finish;
 912         pscreen->fence_get_fd = fd_fence_get_fd;
 913
 914         pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
 915
 916         if (!screen->supported_modifiers) {
 917                 static const uint64_t supported_modifiers[] = {
 918                         DRM_FORMAT_MOD_LINEAR,
 919                 };
 920
 921                 screen->supported_modifiers = supported_modifiers;
 922                 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
 923         }
 924
 925         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 926
 927         return pscreen;
 928
 929 fail:
 930         fd_screen_destroy(pscreen);
 931         return NULL;
 932 }