2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
40 #include "util/os_time.h"
42 #include "drm-uapi/drm_fourcc.h"
46 #include <sys/sysinfo.h>
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
60 /* for fd_get_driver/device_uuid() */
61 #include "common/freedreno_uuid.h"
63 #include "ir3/ir3_nir.h"
64 #include "ir3/ir3_compiler.h"
67 static const struct debug_named_value debug_options
[] = {
68 {"msgs", FD_DBG_MSGS
, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM
, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR
, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW
, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS
, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT
, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS
, "Disable GMEM bypass"},
75 {"log", FD_DBG_LOG
, "Enable GPU timestamp based logging (a6xx+)"},
76 {"nobin", FD_DBG_NOBIN
, "Disable hw binning"},
77 {"nogmem", FD_DBG_NOGMEM
, "Disable GMEM rendering (bypass only)"},
79 {"shaderdb", FD_DBG_SHADERDB
, "Enable shaderdb output"},
80 {"flush", FD_DBG_FLUSH
, "Force flush after every draw"},
81 {"deqp", FD_DBG_DEQP
, "Enable dEQP hacks"},
82 {"inorder", FD_DBG_INORDER
,"Disable reordering for draws/blits"},
83 {"bstat", FD_DBG_BSTAT
, "Print batch stats at context destroy"},
84 {"nogrow", FD_DBG_NOGROW
, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 {"lrz", FD_DBG_LRZ
, "Enable experimental LRZ support (a5xx)"},
86 {"noindirect",FD_DBG_NOINDR
, "Disable hw indirect draws (emulate on CPU)"},
87 {"noblit", FD_DBG_NOBLIT
, "Disable blitter (fallback to generic blit path)"},
88 {"hiprio", FD_DBG_HIPRIO
, "Force high-priority context"},
89 {"ttile", FD_DBG_TTILE
, "Enable texture tiling (a2xx/a3xx/a5xx)"},
90 {"perfcntrs", FD_DBG_PERFC
, "Expose performance counters"},
91 {"noubwc", FD_DBG_NOUBWC
, "Disable UBWC for all internal buffers"},
92 {"nolrz", FD_DBG_NOLRZ
, "Disable LRZ (a6xx)"},
93 {"notile", FD_DBG_NOTILE
, "Disable tiling for all internal buffers"},
94 {"layout", FD_DBG_LAYOUT
, "Dump resource layouts"},
95 {"nofp16", FD_DBG_NOFP16
, "Disable mediump precision lowering"},
96 {"nohw", FD_DBG_NOHW
, "Disable submitting commands to the HW"},
100 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug
, "FD_MESA_DEBUG", debug_options
, 0)
102 int fd_mesa_debug
= 0;
103 bool fd_binning_enabled
= true;
106 fd_screen_get_name(struct pipe_screen
*pscreen
)
108 static char buffer
[128];
109 snprintf(buffer
, sizeof(buffer
), "FD%03d",
110 fd_screen(pscreen
)->device_id
);
115 fd_screen_get_vendor(struct pipe_screen
*pscreen
)
121 fd_screen_get_device_vendor(struct pipe_screen
*pscreen
)
128 fd_screen_get_timestamp(struct pipe_screen
*pscreen
)
130 struct fd_screen
*screen
= fd_screen(pscreen
);
132 if (screen
->has_timestamp
) {
134 fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &n
);
135 debug_assert(screen
->max_freq
> 0);
136 return n
* 1000000000 / screen
->max_freq
;
138 int64_t cpu_time
= os_time_get() * 1000;
139 return cpu_time
+ screen
->cpu_gpu_time_delta
;
145 fd_screen_destroy(struct pipe_screen
*pscreen
)
147 struct fd_screen
*screen
= fd_screen(pscreen
);
150 fd_pipe_del(screen
->pipe
);
153 fd_device_del(screen
->dev
);
158 fd_bc_fini(&screen
->batch_cache
);
159 fd_gmem_screen_fini(pscreen
);
161 slab_destroy_parent(&screen
->transfer_pool
);
163 simple_mtx_destroy(&screen
->lock
);
165 if (screen
->compiler
)
166 ir3_compiler_destroy(screen
->compiler
);
168 ralloc_free(screen
->live_batches
);
170 free(screen
->perfcntr_queries
);
175 TODO either move caps to a2xx/a3xx specific code, or maybe have some
176 tables for things that differ if the delta is not too much..
179 fd_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
181 struct fd_screen
*screen
= fd_screen(pscreen
);
183 /* this is probably not totally correct.. but it's a start: */
185 /* Supported features (boolean caps). */
186 case PIPE_CAP_NPOT_TEXTURES
:
187 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
188 case PIPE_CAP_ANISOTROPIC_FILTER
:
189 case PIPE_CAP_POINT_SPRITE
:
190 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
191 case PIPE_CAP_TEXTURE_SWIZZLE
:
192 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
193 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
194 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
195 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
196 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
197 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
198 case PIPE_CAP_STRING_MARKER
:
199 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
200 case PIPE_CAP_TEXTURE_BARRIER
:
201 case PIPE_CAP_INVALIDATE_BUFFER
:
202 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
203 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
204 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
210 return !is_a2xx(screen
);
212 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
213 return is_a2xx(screen
);
214 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
215 return !is_a2xx(screen
);
217 case PIPE_CAP_PACKED_UNIFORMS
:
218 return !is_a2xx(screen
);
220 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
221 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
222 return screen
->has_robustness
;
224 case PIPE_CAP_VERTEXID_NOBASE
:
225 return is_a3xx(screen
) || is_a4xx(screen
);
227 case PIPE_CAP_COMPUTE
:
228 return has_compute(screen
);
230 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
231 case PIPE_CAP_PCI_GROUP
:
232 case PIPE_CAP_PCI_BUS
:
233 case PIPE_CAP_PCI_DEVICE
:
234 case PIPE_CAP_PCI_FUNCTION
:
235 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
238 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
239 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
240 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
241 case PIPE_CAP_PRIMITIVE_RESTART
:
242 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
243 case PIPE_CAP_TGSI_INSTANCEID
:
244 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
245 case PIPE_CAP_INDEP_BLEND_ENABLE
:
246 case PIPE_CAP_INDEP_BLEND_FUNC
:
247 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
248 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
249 case PIPE_CAP_CONDITIONAL_RENDER
:
250 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
251 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
252 case PIPE_CAP_CLIP_HALFZ
:
253 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
255 case PIPE_CAP_FAKE_SW_MSAA
:
256 return !fd_screen_get_param(pscreen
, PIPE_CAP_TEXTURE_MULTISAMPLE
);
258 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
259 return is_a5xx(screen
) || is_a6xx(screen
);
261 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
262 return is_a6xx(screen
);
264 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
265 return is_a3xx(screen
) || is_a4xx(screen
);
267 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
268 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
270 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
271 if (is_a3xx(screen
)) return 16;
272 if (is_a4xx(screen
)) return 32;
273 if (is_a5xx(screen
)) return 32;
274 if (is_a6xx(screen
)) return 64;
276 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
277 /* We could possibly emulate more by pretending 2d/rect textures and
278 * splitting high bits of index into 2nd dimension..
280 if (is_a3xx(screen
)) return 8192;
281 if (is_a4xx(screen
)) return 16384;
282 if (is_a5xx(screen
)) return 16384;
283 if (is_a6xx(screen
)) return 1 << 27;
286 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
287 case PIPE_CAP_CUBE_MAP_ARRAY
:
288 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
289 case PIPE_CAP_TEXTURE_QUERY_LOD
:
290 return is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
292 case PIPE_CAP_START_INSTANCE
:
293 /* Note that a5xx can do this, it just can't (at least with
294 * current firmware) do draw_indirect with base_instance.
295 * Since draw_indirect is needed sooner (gles31 and gl40 vs
296 * gl42), hide base_instance on a5xx. :-/
298 return is_a4xx(screen
);
300 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
303 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
304 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
305 return is_ir3(screen
) ? 140 : 120;
307 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
308 /* we can probably enable 320 for a5xx too, but need to test: */
309 if (is_a6xx(screen
)) return 320;
310 if (is_a5xx(screen
)) return 310;
311 if (is_ir3(screen
)) return 300;
314 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
315 if (is_a6xx(screen
)) return 64;
316 if (is_a5xx(screen
)) return 4;
319 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
320 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
324 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
325 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
328 case PIPE_CAP_FBFETCH
:
329 if (fd_device_version(screen
->dev
) >= FD_VERSION_GMEM_BASE
&&
333 case PIPE_CAP_SAMPLE_SHADING
:
334 if (is_a6xx(screen
)) return 1;
337 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
338 return screen
->priority_mask
;
340 case PIPE_CAP_DRAW_INDIRECT
:
341 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
345 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
346 if (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
))
350 case PIPE_CAP_LOAD_CONSTBUF
:
351 /* name is confusing, but this turns on std430 packing */
356 case PIPE_CAP_NIR_IMAGES_AS_DEREF
:
359 case PIPE_CAP_MAX_VIEWPORTS
:
362 case PIPE_CAP_MAX_VARYINGS
:
365 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
366 /* We don't really have a limit on this, it all goes into the main
367 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
368 * for GL_MAX_TESS_PATCH_COMPONENTS).
372 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
373 return 64 * 1024 * 1024;
375 case PIPE_CAP_SHAREABLE_SHADERS
:
376 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
377 /* manage the variants for these ourself, to avoid breaking precompile: */
378 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
379 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
384 /* Geometry shaders.. */
385 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
387 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
389 case PIPE_CAP_MAX_GS_INVOCATIONS
:
393 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
395 return PIPE_MAX_SO_BUFFERS
;
397 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
398 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
399 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
400 case PIPE_CAP_TGSI_TEXCOORD
:
404 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
406 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
407 return is_a2xx(screen
);
408 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
409 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
411 return 16 * 4; /* should only be shader out limit? */
415 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
416 if (is_a6xx(screen
) || is_a5xx(screen
) || is_a4xx(screen
))
420 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
421 if (is_a6xx(screen
) || is_a5xx(screen
) || is_a4xx(screen
))
425 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
428 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
429 return (is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 256 : 0;
431 /* Render targets. */
432 case PIPE_CAP_MAX_RENDER_TARGETS
:
433 return screen
->max_rts
;
434 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
435 return is_a3xx(screen
) ? 1 : 0;
438 case PIPE_CAP_OCCLUSION_QUERY
:
439 return is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
);
440 case PIPE_CAP_QUERY_TIMESTAMP
:
441 case PIPE_CAP_QUERY_TIME_ELAPSED
:
442 /* only a4xx, requires new enough kernel so we know max_freq: */
443 return (screen
->max_freq
> 0) && (is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
));
445 case PIPE_CAP_VENDOR_ID
:
447 case PIPE_CAP_DEVICE_ID
:
449 case PIPE_CAP_ACCELERATED
:
451 case PIPE_CAP_VIDEO_MEMORY
:
452 DBG("FINISHME: The value returned is incorrect\n");
456 case PIPE_CAP_MEMOBJ
:
457 return fd_device_version(screen
->dev
) >= FD_VERSION_MEMORY_FD
;
458 case PIPE_CAP_NATIVE_FENCE_FD
:
459 return fd_device_version(screen
->dev
) >= FD_VERSION_FENCE_FD
;
461 return u_pipe_screen_get_param_defaults(pscreen
, param
);
466 fd_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
469 case PIPE_CAPF_MAX_LINE_WIDTH
:
470 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
471 /* NOTE: actual value is 127.0f, but this is working around a deqp
472 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
473 * uses too small of a render target size, and gets confused when
474 * the lines start going offscreen.
476 * See: https://code.google.com/p/android/issues/detail?id=206513
478 if (fd_mesa_debug
& FD_DBG_DEQP
)
481 case PIPE_CAPF_MAX_POINT_WIDTH
:
482 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
484 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
486 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
488 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
489 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
490 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
493 debug_printf("unknown paramf %d\n", param
);
498 fd_screen_get_shader_param(struct pipe_screen
*pscreen
,
499 enum pipe_shader_type shader
,
500 enum pipe_shader_cap param
)
502 struct fd_screen
*screen
= fd_screen(pscreen
);
506 case PIPE_SHADER_FRAGMENT
:
507 case PIPE_SHADER_VERTEX
:
509 case PIPE_SHADER_TESS_CTRL
:
510 case PIPE_SHADER_TESS_EVAL
:
511 case PIPE_SHADER_GEOMETRY
:
515 case PIPE_SHADER_COMPUTE
:
516 if (has_compute(screen
))
520 DBG("unknown shader type %d", shader
);
524 /* this is probably not totally correct.. but it's a start: */
526 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
527 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
528 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
529 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
531 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
533 case PIPE_SHADER_CAP_MAX_INPUTS
:
534 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
536 case PIPE_SHADER_CAP_MAX_TEMPS
:
537 return 64; /* Max native temporaries. */
538 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
539 /* NOTE: seems to be limit for a3xx is actually 512 but
540 * split between VS and FS. Use lower limit of 256 to
541 * avoid getting into impossible situations:
543 return ((is_a3xx(screen
) || is_a4xx(screen
) || is_a5xx(screen
) || is_a6xx(screen
)) ? 4096 : 64) * sizeof(float[4]);
544 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
545 return is_ir3(screen
) ? 16 : 1;
546 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
548 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
549 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
550 /* Technically this should be the same as for TEMP/CONST, since
551 * everything is just normal registers. This is just temporary
552 * hack until load_input/store_output handle arrays in a similar
553 * way as load_var/store_var..
555 * For tessellation stages, inputs are loaded using ldlw or ldg, both
556 * of which support indirection.
558 return shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
;
559 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
560 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
561 /* a2xx compiler doesn't handle indirect: */
562 return is_ir3(screen
) ? 1 : 0;
563 case PIPE_SHADER_CAP_SUBROUTINES
:
564 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
565 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
566 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
567 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
568 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
569 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
570 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
571 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
572 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
574 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
576 case PIPE_SHADER_CAP_INTEGERS
:
577 return is_ir3(screen
) ? 1 : 0;
578 case PIPE_SHADER_CAP_INT64_ATOMICS
:
579 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
580 case PIPE_SHADER_CAP_INT16
:
581 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
583 case PIPE_SHADER_CAP_FP16
:
584 return ((is_a5xx(screen
) || is_a6xx(screen
)) &&
585 (shader
== PIPE_SHADER_COMPUTE
||
586 shader
== PIPE_SHADER_FRAGMENT
) &&
587 !(fd_mesa_debug
& FD_DBG_NOFP16
));
588 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
589 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
591 case PIPE_SHADER_CAP_PREFERRED_IR
:
592 return PIPE_SHADER_IR_NIR
;
593 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
594 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
595 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
597 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
598 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
599 if (is_a5xx(screen
) || is_a6xx(screen
)) {
600 /* a5xx (and a4xx for that matter) has one state-block
601 * for compute-shader SSBO's and another that is shared
602 * by VS/HS/DS/GS/FS.. so to simplify things for now
603 * just advertise SSBOs for FS and CS. We could possibly
604 * do what blob does, and partition the space for
605 * VS/HS/DS/GS/FS. The blob advertises:
607 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
608 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
609 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
610 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
611 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
612 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
613 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
615 * I think that way we could avoid having to patch shaders
616 * for actual SSBO indexes by using a static partitioning.
618 * Note same state block is used for images and buffers,
619 * but images also need texture state for read access
624 case PIPE_SHADER_FRAGMENT
:
625 case PIPE_SHADER_COMPUTE
:
633 debug_printf("unknown shader param %d\n", param
);
637 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
638 * into per-generation backend?
641 fd_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
642 enum pipe_compute_cap param
, void *ret
)
644 struct fd_screen
*screen
= fd_screen(pscreen
);
645 const char * const ir
= "ir3";
647 if (!has_compute(screen
))
650 #define RET(x) do { \
652 memcpy(ret, x, sizeof(x)); \
657 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
658 // don't expose 64b pointer support yet, until ir3 supports 64b
659 // math, otherwise spir64 target is used and we get 64b pointer
660 // calculations that we can't do yet
661 // if (is_a5xx(screen))
662 // RET((uint32_t []){ 64 });
663 RET((uint32_t []){ 32 });
665 case PIPE_COMPUTE_CAP_IR_TARGET
:
667 sprintf(ret
, "%s", ir
);
668 return strlen(ir
) * sizeof(char);
670 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
671 RET((uint64_t []) { 3 });
673 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
674 RET(((uint64_t []) { 65535, 65535, 65535 }));
676 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
677 RET(((uint64_t []) { 1024, 1024, 64 }));
679 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
680 RET((uint64_t []) { 1024 });
682 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
683 RET((uint64_t []) { screen
->ram_size
});
685 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
686 RET((uint64_t []) { 32768 });
688 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
689 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
690 RET((uint64_t []) { 4096 });
692 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
693 RET((uint64_t []) { screen
->ram_size
});
695 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
696 RET((uint32_t []) { screen
->max_freq
/ 1000000 });
698 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
699 RET((uint32_t []) { 9999 }); // TODO
701 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
702 RET((uint32_t []) { 1 });
704 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
705 RET((uint32_t []) { 32 }); // TODO
707 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
708 RET((uint64_t []) { 1024 }); // TODO
715 fd_get_compiler_options(struct pipe_screen
*pscreen
,
716 enum pipe_shader_ir ir
, unsigned shader
)
718 struct fd_screen
*screen
= fd_screen(pscreen
);
721 return ir3_get_compiler_options(screen
->compiler
);
723 return ir2_get_compiler_options();
726 static struct disk_cache
*
727 fd_get_disk_shader_cache(struct pipe_screen
*pscreen
)
729 struct fd_screen
*screen
= fd_screen(pscreen
);
731 if (is_ir3(screen
)) {
732 struct ir3_compiler
*compiler
= screen
->compiler
;
733 return compiler
->disk_cache
;
740 fd_screen_bo_get_handle(struct pipe_screen
*pscreen
,
742 struct renderonly_scanout
*scanout
,
744 struct winsys_handle
*whandle
)
746 whandle
->stride
= stride
;
748 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
749 return fd_bo_get_name(bo
, &whandle
->handle
) == 0;
750 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
751 if (renderonly_get_handle(scanout
, whandle
))
753 whandle
->handle
= fd_bo_handle(bo
);
755 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
756 whandle
->handle
= fd_bo_dmabuf(bo
);
764 fd_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
765 enum pipe_format format
,
766 int max
, uint64_t *modifiers
,
767 unsigned int *external_only
,
770 struct fd_screen
*screen
= fd_screen(pscreen
);
773 max
= MIN2(max
, screen
->num_supported_modifiers
);
776 max
= screen
->num_supported_modifiers
;
777 external_only
= NULL
;
781 for (i
= 0; i
< max
; i
++) {
783 modifiers
[num
] = screen
->supported_modifiers
[i
];
786 external_only
[num
] = 0;
795 fd_screen_bo_from_handle(struct pipe_screen
*pscreen
,
796 struct winsys_handle
*whandle
)
798 struct fd_screen
*screen
= fd_screen(pscreen
);
801 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
802 bo
= fd_bo_from_name(screen
->dev
, whandle
->handle
);
803 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
804 bo
= fd_bo_from_handle(screen
->dev
, whandle
->handle
, 0);
805 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
806 bo
= fd_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
808 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
813 DBG("ref name 0x%08x failed", whandle
->handle
);
820 static void _fd_fence_ref(struct pipe_screen
*pscreen
,
821 struct pipe_fence_handle
**ptr
,
822 struct pipe_fence_handle
*pfence
)
824 fd_fence_ref(ptr
, pfence
);
828 fd_screen_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
830 struct fd_screen
*screen
= fd_screen(pscreen
);
832 fd_get_device_uuid(uuid
, screen
->gpu_id
);
836 fd_screen_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
838 fd_get_driver_uuid(uuid
);
842 fd_screen_create(struct fd_device
*dev
, struct renderonly
*ro
)
844 struct fd_screen
*screen
= CALLOC_STRUCT(fd_screen
);
845 struct pipe_screen
*pscreen
;
848 fd_mesa_debug
= debug_get_option_fd_mesa_debug();
850 if (fd_mesa_debug
& FD_DBG_NOBIN
)
851 fd_binning_enabled
= false;
856 pscreen
= &screen
->base
;
862 screen
->ro
= renderonly_dup(ro
);
864 DBG("could not create renderonly object");
869 // maybe this should be in context?
870 screen
->pipe
= fd_pipe_new(screen
->dev
, FD_PIPE_3D
);
872 DBG("could not create 3d pipe");
876 if (fd_pipe_get_param(screen
->pipe
, FD_GMEM_SIZE
, &val
)) {
877 DBG("could not get GMEM size");
880 screen
->gmemsize_bytes
= val
;
882 if (fd_device_version(dev
) >= FD_VERSION_GMEM_BASE
) {
883 fd_pipe_get_param(screen
->pipe
, FD_GMEM_BASE
, &screen
->gmem_base
);
886 if (fd_pipe_get_param(screen
->pipe
, FD_DEVICE_ID
, &val
)) {
887 DBG("could not get device-id");
890 screen
->device_id
= val
;
892 if (fd_pipe_get_param(screen
->pipe
, FD_MAX_FREQ
, &val
)) {
893 DBG("could not get gpu freq");
894 /* this limits what performance related queries are
895 * supported but is not fatal
897 screen
->max_freq
= 0;
899 screen
->max_freq
= val
;
900 if (fd_pipe_get_param(screen
->pipe
, FD_TIMESTAMP
, &val
) == 0)
901 screen
->has_timestamp
= true;
904 if (fd_pipe_get_param(screen
->pipe
, FD_GPU_ID
, &val
)) {
905 DBG("could not get gpu-id");
908 screen
->gpu_id
= val
;
910 if (fd_pipe_get_param(screen
->pipe
, FD_CHIP_ID
, &val
)) {
911 DBG("could not get chip-id");
912 /* older kernels may not have this property: */
913 unsigned core
= screen
->gpu_id
/ 100;
914 unsigned major
= (screen
->gpu_id
% 100) / 10;
915 unsigned minor
= screen
->gpu_id
% 10;
916 unsigned patch
= 0; /* assume the worst */
917 val
= (patch
& 0xff) | ((minor
& 0xff) << 8) |
918 ((major
& 0xff) << 16) | ((core
& 0xff) << 24);
920 screen
->chip_id
= val
;
922 if (fd_pipe_get_param(screen
->pipe
, FD_NR_RINGS
, &val
)) {
923 DBG("could not get # of rings");
924 screen
->priority_mask
= 0;
926 /* # of rings equates to number of unique priority values: */
927 screen
->priority_mask
= (1 << val
) - 1;
930 if (fd_device_version(dev
) >= FD_VERSION_ROBUSTNESS
)
931 screen
->has_robustness
= true;
935 screen
->ram_size
= si
.totalram
;
938 DBG(" GPU-id: %d", screen
->gpu_id
);
939 DBG(" Chip-id: 0x%08x", screen
->chip_id
);
940 DBG(" GMEM size: 0x%08x", screen
->gmemsize_bytes
);
942 /* explicitly checking for GPU revisions that are known to work. This
943 * may be overly conservative for a3xx, where spoofing the gpu_id with
944 * the blob driver seems to generate identical cmdstream dumps. But
945 * on a2xx, there seem to be small differences between the GPU revs
946 * so it is probably better to actually test first on real hardware
949 * If you have a different adreno version, feel free to add it to one
950 * of the cases below and see what happens. And if it works, please
953 switch (screen
->gpu_id
) {
958 fd2_screen_init(pscreen
);
964 fd3_screen_init(pscreen
);
969 fd4_screen_init(pscreen
);
974 fd5_screen_init(pscreen
);
980 fd6_screen_init(pscreen
);
983 debug_printf("unsupported GPU: a%03d\n", screen
->gpu_id
);
987 if (screen
->gpu_id
>= 600) {
988 screen
->gmem_alignw
= 16;
989 screen
->gmem_alignh
= 4;
990 screen
->tile_alignw
= is_a650(screen
) ? 96 : 32;
991 screen
->tile_alignh
= 32;
992 screen
->num_vsc_pipes
= 32;
993 } else if (screen
->gpu_id
>= 500) {
994 screen
->gmem_alignw
= screen
->tile_alignw
= 64;
995 screen
->gmem_alignh
= screen
->tile_alignh
= 32;
996 screen
->num_vsc_pipes
= 16;
998 screen
->gmem_alignw
= screen
->tile_alignw
= 32;
999 screen
->gmem_alignh
= screen
->tile_alignh
= 32;
1000 screen
->num_vsc_pipes
= 8;
1003 if (fd_mesa_debug
& FD_DBG_PERFC
) {
1004 screen
->perfcntr_groups
= fd_perfcntrs(screen
->gpu_id
,
1005 &screen
->num_perfcntr_groups
);
1008 /* NOTE: don't enable if we have too old of a kernel to support
1009 * growable cmdstream buffers, since memory requirement for cmdstream
1010 * buffers would be too much otherwise.
1012 if (fd_device_version(dev
) >= FD_VERSION_UNLIMITED_CMDS
)
1013 screen
->reorder
= !(fd_mesa_debug
& FD_DBG_INORDER
);
1016 screen
->live_batches
= _mesa_pointer_set_create(NULL
);
1018 fd_bc_init(&screen
->batch_cache
);
1020 list_inithead(&screen
->context_list
);
1022 (void) simple_mtx_init(&screen
->lock
, mtx_plain
);
1024 pscreen
->destroy
= fd_screen_destroy
;
1025 pscreen
->get_param
= fd_screen_get_param
;
1026 pscreen
->get_paramf
= fd_screen_get_paramf
;
1027 pscreen
->get_shader_param
= fd_screen_get_shader_param
;
1028 pscreen
->get_compute_param
= fd_get_compute_param
;
1029 pscreen
->get_compiler_options
= fd_get_compiler_options
;
1030 pscreen
->get_disk_shader_cache
= fd_get_disk_shader_cache
;
1032 fd_resource_screen_init(pscreen
);
1033 fd_query_screen_init(pscreen
);
1034 fd_gmem_screen_init(pscreen
);
1036 pscreen
->get_name
= fd_screen_get_name
;
1037 pscreen
->get_vendor
= fd_screen_get_vendor
;
1038 pscreen
->get_device_vendor
= fd_screen_get_device_vendor
;
1040 pscreen
->get_timestamp
= fd_screen_get_timestamp
;
1042 pscreen
->fence_reference
= _fd_fence_ref
;
1043 pscreen
->fence_finish
= fd_fence_finish
;
1044 pscreen
->fence_get_fd
= fd_fence_get_fd
;
1046 pscreen
->query_dmabuf_modifiers
= fd_screen_query_dmabuf_modifiers
;
1048 pscreen
->get_device_uuid
= fd_screen_get_device_uuid
;
1049 pscreen
->get_driver_uuid
= fd_screen_get_driver_uuid
;
1051 slab_create_parent(&screen
->transfer_pool
, sizeof(struct fd_transfer
), 16);
1056 fd_screen_destroy(pscreen
);