src/gallium/drivers/freedreno/freedreno_util.h

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FREEDRENO_UTIL_H_
  28 #define FREEDRENO_UTIL_H_
  29
  30 #include "drm/freedreno_drmif.h"
  31 #include "drm/freedreno_ringbuffer.h"
  32
  33 #include "pipe/p_format.h"
  34 #include "pipe/p_state.h"
  35 #include "util/u_debug.h"
  36 #include "util/u_math.h"
  37 #include "util/u_half.h"
  38 #include "util/u_dynarray.h"
  39 #include "util/u_pack_color.h"
  40
  41 #include "disasm.h"
  42 #include "adreno_common.xml.h"
  43 #include "adreno_pm4.xml.h"
  44
  45 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
  46 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
  47 enum pipe_format fd_gmem_restore_format(enum pipe_format format);
  48 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
  49 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
  50 enum adreno_stencil_op fd_stencil_op(unsigned op);
  51
  52 #define A3XX_MAX_MIP_LEVELS 14
  53 /* TBD if it is same on a2xx, but for now: */
  54 #define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
  55
  56 #define A2XX_MAX_RENDER_TARGETS 1
  57 #define A3XX_MAX_RENDER_TARGETS 4
  58 #define A4XX_MAX_RENDER_TARGETS 8
  59 #define A5XX_MAX_RENDER_TARGETS 8
  60 #define A6XX_MAX_RENDER_TARGETS 8
  61
  62 #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
  63
  64 enum fd_debug_flag {
  65         FD_DBG_MSGS         = BITFIELD_BIT(0),
  66         FD_DBG_DISASM       = BITFIELD_BIT(1),
  67         FD_DBG_DCLEAR       = BITFIELD_BIT(2),
  68         FD_DBG_DDRAW        = BITFIELD_BIT(3),
  69         FD_DBG_NOSCIS       = BITFIELD_BIT(4),
  70         FD_DBG_DIRECT       = BITFIELD_BIT(5),
  71         FD_DBG_NOBYPASS     = BITFIELD_BIT(6),
  72         FD_DBG_FRAGHALF     = BITFIELD_BIT(7),
  73         FD_DBG_NOBIN        = BITFIELD_BIT(8),
  74         FD_DBG_NOGMEM       = BITFIELD_BIT(9),
  75         FD_DBG_GLSL120      = BITFIELD_BIT(10),
  76         FD_DBG_SHADERDB     = BITFIELD_BIT(11),
  77         FD_DBG_FLUSH        = BITFIELD_BIT(12),
  78         FD_DBG_DEQP         = BITFIELD_BIT(13),
  79         FD_DBG_INORDER      = BITFIELD_BIT(14),
  80         FD_DBG_BSTAT        = BITFIELD_BIT(15),
  81         FD_DBG_NOGROW       = BITFIELD_BIT(16),
  82         FD_DBG_LRZ          = BITFIELD_BIT(17),
  83         FD_DBG_NOINDR       = BITFIELD_BIT(18),
  84         FD_DBG_NOBLIT       = BITFIELD_BIT(19),
  85         FD_DBG_HIPRIO       = BITFIELD_BIT(20),
  86         FD_DBG_TTILE        = BITFIELD_BIT(21),
  87         FD_DBG_PERFC        = BITFIELD_BIT(22),
  88         FD_DBG_NOUBWC       = BITFIELD_BIT(23),
  89         FD_DBG_NOLRZ        = BITFIELD_BIT(24),
  90         FD_DBG_NOTILE       = BITFIELD_BIT(25),
  91         FD_DBG_LAYOUT       = BITFIELD_BIT(26),
  92
  93 };
  94
  95 extern int fd_mesa_debug;
  96 extern bool fd_binning_enabled;
  97
  98 #define DBG(fmt, ...) \
  99                 do { if (fd_mesa_debug & FD_DBG_MSGS) \
 100                         debug_printf("%s:%d: "fmt "\n", \
 101                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
 102
 103 /* for conditionally setting boolean flag(s): */
 104 #define COND(bool, val) ((bool) ? (val) : 0)
 105
 106 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
 107
 108 static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 109                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 110                 enum pc_di_vis_cull_mode vis_cull_mode,
 111                 uint8_t instances)
 112 {
 113         return (prim_type         << 0) |
 114                         (source_select     << 6) |
 115                         ((index_size & 1)  << 11) |
 116                         ((index_size >> 1) << 13) |
 117                         (vis_cull_mode     << 9) |
 118                         (1                 << 14) |
 119                         (instances         << 24);
 120 }
 121
 122 static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
 123                 enum pc_di_face_cull_sel faceness_cull_select,
 124                 enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
 125                 bool pre_fetch_cull_enable,
 126                 bool grp_cull_enable,
 127                 uint16_t count)
 128 {
 129         return (prim_type         << 0) |
 130                         (source_select     << 6) |
 131                         (faceness_cull_select << 8) |
 132                         ((index_size & 1)  << 11) |
 133                         ((index_size >> 1) << 13) |
 134                         (pre_fetch_cull_enable << 14) |
 135                         (grp_cull_enable << 15) |
 136                         (count         << 16);
 137 }
 138
 139 /* for tracking cmdstream positions that need to be patched: */
 140 struct fd_cs_patch {
 141         uint32_t *cs;
 142         uint32_t val;
 143 };
 144 #define fd_patch_num_elements(buf) ((buf)->size / sizeof(struct fd_cs_patch))
 145 #define fd_patch_element(buf, i)   util_dynarray_element(buf, struct fd_cs_patch, i)
 146
 147 static inline enum pipe_format
 148 pipe_surface_format(struct pipe_surface *psurf)
 149 {
 150         if (!psurf)
 151                 return PIPE_FORMAT_NONE;
 152         return psurf->format;
 153 }
 154
 155 static inline bool
 156 fd_surface_half_precision(const struct pipe_surface *psurf)
 157 {
 158         enum pipe_format format;
 159
 160         if (!psurf)
 161                 return true;
 162
 163         format = psurf->format;
 164
 165         /* colors are provided in consts, which go through cov.f32f16, which will
 166          * break these values
 167          */
 168         if (util_format_is_pure_integer(format))
 169                 return false;
 170
 171         /* avoid losing precision on 32-bit float formats */
 172         if (util_format_is_float(format) &&
 173                 util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
 174                 return false;
 175
 176         return true;
 177 }
 178
 179 static inline unsigned
 180 fd_sampler_first_level(const struct pipe_sampler_view *view)
 181 {
 182         if (view->target == PIPE_BUFFER)
 183                 return 0;
 184         return view->u.tex.first_level;
 185 }
 186
 187 static inline unsigned
 188 fd_sampler_last_level(const struct pipe_sampler_view *view)
 189 {
 190         if (view->target == PIPE_BUFFER)
 191                 return 0;
 192         return view->u.tex.last_level;
 193 }
 194
 195 static inline bool
 196 fd_half_precision(struct pipe_framebuffer_state *pfb)
 197 {
 198         unsigned i;
 199
 200         for (i = 0; i < pfb->nr_cbufs; i++)
 201                 if (!fd_surface_half_precision(pfb->cbufs[i]))
 202                         return false;
 203
 204         return true;
 205 }
 206
 207 /* Note sure if this is same on all gens, but seems to be same on the later
 208  * gen's
 209  */
 210 static inline unsigned
 211 fd_calc_guardband(unsigned x)
 212 {
 213         float l = log2(x);
 214         if (l <= 8)
 215                 return 511;
 216         return 511 - ((l - 8) * 65);
 217 }
 218
 219 #define LOG_DWORDS 0
 220
 221 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
 222
 223 static inline void
 224 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 225 {
 226         if (LOG_DWORDS) {
 227                 DBG("ring[%p]: OUT_RING   %04x:  %08x", ring,
 228                                 (uint32_t)(ring->cur - ring->start), data);
 229         }
 230         fd_ringbuffer_emit(ring, data);
 231 }
 232
 233 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
 234 static inline void
 235 OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
 236                 struct util_dynarray *buf)
 237 {
 238         if (LOG_DWORDS) {
 239                 DBG("ring[%p]: OUT_RINGP  %04x:  %08x", ring,
 240                                 (uint32_t)(ring->cur - ring->start), data);
 241         }
 242         util_dynarray_append(buf, struct fd_cs_patch, ((struct fd_cs_patch){
 243                 .cs  = ring->cur++,
 244                 .val = data,
 245         }));
 246 }
 247
 248 /*
 249  * NOTE: OUT_RELOC*() is 2 dwords (64b) on a5xx+
 250  */
 251
 252 static inline void
 253 __out_reloc(struct fd_ringbuffer *ring, struct fd_bo *bo,
 254                 uint32_t offset, uint64_t or, int32_t shift, uint32_t flags)
 255 {
 256         if (LOG_DWORDS) {
 257                 DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 258                                 (uint32_t)(ring->cur - ring->start), bo, offset, shift);
 259         }
 260         debug_assert(offset < fd_bo_size(bo));
 261         fd_ringbuffer_reloc(ring, &(struct fd_reloc){
 262                 .bo = bo,
 263                 .flags = flags,
 264                 .offset = offset,
 265                 .or = or,
 266                 .shift = shift,
 267                 .orhi = or >> 32,
 268         });
 269 }
 270
 271 static inline void
 272 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
 273                 uint32_t offset, uint64_t or, int32_t shift)
 274 {
 275         __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ);
 276 }
 277
 278 static inline void
 279 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
 280                 uint32_t offset, uint64_t or, int32_t shift)
 281 {
 282         __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_WRITE);
 283 }
 284
 285 static inline void
 286 OUT_RELOCD(struct fd_ringbuffer *ring, struct fd_bo *bo,
 287                 uint32_t offset, uint64_t or, int32_t shift)
 288 {
 289         __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_DUMP);
 290 }
 291
 292 static inline void
 293 OUT_RB(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 294 {
 295         fd_ringbuffer_emit_reloc_ring_full(ring, target, 0);
 296 }
 297
 298 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 299 {
 300         if (ring->cur + ndwords > ring->end)
 301                 fd_ringbuffer_grow(ring, ndwords);
 302 }
 303
 304 static inline void
 305 OUT_PKT0(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 306 {
 307         BEGIN_RING(ring, cnt+1);
 308         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 309 }
 310
 311 static inline void
 312 OUT_PKT2(struct fd_ringbuffer *ring)
 313 {
 314         BEGIN_RING(ring, 1);
 315         OUT_RING(ring, CP_TYPE2_PKT);
 316 }
 317
 318 static inline void
 319 OUT_PKT3(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 320 {
 321         BEGIN_RING(ring, cnt+1);
 322         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 323 }
 324
 325 /*
 326  * Starting with a5xx, pkt4/pkt7 are used instead of pkt0/pkt3
 327  */
 328
 329 static inline unsigned
 330 _odd_parity_bit(unsigned val)
 331 {
 332         /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
 333          * note that we want odd parity so 0x6996 is inverted.
 334          */
 335         val ^= val >> 16;
 336         val ^= val >> 8;
 337         val ^= val >> 4;
 338         val &= 0xf;
 339         return (~0x6996 >> val) & 1;
 340 }
 341
 342 static inline void
 343 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 344 {
 345         BEGIN_RING(ring, cnt+1);
 346         OUT_RING(ring, CP_TYPE4_PKT | cnt |
 347                         (_odd_parity_bit(cnt) << 7) |
 348                         ((regindx & 0x3ffff) << 8) |
 349                         ((_odd_parity_bit(regindx) << 27)));
 350 }
 351
 352 static inline void
 353 OUT_PKT7(struct fd_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 354 {
 355         BEGIN_RING(ring, cnt+1);
 356         OUT_RING(ring, CP_TYPE7_PKT | cnt |
 357                         (_odd_parity_bit(cnt) << 15) |
 358                         ((opcode & 0x7f) << 16) |
 359                         ((_odd_parity_bit(opcode) << 23)));
 360 }
 361
 362 static inline void
 363 OUT_WFI(struct fd_ringbuffer *ring)
 364 {
 365         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 366         OUT_RING(ring, 0x00000000);
 367 }
 368
 369 static inline void
 370 OUT_WFI5(struct fd_ringbuffer *ring)
 371 {
 372         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 373 }
 374
 375 static inline void
 376 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 377 {
 378         if (target->cur == target->start)
 379                 return;
 380
 381         unsigned count = fd_ringbuffer_cmd_count(target);
 382
 383         /* for debug after a lock up, write a unique counter value
 384          * to scratch6 for each IB, to make it easier to match up
 385          * register dumps to cmdstream.  The combination of IB and
 386          * DRAW (scratch7) is enough to "triangulate" the particular
 387          * draw that caused lockup.
 388          */
 389         emit_marker(ring, 6);
 390
 391         for (unsigned i = 0; i < count; i++) {
 392                 uint32_t dwords;
 393                 OUT_PKT3(ring, prefetch ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 394                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 395                 assert(dwords > 0);
 396                 OUT_RING(ring, dwords);
 397                 OUT_PKT2(ring);
 398         }
 399
 400         emit_marker(ring, 6);
 401 }
 402
 403 static inline void
 404 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 405 {
 406         if (target->cur == target->start)
 407                 return;
 408
 409         unsigned count = fd_ringbuffer_cmd_count(target);
 410
 411         for (unsigned i = 0; i < count; i++) {
 412                 uint32_t dwords;
 413                 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
 414                 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
 415                 assert(dwords > 0);
 416                 OUT_RING(ring, dwords);
 417         }
 418 }
 419
 420 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
 421 // XXX annoyingly scratch regs move on a5xx.. and additionally different
 422 // packet types.. so freedreno_query_hw is going to need a bit of
 423 // rework..
 424 #define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
 425
 426 static inline void
 427 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 428 {
 429         extern unsigned marker_cnt;
 430         unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
 431         assert(reg != HW_QUERY_BASE_REG);
 432         if (reg == HW_QUERY_BASE_REG)
 433                 return;
 434         OUT_PKT0(ring, reg, 1);
 435         OUT_RING(ring, ++marker_cnt);
 436 }
 437
 438 static inline uint32_t
 439 pack_rgba(enum pipe_format format, const float *rgba)
 440 {
 441         union util_color uc;
 442         util_pack_color(rgba, format, &uc);
 443         return uc.ui[0];
 444 }
 445
 446 /*
 447  * swap - swap value of @a and @b
 448  */
 449 #define swap(a, b) \
 450         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 451
 452 #define foreach_bit(b, mask) \
 453         for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 454
 455
 456 #define BIT(bit) (1u << bit)
 457
 458 /*
 459  * a3xx+ helpers:
 460  */
 461
 462 static inline enum a3xx_msaa_samples
 463 fd_msaa_samples(unsigned samples)
 464 {
 465         switch (samples) {
 466         default:
 467                 debug_assert(0);
 468         case 0:
 469         case 1: return MSAA_ONE;
 470         case 2: return MSAA_TWO;
 471         case 4: return MSAA_FOUR;
 472         case 8: return MSAA_EIGHT;
 473         }
 474 }
 475
 476 /*
 477  * a4xx+ helpers:
 478  */
 479
 480 static inline enum a4xx_state_block
 481 fd4_stage2shadersb(gl_shader_stage type)
 482 {
 483         switch (type) {
 484         case MESA_SHADER_VERTEX:
 485                 return SB4_VS_SHADER;
 486         case MESA_SHADER_FRAGMENT:
 487                 return SB4_FS_SHADER;
 488         case MESA_SHADER_COMPUTE:
 489         case MESA_SHADER_KERNEL:
 490                 return SB4_CS_SHADER;
 491         default:
 492                 unreachable("bad shader type");
 493                 return ~0;
 494         }
 495 }
 496
 497 static inline enum a4xx_index_size
 498 fd4_size2indextype(unsigned index_size)
 499 {
 500         switch (index_size) {
 501         case 1: return INDEX4_SIZE_8_BIT;
 502         case 2: return INDEX4_SIZE_16_BIT;
 503         case 4: return INDEX4_SIZE_32_BIT;
 504         }
 505         DBG("unsupported index size: %d", index_size);
 506         assert(0);
 507         return INDEX4_SIZE_32_BIT;
 508 }
 509
 510 #endif /* FREEDRENO_UTIL_H_ */