2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "ir3/ir3_nir.h"
29 /* This has to reach into the fd_context a bit more than the rest of
30 * ir3, but it needs to be aligned with the compiler, so both agree
31 * on which const regs hold what. And the logic is identical between
32 * ir3 generations, the only difference is small details in the actual
33 * CP_LOAD_STATE packets (which is handled inside the generation
34 * specific ctx->emit_const(_bo)() fxns)
36 * This file should be included in only a single .c file per gen, which
37 * defines the following functions:
40 static bool is_stateobj(struct fd_ringbuffer
*ring
);
42 static void emit_const(struct fd_ringbuffer
*ring
,
43 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
44 uint32_t offset
, uint32_t size
,
45 const void *user_buffer
, struct pipe_resource
*buffer
);
47 static void emit_const_bo(struct fd_ringbuffer
*ring
,
48 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
49 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
);
53 ring_wfi(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
55 /* when we emit const state via ring (IB2) we need a WFI, but when
56 * it is emit'd via stateobj, we don't
58 if (is_stateobj(ring
))
65 * Indirectly calculates size of cmdstream needed for ir3_emit_user_consts().
66 * Returns number of packets, and total size of all the payload.
68 * The value can be a worst-case, ie. some shader variants may not read all
71 * Returns size in dwords.
74 ir3_user_consts_size(struct ir3_ubo_analysis_state
*state
,
75 unsigned *packets
, unsigned *size
)
79 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
80 if (state
->range
[i
].start
< state
->range
[i
].end
) {
81 *size
+= state
->range
[i
].end
- state
->range
[i
].start
;
88 * Uploads sub-ranges of UBOs to the hardware's constant buffer (UBO access
89 * outside of these ranges will be done using full UBO accesses in the
93 ir3_emit_user_consts(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
94 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
96 struct ir3_ubo_analysis_state
*state
;
97 state
= &v
->shader
->ubo_state
;
99 for (unsigned i
= 0; i
< state
->num_enabled
; i
++) {
100 assert(!state
->range
[i
].bindless
);
101 unsigned ubo
= state
->range
[i
].block
;
102 if (!(constbuf
->enabled_mask
& (1 << ubo
)))
104 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[ubo
];
106 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
107 uint32_t offset
= cb
->buffer_offset
+ state
->range
[i
].start
;
109 /* and even if the start of the const buffer is before
110 * first_immediate, the end may not be:
112 size
= MIN2(size
, (16 * v
->constlen
) - state
->range
[i
].offset
);
117 /* things should be aligned to vec4: */
118 debug_assert((state
->range
[i
].offset
% 16) == 0);
119 debug_assert((size
% 16) == 0);
120 debug_assert((offset
% 16) == 0);
122 emit_const(ring
, v
, state
->range
[i
].offset
/ 4,
123 offset
, size
/ 4, cb
->user_buffer
, cb
->buffer
);
128 ir3_emit_ubos(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
129 struct fd_ringbuffer
*ring
, struct fd_constbuf_stateobj
*constbuf
)
131 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
132 uint32_t offset
= const_state
->offsets
.ubo
;
133 if (v
->constlen
> offset
) {
134 uint32_t params
= const_state
->num_ubos
;
135 uint32_t offsets
[params
];
136 struct pipe_resource
*prscs
[params
];
138 for (uint32_t i
= 0; i
< params
; i
++) {
139 const uint32_t index
= i
+ 1; /* UBOs start at index 1 */
140 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
141 assert(!cb
->user_buffer
);
143 if ((constbuf
->enabled_mask
& (1 << index
)) && cb
->buffer
) {
144 offsets
[i
] = cb
->buffer_offset
;
145 prscs
[i
] = cb
->buffer
;
152 assert(offset
* 4 + params
< v
->constlen
* 4);
154 emit_const_bo(ring
, v
, offset
* 4, params
, prscs
, offsets
);
159 ir3_emit_ssbo_sizes(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
160 struct fd_ringbuffer
*ring
, struct fd_shaderbuf_stateobj
*sb
)
162 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
163 uint32_t offset
= const_state
->offsets
.ssbo_sizes
;
164 if (v
->constlen
> offset
) {
165 uint32_t sizes
[align(const_state
->ssbo_size
.count
, 4)];
166 unsigned mask
= const_state
->ssbo_size
.mask
;
169 unsigned index
= u_bit_scan(&mask
);
170 unsigned off
= const_state
->ssbo_size
.off
[index
];
171 sizes
[off
] = sb
->sb
[index
].buffer_size
;
174 emit_const(ring
, v
, offset
* 4, 0, ARRAY_SIZE(sizes
), sizes
, NULL
);
179 ir3_emit_image_dims(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
180 struct fd_ringbuffer
*ring
, struct fd_shaderimg_stateobj
*si
)
182 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
183 uint32_t offset
= const_state
->offsets
.image_dims
;
184 if (v
->constlen
> offset
) {
185 uint32_t dims
[align(const_state
->image_dims
.count
, 4)];
186 unsigned mask
= const_state
->image_dims
.mask
;
189 struct pipe_image_view
*img
;
190 struct fd_resource
*rsc
;
191 unsigned index
= u_bit_scan(&mask
);
192 unsigned off
= const_state
->image_dims
.off
[index
];
194 img
= &si
->si
[index
];
195 rsc
= fd_resource(img
->resource
);
197 dims
[off
+ 0] = util_format_get_blocksize(img
->format
);
198 if (img
->resource
->target
!= PIPE_BUFFER
) {
199 struct fdl_slice
*slice
=
200 fd_resource_slice(rsc
, img
->u
.tex
.level
);
201 /* note for 2d/cube/etc images, even if re-interpreted
202 * as a different color format, the pixel size should
203 * be the same, so use original dimensions for y and z
206 dims
[off
+ 1] = slice
->pitch
;
207 /* see corresponding logic in fd_resource_offset(): */
208 if (rsc
->layout
.layer_first
) {
209 dims
[off
+ 2] = rsc
->layout
.layer_size
;
211 dims
[off
+ 2] = slice
->size0
;
214 /* For buffer-backed images, the log2 of the format's
215 * bytes-per-pixel is placed on the 2nd slot. This is useful
216 * when emitting image_size instructions, for which we need
217 * to divide by bpp for image buffers. Since the bpp
218 * can only be power-of-two, the division is implemented
219 * as a SHR, and for that it is handy to have the log2 of
220 * bpp as a constant. (log2 = first-set-bit - 1)
222 dims
[off
+ 1] = ffs(dims
[off
+ 0]) - 1;
225 uint32_t size
= MIN2(ARRAY_SIZE(dims
), v
->constlen
* 4 - offset
* 4);
227 emit_const(ring
, v
, offset
* 4, 0, size
, dims
, NULL
);
232 ir3_emit_immediates(struct fd_screen
*screen
, const struct ir3_shader_variant
*v
,
233 struct fd_ringbuffer
*ring
)
235 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
236 uint32_t base
= const_state
->offsets
.immediate
;
237 int size
= const_state
->immediates_count
;
239 /* truncate size to avoid writing constants that shader
242 size
= MIN2(size
+ base
, v
->constlen
) - base
;
244 /* convert out of vec4: */
249 emit_const(ring
, v
, base
, 0, size
, const_state
->immediates
[0].val
, NULL
);
253 ir3_emit_link_map(struct fd_screen
*screen
,
254 const struct ir3_shader_variant
*producer
,
255 const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
)
257 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
258 uint32_t base
= const_state
->offsets
.primitive_map
;
259 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
261 num_loc
= ir3_link_geometry_stages(producer
, v
, patch_locs
);
263 int size
= DIV_ROUND_UP(num_loc
, 4);
265 /* truncate size to avoid writing constants that shader
268 size
= MIN2(size
+ base
, v
->constlen
) - base
;
270 /* convert out of vec4: */
275 emit_const(ring
, v
, base
, 0, size
, patch_locs
, NULL
);
278 /* emit stream-out buffers: */
280 emit_tfbos(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
281 struct fd_ringbuffer
*ring
)
283 /* streamout addresses after driver-params: */
284 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
285 uint32_t offset
= const_state
->offsets
.tfbo
;
286 if (v
->constlen
> offset
) {
287 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
288 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
290 uint32_t offsets
[params
];
291 struct pipe_resource
*prscs
[params
];
293 for (uint32_t i
= 0; i
< params
; i
++) {
294 struct pipe_stream_output_target
*target
= so
->targets
[i
];
297 offsets
[i
] = (so
->offsets
[i
] * info
->stride
[i
] * 4) +
298 target
->buffer_offset
;
299 prscs
[i
] = target
->buffer
;
306 assert(offset
* 4 + params
< v
->constlen
* 4);
308 emit_const_bo(ring
, v
, offset
* 4, params
, prscs
, offsets
);
312 static inline uint32_t
313 max_tf_vtx(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
)
315 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
316 struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
317 uint32_t maxvtxcnt
= 0x7fffffff;
319 if (ctx
->screen
->gpu_id
>= 500)
323 if (v
->shader
->stream_output
.num_outputs
== 0)
325 if (so
->num_targets
== 0)
328 /* offset to write to is:
330 * total_vtxcnt = vtxcnt + offsets[i]
331 * offset = total_vtxcnt * stride[i]
333 * offset = vtxcnt * stride[i] ; calculated in shader
334 * + offsets[i] * stride[i] ; calculated at emit_tfbos()
336 * assuming for each vtx, each target buffer will have data written
337 * up to 'offset + stride[i]', that leaves maxvtxcnt as:
339 * buffer_size = (maxvtxcnt * stride[i]) + stride[i]
340 * maxvtxcnt = (buffer_size - stride[i]) / stride[i]
342 * but shader is actually doing a less-than (rather than less-than-
343 * equal) check, so we can drop the -stride[i].
345 * TODO is assumption about `offset + stride[i]` legit?
347 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
348 struct pipe_stream_output_target
*target
= so
->targets
[i
];
349 unsigned stride
= info
->stride
[i
] * 4; /* convert dwords->bytes */
351 uint32_t max
= target
->buffer_size
/ stride
;
352 maxvtxcnt
= MIN2(maxvtxcnt
, max
);
360 emit_common_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
361 struct fd_context
*ctx
, enum pipe_shader_type t
)
363 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[t
];
365 /* When we use CP_SET_DRAW_STATE objects to emit constant state,
366 * if we emit any of it we need to emit all. This is because
367 * we are using the same state-group-id each time for uniform
368 * state, and if previous update is never evaluated (due to no
369 * visible primitives in the current tile) then the new stateobj
370 * completely replaces the old one.
372 * Possibly if we split up different parts of the const state to
373 * different state-objects we could avoid this.
375 if (dirty
&& is_stateobj(ring
))
378 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_CONST
)) {
379 struct fd_constbuf_stateobj
*constbuf
;
382 constbuf
= &ctx
->constbuf
[t
];
383 shader_dirty
= !!(dirty
& FD_DIRTY_SHADER_PROG
);
385 ring_wfi(ctx
->batch
, ring
);
387 ir3_emit_user_consts(ctx
->screen
, v
, ring
, constbuf
);
388 ir3_emit_ubos(ctx
->screen
, v
, ring
, constbuf
);
390 ir3_emit_immediates(ctx
->screen
, v
, ring
);
393 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_SSBO
)) {
394 struct fd_shaderbuf_stateobj
*sb
= &ctx
->shaderbuf
[t
];
395 ring_wfi(ctx
->batch
, ring
);
396 ir3_emit_ssbo_sizes(ctx
->screen
, v
, ring
, sb
);
399 if (dirty
& (FD_DIRTY_SHADER_PROG
| FD_DIRTY_SHADER_IMAGE
)) {
400 struct fd_shaderimg_stateobj
*si
= &ctx
->shaderimg
[t
];
401 ring_wfi(ctx
->batch
, ring
);
402 ir3_emit_image_dims(ctx
->screen
, v
, ring
, si
);
407 ir3_needs_vs_driver_params(const struct ir3_shader_variant
*v
)
409 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
410 uint32_t offset
= const_state
->offsets
.driver_param
;
412 return v
->constlen
> offset
;
416 ir3_emit_vs_driver_params(const struct ir3_shader_variant
*v
,
417 struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
418 const struct pipe_draw_info
*info
)
420 debug_assert(ir3_needs_vs_driver_params(v
));
422 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
423 uint32_t offset
= const_state
->offsets
.driver_param
;
424 uint32_t vertex_params
[IR3_DP_VS_COUNT
] = {
425 [IR3_DP_VTXID_BASE
] = info
->index_size
?
426 info
->index_bias
: info
->start
,
427 [IR3_DP_VTXCNT_MAX
] = max_tf_vtx(ctx
, v
),
429 /* if no user-clip-planes, we don't need to emit the
432 uint32_t vertex_params_size
= 4;
434 if (v
->key
.ucp_enables
) {
435 struct pipe_clip_state
*ucp
= &ctx
->ucp
;
436 unsigned pos
= IR3_DP_UCP0_X
;
437 for (unsigned i
= 0; pos
<= IR3_DP_UCP7_W
; i
++) {
438 for (unsigned j
= 0; j
< 4; j
++) {
439 vertex_params
[pos
] = fui(ucp
->ucp
[i
][j
]);
443 vertex_params_size
= ARRAY_SIZE(vertex_params
);
446 vertex_params_size
= MAX2(vertex_params_size
, const_state
->num_driver_params
);
448 bool needs_vtxid_base
=
449 ir3_find_sysval_regid(v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) != regid(63, 0);
451 /* for indirect draw, we need to copy VTXID_BASE from
452 * indirect-draw parameters buffer.. which is annoying
453 * and means we can't easily emit these consts in cmd
454 * stream so need to copy them to bo.
456 if (info
->indirect
&& needs_vtxid_base
) {
457 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
458 struct pipe_resource
*vertex_params_rsc
=
459 pipe_buffer_create(&ctx
->screen
->base
,
460 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
,
461 vertex_params_size
* 4);
462 unsigned src_off
= info
->indirect
->offset
;;
465 ptr
= fd_bo_map(fd_resource(vertex_params_rsc
)->bo
);
466 memcpy(ptr
, vertex_params
, vertex_params_size
* 4);
468 if (info
->index_size
) {
469 /* indexed draw, index_bias is 4th field: */
472 /* non-indexed draw, start is 3rd field: */
476 /* copy index_bias or start from draw params: */
477 ctx
->screen
->mem_to_mem(ring
, vertex_params_rsc
, 0,
478 indirect
->buffer
, src_off
, 1);
480 emit_const(ring
, v
, offset
* 4, 0,
481 vertex_params_size
, NULL
, vertex_params_rsc
);
483 pipe_resource_reference(&vertex_params_rsc
, NULL
);
485 emit_const(ring
, v
, offset
* 4, 0,
486 vertex_params_size
, vertex_params
, NULL
);
489 /* if needed, emit stream-out buffer addresses: */
490 if (vertex_params
[IR3_DP_VTXCNT_MAX
] > 0) {
491 emit_tfbos(ctx
, v
, ring
);
496 ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
497 struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
499 debug_assert(v
->type
== MESA_SHADER_VERTEX
);
501 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_VERTEX
);
503 /* emit driver params every time: */
504 if (info
&& ir3_needs_vs_driver_params(v
)) {
505 ring_wfi(ctx
->batch
, ring
);
506 ir3_emit_vs_driver_params(v
, ring
, ctx
, info
);
511 ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
512 struct fd_context
*ctx
)
514 debug_assert(v
->type
== MESA_SHADER_FRAGMENT
);
516 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_FRAGMENT
);
519 /* emit compute-shader consts: */
521 ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
522 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
524 debug_assert(gl_shader_stage_is_compute(v
->type
));
526 emit_common_consts(v
, ring
, ctx
, PIPE_SHADER_COMPUTE
);
528 /* emit compute-shader driver-params: */
529 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
530 uint32_t offset
= const_state
->offsets
.driver_param
;
531 if (v
->constlen
> offset
) {
532 ring_wfi(ctx
->batch
, ring
);
534 if (info
->indirect
) {
535 struct pipe_resource
*indirect
= NULL
;
536 unsigned indirect_offset
;
538 /* This is a bit awkward, but CP_LOAD_STATE.EXT_SRC_ADDR needs
539 * to be aligned more strongly than 4 bytes. So in this case
540 * we need a temporary buffer to copy NumWorkGroups.xyz to.
542 * TODO if previous compute job is writing to info->indirect,
543 * we might need a WFI.. but since we currently flush for each
544 * compute job, we are probably ok for now.
546 if (info
->indirect_offset
& 0xf) {
547 indirect
= pipe_buffer_create(&ctx
->screen
->base
,
548 PIPE_BIND_COMMAND_ARGS_BUFFER
, PIPE_USAGE_STREAM
,
552 ctx
->screen
->mem_to_mem(ring
, indirect
, 0, info
->indirect
,
553 info
->indirect_offset
, 3);
555 pipe_resource_reference(&indirect
, info
->indirect
);
556 indirect_offset
= info
->indirect_offset
;
559 emit_const(ring
, v
, offset
* 4, indirect_offset
, 4, NULL
, indirect
);
561 pipe_resource_reference(&indirect
, NULL
);
563 uint32_t compute_params
[IR3_DP_CS_COUNT
] = {
564 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->grid
[0],
565 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->grid
[1],
566 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->grid
[2],
567 [IR3_DP_LOCAL_GROUP_SIZE_X
] = info
->block
[0],
568 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = info
->block
[1],
569 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = info
->block
[2],
571 uint32_t size
= MIN2(const_state
->num_driver_params
,
572 v
->constlen
* 4 - offset
* 4);
574 emit_const(ring
, v
, offset
* 4, 0, size
, compute_params
, NULL
);