src/gallium/drivers/i915/i915_state_static.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2010 Jakob Bornecrantz
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  **************************************************************************/
  25
  26
  27 #include "i915_reg.h"
  28 #include "i915_context.h"
  29 #include "i915_state.h"
  30 #include "i915_resource.h"
  31 #include "i915_screen.h"
  32
  33
  34 /***********************************************************************
  35  * Update framebuffer state
  36  */
  37 static unsigned translate_format(enum pipe_format format)
  38 {
  39    switch (format) {
  40    case PIPE_FORMAT_B8G8R8A8_UNORM:
  41    case PIPE_FORMAT_B8G8R8A8_SRGB:
  42    case PIPE_FORMAT_B8G8R8X8_UNORM:
  43    case PIPE_FORMAT_R8G8B8A8_UNORM:
  44    case PIPE_FORMAT_R8G8B8X8_UNORM:
  45       return COLOR_BUF_ARGB8888;
  46    case PIPE_FORMAT_B5G6R5_UNORM:
  47       return COLOR_BUF_RGB565;
  48    case PIPE_FORMAT_B5G5R5A1_UNORM:
  49       return COLOR_BUF_ARGB1555;
  50    case PIPE_FORMAT_B4G4R4A4_UNORM:
  51       return COLOR_BUF_ARGB4444;
  52    case PIPE_FORMAT_B10G10R10A2_UNORM:
  53       return COLOR_BUF_ARGB2101010;
  54    case PIPE_FORMAT_L8_UNORM:
  55    case PIPE_FORMAT_A8_UNORM:
  56    case PIPE_FORMAT_I8_UNORM:
  57       return COLOR_BUF_8BIT;
  58    default:
  59       assert(0);
  60       return 0;
  61    }
  62 }
  63
  64 static unsigned translate_depth_format(enum pipe_format zformat)
  65 {
  66    switch (zformat) {
  67    case PIPE_FORMAT_Z24X8_UNORM:
  68    case PIPE_FORMAT_Z24_UNORM_S8_UINT:
  69       return DEPTH_FRMT_24_FIXED_8_OTHER;
  70    case PIPE_FORMAT_Z16_UNORM:
  71       return DEPTH_FRMT_16_FIXED;
  72    default:
  73       assert(0);
  74       return 0;
  75    }
  76 }
  77
  78 static inline uint32_t
  79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling)
  80 {
  81    uint32_t tiling_bits = 0;
  82
  83    switch (tiling) {
  84    case I915_TILE_Y:
  85       tiling_bits |= BUF_3D_TILE_WALK_Y;
  86    case I915_TILE_X:
  87       tiling_bits |= BUF_3D_TILED_SURFACE;
  88    case I915_TILE_NONE:
  89       break;
  90    }
  91
  92    return tiling_bits;
  93 }
  94
  95 static void update_framebuffer(struct i915_context *i915)
  96 {
  97    struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
  98    struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
  99    unsigned x, y;
 100    int layer;
 101    uint32_t draw_offset, draw_size;
 102
 103    if (cbuf_surface) {
 104       struct i915_texture *tex = i915_texture(cbuf_surface->texture);
 105       assert(tex);
 106
 107       i915->current.cbuf_bo = tex->buffer;
 108       i915->current.cbuf_flags = BUF_3D_ID_COLOR_BACK |
 109                                  BUF_3D_PITCH(tex->stride) |  /* pitch in bytes */
 110                                  buf_3d_tiling_bits(tex->tiling);
 111
 112       layer = cbuf_surface->u.tex.first_layer;
 113
 114       x = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksx;
 115       y = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksy;
 116    } else {
 117       i915->current.cbuf_bo = NULL;
 118       x = y = 0;
 119    }
 120    i915->static_dirty |= I915_DST_BUF_COLOR;
 121
 122    /* What happens if no zbuf??
 123     */
 124    if (depth_surface) {
 125       struct i915_texture *tex = i915_texture(depth_surface->texture);
 126       unsigned offset = i915_texture_offset(tex, depth_surface->u.tex.level,
 127                                             depth_surface->u.tex.first_layer);
 128       assert(tex);
 129       if (offset != 0)
 130          debug_printf("Depth offset is %d\n",offset);
 131
 132       i915->current.depth_bo = tex->buffer;
 133       i915->current.depth_flags = BUF_3D_ID_DEPTH |
 134                                   BUF_3D_PITCH(tex->stride) |  /* pitch in bytes */
 135                                   buf_3d_tiling_bits(tex->tiling);
 136    } else
 137       i915->current.depth_bo = NULL;
 138    i915->static_dirty |= I915_DST_BUF_DEPTH;
 139
 140    /* drawing rect calculations */
 141    draw_offset = x | (y << 16);
 142    draw_size = (i915->framebuffer.width - 1 + x) |
 143                ((i915->framebuffer.height - 1 + y) << 16);
 144    if (i915->current.draw_offset != draw_offset) {
 145       i915->current.draw_offset = draw_offset;
 146       i915_set_flush_dirty(i915, I915_PIPELINE_FLUSH);
 147       i915->static_dirty |= I915_DST_RECT;
 148    }
 149    if (i915->current.draw_size != draw_size) {
 150       i915->current.draw_size = draw_size;
 151       i915->static_dirty |= I915_DST_RECT;
 152    }
 153
 154    i915->hardware_dirty |= I915_HW_STATIC;
 155
 156    /* flush the cache in case we sample from the old renderbuffers */
 157    i915_set_flush_dirty(i915, I915_FLUSH_CACHE);
 158 }
 159
 160 struct i915_tracked_state i915_hw_framebuffer = {
 161    "framebuffer",
 162    update_framebuffer,
 163    I915_NEW_FRAMEBUFFER
 164 };
 165
 166 static uint32_t need_target_fixup(struct pipe_surface* p, uint32_t *fixup)
 167 {
 168    const struct
 169    {
 170       enum pipe_format format;
 171       uint hw_swizzle;
 172    } fixup_formats[] = {
 173       { PIPE_FORMAT_R8G8B8A8_UNORM, 0x21030000 /* BGRA */},
 174       { PIPE_FORMAT_R8G8B8X8_UNORM, 0x21030000 /* BGRX */},
 175       { PIPE_FORMAT_L8_UNORM,       0x00030000 /* RRRA */},
 176       { PIPE_FORMAT_I8_UNORM,       0x00030000 /* RRRA */},
 177       { PIPE_FORMAT_A8_UNORM,       0x33330000 /* AAAA */},
 178       { PIPE_FORMAT_NONE,           0x00000000},
 179    };
 180
 181    enum pipe_format f;
 182    /* if we don't have a surface bound yet, we don't need to fixup the shader */
 183    if (!p)
 184       return 0;
 185
 186    f = p->format;
 187    for(int i = 0; fixup_formats[i].format != PIPE_FORMAT_NONE; i++)
 188       if (fixup_formats[i].format == f) {
 189          *fixup = fixup_formats[i].hw_swizzle;
 190          return f;
 191       }
 192
 193    *fixup = 0;
 194    return 0;
 195 }
 196
 197 static void update_dst_buf_vars(struct i915_context *i915)
 198 {
 199    struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
 200    struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
 201    uint32_t dst_buf_vars, cformat, zformat;
 202    uint32_t early_z = 0;
 203    uint32_t fixup = 0;
 204    int need_fixup;
 205
 206    if (cbuf_surface)
 207       cformat = cbuf_surface->format;
 208    else
 209       cformat = PIPE_FORMAT_B8G8R8A8_UNORM; /* arbitrary */
 210    cformat = translate_format(cformat);
 211
 212    if (depth_surface) {
 213       struct i915_texture *tex = i915_texture(depth_surface->texture);
 214       struct i915_screen *is = i915_screen(i915->base.screen);
 215
 216       zformat = translate_depth_format(depth_surface->format);
 217
 218       if (is->is_i945 && tex->tiling != I915_TILE_NONE
 219           && (i915->fs && !i915->fs->info.writes_z))
 220          early_z = CLASSIC_EARLY_DEPTH;
 221    } else
 222       zformat = 0;
 223
 224    dst_buf_vars = DSTORG_HORT_BIAS(0x8) | /* .5 */
 225                   DSTORG_VERT_BIAS(0x8) | /* .5 */
 226                   LOD_PRECLAMP_OGL |
 227                   TEX_DEFAULT_COLOR_OGL |
 228                   cformat |
 229                   zformat |
 230                   early_z;
 231
 232    if (i915->current.dst_buf_vars != dst_buf_vars) {
 233       if (early_z != (i915->current.dst_buf_vars & CLASSIC_EARLY_DEPTH))
 234          i915_set_flush_dirty(i915, I915_PIPELINE_FLUSH);
 235
 236       i915->current.dst_buf_vars = dst_buf_vars;
 237       i915->static_dirty |= I915_DST_VARS;
 238       i915->hardware_dirty |= I915_HW_STATIC;
 239    }
 240
 241    need_fixup = need_target_fixup(cbuf_surface, &fixup);
 242    if (i915->current.target_fixup_format != need_fixup ||
 243          i915->current.fixup_swizzle != fixup) {
 244       i915->current.target_fixup_format = need_fixup;
 245       i915->current.fixup_swizzle = fixup;
 246       /* we also send a new program to make sure the fixup for RGBA surfaces happens */
 247       i915->hardware_dirty |= I915_HW_PROGRAM;
 248    }
 249 }
 250
 251 struct i915_tracked_state i915_hw_dst_buf_vars = {
 252    "dst buf vars",
 253    update_dst_buf_vars,
 254    I915_NEW_FRAMEBUFFER | I915_NEW_FS
 255 };