src/gallium/drivers/i965/brw_clip.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_math.h"
  35
  36 #include "brw_screen.h"
  37 #include "brw_batchbuffer.h"
  38 #include "brw_defines.h"
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "brw_util.h"
  42 #include "brw_state.h"
  43 #include "brw_pipe_rast.h"
  44 #include "brw_clip.h"
  45
  46
  47 #define FRONT_UNFILLED_BIT  0x1
  48 #define BACK_UNFILLED_BIT   0x2
  49
  50
  51 static enum pipe_error
  52 compile_clip_prog( struct brw_context *brw,
  53                    struct brw_clip_prog_key *key,
  54                    struct brw_winsys_buffer **bo_out )
  55 {
  56    enum pipe_error ret;
  57    struct brw_clip_compile c;
  58    const GLuint *program;
  59    GLuint program_size;
  60    GLuint delta;
  61
  62    memset(&c, 0, sizeof(c));
  63
  64    /* Begin the compilation:
  65     */
  66    brw_init_compile(brw, &c.func);
  67
  68    c.func.single_program_flow = 1;
  69
  70    c.chipset = brw->chipset;
  71    c.key = *key;
  72    c.need_ff_sync = c.chipset.is_igdng;
  73
  74    /* Need to locate the two positions present in vertex + header.
  75     * These are currently hardcoded:
  76     */
  77    c.header_position_offset = ATTR_SIZE;
  78
  79    if (c.chipset.is_igdng)
  80        delta = 3 * REG_SIZE;
  81    else
  82        delta = REG_SIZE;
  83
  84    c.offset_hpos = delta + c.key.output_hpos * ATTR_SIZE;
  85
  86    if (c.key.output_color0 != BRW_OUTPUT_NOT_PRESENT)
  87       c.offset_color0 = delta + c.key.output_color0 * ATTR_SIZE;
  88
  89    if (c.key.output_color1 != BRW_OUTPUT_NOT_PRESENT)
  90       c.offset_color1 = delta + c.key.output_color1 * ATTR_SIZE;
  91
  92    if (c.key.output_bfc0 != BRW_OUTPUT_NOT_PRESENT)
  93       c.offset_bfc0 = delta + c.key.output_bfc0 * ATTR_SIZE;
  94
  95    if (c.key.output_bfc1 != BRW_OUTPUT_NOT_PRESENT)
  96       c.offset_bfc1 = delta + c.key.output_bfc1 * ATTR_SIZE;
  97
  98    if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
  99       c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
 100
 101    if (BRW_IS_IGDNG(brw))
 102        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
 103    else
 104        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
 105
 106    c.nr_bytes = c.nr_regs * REG_SIZE;
 107
 108    c.prog_data.clip_mode = c.key.clip_mode; /* XXX */
 109
 110    /* For some reason the thread is spawned with only 4 channels
 111     * unmasked.
 112     */
 113    brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
 114
 115
 116    /* Would ideally have the option of producing a program which could
 117     * do all three:
 118     */
 119    switch (key->primitive) {
 120    case PIPE_PRIM_TRIANGLES:
 121       if (key->do_unfilled)
 122          brw_emit_unfilled_clip( &c );
 123       else
 124          brw_emit_tri_clip( &c );
 125       break;
 126    case PIPE_PRIM_LINES:
 127       brw_emit_line_clip( &c );
 128       break;
 129    case PIPE_PRIM_POINTS:
 130       brw_emit_point_clip( &c );
 131       break;
 132    default:
 133       assert(0);
 134       return PIPE_ERROR_BAD_INPUT;
 135    }
 136
 137
 138
 139    /* get the program
 140     */
 141    ret = brw_get_program(&c.func, &program, &program_size);
 142    if (ret)
 143       return ret;
 144
 145    /* Upload
 146     */
 147    ret = brw_upload_cache( &brw->cache,
 148                            BRW_CLIP_PROG,
 149                            &c.key, sizeof(c.key),
 150                            NULL, 0,
 151                            program, program_size,
 152                            &c.prog_data,
 153                            &brw->clip.prog_data,
 154                            bo_out );
 155    if (ret)
 156       return ret;
 157
 158    return PIPE_OK;
 159 }
 160
 161 /* Calculate interpolants for triangle and line rasterization.
 162  */
 163 static enum pipe_error
 164 upload_clip_prog(struct brw_context *brw)
 165 {
 166    const struct brw_vertex_shader *vs = brw->curr.vertex_shader;
 167    struct brw_clip_prog_key key;
 168    enum pipe_error ret;
 169
 170    /* Populate the key, starting from the almost-complete version from
 171     * the rast state.
 172     */
 173
 174    /* PIPE_NEW_RAST */
 175    key = brw->curr.rast->clip_key;
 176
 177    /* BRW_NEW_REDUCED_PRIMITIVE */
 178    key.primitive = brw->reduced_primitive;
 179
 180    /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove
 181     * dependency on CACHE_NEW_VS_PROG
 182     */
 183    /* CACHE_NEW_VS_PROG */
 184    key.nr_attrs        = brw->vs.prog_data->nr_outputs;
 185
 186    /* PIPE_NEW_VS */
 187    key.output_hpos     = vs->output_hpos;
 188    key.output_color0   = vs->output_color0;
 189    key.output_color1   = vs->output_color1;
 190    key.output_bfc0     = vs->output_bfc0;
 191    key.output_bfc1     = vs->output_bfc1;
 192    key.output_edgeflag = vs->output_edgeflag;
 193
 194    /* PIPE_NEW_CLIP */
 195    key.nr_userclip = brw->curr.ucp.nr;
 196
 197    /* Already cached?
 198     */
 199    if (brw_search_cache(&brw->cache, BRW_CLIP_PROG,
 200                         &key, sizeof(key),
 201                         NULL, 0,
 202                         &brw->clip.prog_data,
 203                         &brw->clip.prog_bo))
 204       return PIPE_OK;
 205
 206    /* Compile new program:
 207     */
 208    ret = compile_clip_prog( brw, &key, &brw->clip.prog_bo );
 209    if (ret)
 210       return ret;
 211
 212    return PIPE_OK;
 213 }
 214
 215
 216 const struct brw_tracked_state brw_clip_prog = {
 217    .dirty = {
 218       .mesa  = (PIPE_NEW_RAST |
 219                 PIPE_NEW_CLIP),
 220       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
 221       .cache = CACHE_NEW_VS_PROG
 222    },
 223    .prepare = upload_clip_prog
 224 };