src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_debug.h"
  38
  39 #ifdef DEBUG
  40 static const struct debug_named_value debug_names[] = {
  41    { "tex",   DEBUG_TEXTURE},
  42    { "state", DEBUG_STATE},
  43    { "ioctl", DEBUG_IOCTL},
  44    { "blit",  DEBUG_BLIT},
  45    { "curbe", DEBUG_CURBE},
  46    { "fall",  DEBUG_FALLBACKS},
  47    { "verb",  DEBUG_VERBOSE},
  48    { "bat",   DEBUG_BATCH},
  49    { "pix",   DEBUG_PIXEL},
  50    { "wins",  DEBUG_WINSYS},
  51    { "min",   DEBUG_MIN_URB},
  52    { "dis",   DEBUG_DISASSEM},
  53    { "sync",  DEBUG_SYNC},
  54    { "prim",  DEBUG_PRIMS },
  55    { "vert",  DEBUG_VERTS },
  56    { "dma",   DEBUG_DMA },
  57    { "san",   DEBUG_SANITY },
  58    { "sleep", DEBUG_SLEEP },
  59    { "stats", DEBUG_STATS },
  60    { "sing",  DEBUG_SINGLE_THREAD },
  61    { "thre",  DEBUG_SINGLE_THREAD },
  62    { "wm",    DEBUG_WM },
  63    { "urb",   DEBUG_URB },
  64    { "vs",    DEBUG_VS },
  65    { NULL,    0 }
  66 };
  67
  68 static const struct debug_named_value dump_names[] = {
  69    { "asm",   DUMP_ASM},
  70    { "state", DUMP_STATE},
  71    { "batch", DUMP_BATCH},
  72    { NULL, 0 }
  73 };
  74
  75 int BRW_DEBUG = 0;
  76 int BRW_DUMP = 0;
  77
  78 #endif
  79
  80
  81 /*
  82  * Probe functions
  83  */
  84
  85
  86 static const char *
  87 brw_get_vendor(struct pipe_screen *screen)
  88 {
  89    return "VMware, Inc.";
  90 }
  91
  92 static const char *
  93 brw_get_name(struct pipe_screen *screen)
  94 {
  95    static char buffer[128];
  96    const char *chipset;
  97
  98    switch (brw_screen(screen)->chipset.pci_id) {
  99    case PCI_CHIP_I965_G:
 100       chipset = "I965_G";
 101       break;
 102    case PCI_CHIP_I965_Q:
 103       chipset = "I965_Q";
 104       break;
 105    case PCI_CHIP_I965_G_1:
 106       chipset = "I965_G_1";
 107       break;
 108    case PCI_CHIP_I946_GZ:
 109       chipset = "I946_GZ";
 110       break;
 111    case PCI_CHIP_I965_GM:
 112       chipset = "I965_GM";
 113       break;
 114    case PCI_CHIP_I965_GME:
 115       chipset = "I965_GME";
 116       break;
 117    case PCI_CHIP_GM45_GM:
 118       chipset = "GM45_GM";
 119       break;
 120    case PCI_CHIP_IGD_E_G:
 121       chipset = "IGD_E_G";
 122       break;
 123    case PCI_CHIP_Q45_G:
 124       chipset = "Q45_G";
 125       break;
 126    case PCI_CHIP_G45_G:
 127       chipset = "G45_G";
 128       break;
 129    case PCI_CHIP_G41_G:
 130       chipset = "G41_G";
 131       break;
 132    case PCI_CHIP_B43_G:
 133       chipset = "B43_G";
 134       break;
 135    case PCI_CHIP_ILD_G:
 136       chipset = "ILD_G";
 137       break;
 138    case PCI_CHIP_ILM_G:
 139       chipset = "ILM_G";
 140       break;
 141    default:
 142       chipset = "unknown";
 143       break;
 144    }
 145
 146    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 147    return buffer;
 148 }
 149
 150 static int
 151 brw_get_param(struct pipe_screen *screen, int param)
 152 {
 153    switch (param) {
 154    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 155       return 8;
 156    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 157       return 8;
 158    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 159       return 16; /* XXX correct? */
 160    case PIPE_CAP_NPOT_TEXTURES:
 161       return 1;
 162    case PIPE_CAP_TWO_SIDED_STENCIL:
 163       return 1;
 164    case PIPE_CAP_GLSL:
 165       return 0;
 166    case PIPE_CAP_ANISOTROPIC_FILTER:
 167       return 0;
 168    case PIPE_CAP_POINT_SPRITE:
 169       return 0;
 170    case PIPE_CAP_MAX_RENDER_TARGETS:
 171       return 1;
 172    case PIPE_CAP_OCCLUSION_QUERY:
 173       return 0;
 174    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 175       return 1;
 176    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 177       return BRW_MAX_TEXTURE_2D_LEVELS;
 178    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 179       return BRW_MAX_TEXTURE_3D_LEVELS;
 180    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 181       return BRW_MAX_TEXTURE_2D_LEVELS;
 182    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 183    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 184       return 1;
 185    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 186    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 187       return 0;
 188    default:
 189       return 0;
 190    }
 191 }
 192
 193 static float
 194 brw_get_paramf(struct pipe_screen *screen, int param)
 195 {
 196    switch (param) {
 197    case PIPE_CAP_MAX_LINE_WIDTH:
 198       /* fall-through */
 199    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 200       return 7.5;
 201
 202    case PIPE_CAP_MAX_POINT_WIDTH:
 203       /* fall-through */
 204    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 205       return 255.0;
 206
 207    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 208       return 4.0;
 209
 210    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 211       return 16.0;
 212
 213    default:
 214       return 0;
 215    }
 216 }
 217
 218 static boolean
 219 brw_is_format_supported(struct pipe_screen *screen,
 220                          enum pipe_format format,
 221                          enum pipe_texture_target target,
 222                          unsigned tex_usage,
 223                          unsigned geom_flags)
 224 {
 225    static const enum pipe_format tex_supported[] = {
 226       PIPE_FORMAT_L8_UNORM,
 227       PIPE_FORMAT_I8_UNORM,
 228       PIPE_FORMAT_A8_UNORM,
 229       PIPE_FORMAT_L16_UNORM,
 230       /*PIPE_FORMAT_I16_UNORM,*/
 231       /*PIPE_FORMAT_A16_UNORM,*/
 232       PIPE_FORMAT_L8A8_UNORM,
 233       PIPE_FORMAT_B5G6R5_UNORM,
 234       PIPE_FORMAT_B5G5R5A1_UNORM,
 235       PIPE_FORMAT_B4G4R4A4_UNORM,
 236       PIPE_FORMAT_B8G8R8X8_UNORM,
 237       PIPE_FORMAT_B8G8R8A8_UNORM,
 238       /* video */
 239       PIPE_FORMAT_UYVY,
 240       PIPE_FORMAT_YUYV,
 241       /* compressed */
 242       /*PIPE_FORMAT_FXT1_RGBA,*/
 243       PIPE_FORMAT_DXT1_RGB,
 244       PIPE_FORMAT_DXT1_RGBA,
 245       PIPE_FORMAT_DXT3_RGBA,
 246       PIPE_FORMAT_DXT5_RGBA,
 247       /* sRGB */
 248       PIPE_FORMAT_A8B8G8R8_SRGB,
 249       PIPE_FORMAT_L8A8_SRGB,
 250       PIPE_FORMAT_L8_SRGB,
 251       PIPE_FORMAT_DXT1_SRGB,
 252       /* depth */
 253       PIPE_FORMAT_Z32_FLOAT,
 254       PIPE_FORMAT_Z24X8_UNORM,
 255       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 256       PIPE_FORMAT_Z16_UNORM,
 257       /* signed */
 258       PIPE_FORMAT_R8G8_SNORM,
 259       PIPE_FORMAT_R8G8B8A8_SNORM,
 260       PIPE_FORMAT_NONE  /* list terminator */
 261    };
 262    static const enum pipe_format render_supported[] = {
 263       PIPE_FORMAT_B8G8R8X8_UNORM,
 264       PIPE_FORMAT_B8G8R8A8_UNORM,
 265       PIPE_FORMAT_B5G6R5_UNORM,
 266       PIPE_FORMAT_NONE  /* list terminator */
 267    };
 268    static const enum pipe_format depth_supported[] = {
 269       PIPE_FORMAT_Z32_FLOAT,
 270       PIPE_FORMAT_Z24X8_UNORM,
 271       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 272       PIPE_FORMAT_Z16_UNORM,
 273       PIPE_FORMAT_NONE  /* list terminator */
 274    };
 275    const enum pipe_format *list;
 276    uint i;
 277
 278    if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL)
 279       list = depth_supported;
 280    else if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
 281       list = render_supported;
 282    else
 283       list = tex_supported;
 284
 285    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 286       if (list[i] == format)
 287          return TRUE;
 288    }
 289
 290    return FALSE;
 291 }
 292
 293
 294 /*
 295  * Fence functions
 296  */
 297
 298
 299 static void
 300 brw_fence_reference(struct pipe_screen *screen,
 301                      struct pipe_fence_handle **ptr,
 302                      struct pipe_fence_handle *fence)
 303 {
 304 }
 305
 306 static int
 307 brw_fence_signalled(struct pipe_screen *screen,
 308                      struct pipe_fence_handle *fence,
 309                      unsigned flags)
 310 {
 311    return 0;                    /* XXX shouldn't this be a boolean? */
 312 }
 313
 314 static int
 315 brw_fence_finish(struct pipe_screen *screen,
 316                  struct pipe_fence_handle *fence,
 317                  unsigned flags)
 318 {
 319    return 0;
 320 }
 321
 322
 323 /*
 324  * Generic functions
 325  */
 326
 327
 328 static void
 329 brw_destroy_screen(struct pipe_screen *screen)
 330 {
 331    struct brw_screen *bscreen = brw_screen(screen);
 332
 333    if (bscreen->sws)
 334       bscreen->sws->destroy(bscreen->sws);
 335
 336    FREE(bscreen);
 337 }
 338
 339 /**
 340  * Create a new brw_screen object
 341  */
 342 struct pipe_screen *
 343 brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
 344 {
 345    struct brw_screen *bscreen;
 346    struct brw_chipset chipset;
 347
 348 #ifdef DEBUG
 349    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 350    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 351    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 352
 353    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 354 #endif
 355
 356    memset(&chipset, 0, sizeof chipset);
 357
 358    chipset.pci_id = pci_id;
 359
 360    switch (pci_id) {
 361    case PCI_CHIP_I965_G:
 362    case PCI_CHIP_I965_Q:
 363    case PCI_CHIP_I965_G_1:
 364    case PCI_CHIP_I946_GZ:
 365    case PCI_CHIP_I965_GM:
 366    case PCI_CHIP_I965_GME:
 367       chipset.is_965 = TRUE;
 368       break;
 369
 370    case PCI_CHIP_GM45_GM:
 371    case PCI_CHIP_IGD_E_G:
 372    case PCI_CHIP_Q45_G:
 373    case PCI_CHIP_G45_G:
 374    case PCI_CHIP_G41_G:
 375    case PCI_CHIP_B43_G:
 376       chipset.is_g4x = TRUE;
 377       break;
 378
 379    case PCI_CHIP_ILD_G:
 380    case PCI_CHIP_ILM_G:
 381       chipset.is_igdng = TRUE;
 382       break;
 383
 384    default:
 385       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 386                    __FUNCTION__, pci_id);
 387       return NULL;
 388    }
 389
 390
 391    bscreen = CALLOC_STRUCT(brw_screen);
 392    if (!bscreen)
 393       return NULL;
 394
 395    bscreen->chipset = chipset;
 396    bscreen->sws = sws;
 397    bscreen->base.winsys = NULL;
 398    bscreen->base.destroy = brw_destroy_screen;
 399    bscreen->base.get_name = brw_get_name;
 400    bscreen->base.get_vendor = brw_get_vendor;
 401    bscreen->base.get_param = brw_get_param;
 402    bscreen->base.get_paramf = brw_get_paramf;
 403    bscreen->base.is_format_supported = brw_is_format_supported;
 404    bscreen->base.context_create = brw_create_context;
 405    bscreen->base.fence_reference = brw_fence_reference;
 406    bscreen->base.fence_signalled = brw_fence_signalled;
 407    bscreen->base.fence_finish = brw_fence_finish;
 408
 409    brw_screen_tex_init(bscreen);
 410    brw_screen_tex_surface_init(bscreen);
 411    brw_screen_buffer_init(bscreen);
 412
 413    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 414
 415
 416    return &bscreen->base;
 417 }