src/gallium/drivers/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 #include "brw_types.h"
  37
  38 /** Number of general purpose registers (VS, WM, etc) */
  39 #define BRW_MAX_GRF 128
  40
  41 /** Number of message register file registers */
  42 #define BRW_MAX_MRF 16
  43
  44
  45 /* Command packets:
  46  */
  47 struct header
  48 {
  49    GLuint length:16;
  50    GLuint opcode:16;
  51 };
  52
  53
  54 union header_union
  55 {
  56    struct header bits;
  57    GLuint dword;
  58 };
  59
  60 struct brw_3d_control
  61 {
  62    struct
  63    {
  64       GLuint length:8;
  65       GLuint notify_enable:1;
  66       GLuint pad:3;
  67       GLuint wc_flush_enable:1;
  68       GLuint depth_stall_enable:1;
  69       GLuint operation:2;
  70       GLuint opcode:16;
  71    } header;
  72
  73    struct
  74    {
  75       GLuint pad:2;
  76       GLuint dest_addr_type:1;
  77       GLuint dest_addr:29;
  78    } dest;
  79
  80    GLuint dword2;
  81    GLuint dword3;
  82 };
  83
  84
  85 struct brw_3d_primitive
  86 {
  87    struct
  88    {
  89       GLuint length:8;
  90       GLuint pad:2;
  91       GLuint topology:5;
  92       GLuint indexed:1;
  93       GLuint opcode:16;
  94    } header;
  95
  96    GLuint verts_per_instance;
  97    GLuint start_vert_location;
  98    GLuint instance_count;
  99    GLuint start_instance_location;
 100    GLuint base_vert_location;
 101 };
 102
 103 /* These seem to be passed around as function args, so it works out
 104  * better to keep them as #defines:
 105  */
 106 #define BRW_FLUSH_READ_CACHE           0x1
 107 #define BRW_FLUSH_STATE_CACHE          0x2
 108 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
 109 #define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
 110
 111 struct brw_mi_flush
 112 {
 113    GLuint flags:4;
 114    GLuint pad:12;
 115    GLuint opcode:16;
 116 };
 117
 118 struct brw_vf_statistics
 119 {
 120    GLuint statistics_enable:1;
 121    GLuint pad:15;
 122    GLuint opcode:16;
 123 };
 124
 125
 126
 127 struct brw_binding_table_pointers
 128 {
 129    struct header header;
 130    GLuint vs;
 131    GLuint gs;
 132    GLuint clp;
 133    GLuint sf;
 134    GLuint wm;
 135 };
 136
 137
 138 struct brw_blend_constant_color
 139 {
 140    struct header header;
 141    GLfloat blend_constant_color[4];
 142 };
 143
 144
 145 struct brw_depthbuffer
 146 {
 147    union header_union header;
 148
 149    union {
 150       struct {
 151          GLuint pitch:18;
 152          GLuint format:3;
 153          GLuint pad:2;
 154          GLuint software_tiled_rendering_mode:2;
 155          GLuint depth_offset_disable:1;
 156          GLuint tile_walk:1;
 157          GLuint tiled_surface:1;
 158          GLuint pad2:1;
 159          GLuint surface_type:3;
 160       } bits;
 161       GLuint dword;
 162    } dword1;
 163
 164    GLuint dword2_base_addr;
 165
 166    union {
 167       struct {
 168          GLuint pad:1;
 169          GLuint mipmap_layout:1;
 170          GLuint lod:4;
 171          GLuint width:13;
 172          GLuint height:13;
 173       } bits;
 174       GLuint dword;
 175    } dword3;
 176
 177    union {
 178       struct {
 179          GLuint pad:10;
 180          GLuint min_array_element:11;
 181          GLuint depth:11;
 182       } bits;
 183       GLuint dword;
 184    } dword4;
 185 };
 186
 187 struct brw_depthbuffer_g4x
 188 {
 189    union header_union header;
 190
 191    union {
 192       struct {
 193          GLuint pitch:18;
 194          GLuint format:3;
 195          GLuint pad:2;
 196          GLuint software_tiled_rendering_mode:2;
 197          GLuint depth_offset_disable:1;
 198          GLuint tile_walk:1;
 199          GLuint tiled_surface:1;
 200          GLuint pad2:1;
 201          GLuint surface_type:3;
 202       } bits;
 203       GLuint dword;
 204    } dword1;
 205
 206    GLuint dword2_base_addr;
 207
 208    union {
 209       struct {
 210          GLuint pad:1;
 211          GLuint mipmap_layout:1;
 212          GLuint lod:4;
 213          GLuint width:13;
 214          GLuint height:13;
 215       } bits;
 216       GLuint dword;
 217    } dword3;
 218
 219    union {
 220       struct {
 221          GLuint pad:10;
 222          GLuint min_array_element:11;
 223          GLuint depth:11;
 224       } bits;
 225       GLuint dword;
 226    } dword4;
 227
 228    union {
 229       struct {
 230          GLuint xoffset:16;
 231          GLuint yoffset:16;
 232       } bits;
 233       GLuint dword;
 234    } dword5;   /* NEW in Integrated Graphics Device */
 235 };
 236
 237 struct brw_drawrect
 238 {
 239    struct header header;
 240    GLuint xmin:16;
 241    GLuint ymin:16;
 242    GLuint xmax:16;
 243    GLuint ymax:16;
 244    GLuint xorg:16;
 245    GLuint yorg:16;
 246 };
 247
 248
 249
 250
 251 struct brw_global_depth_offset_clamp
 252 {
 253    struct header header;
 254    GLfloat depth_offset_clamp;
 255 };
 256
 257 struct brw_indexbuffer
 258 {
 259    union {
 260       struct
 261       {
 262          GLuint length:8;
 263          GLuint index_format:2;
 264          GLuint cut_index_enable:1;
 265          GLuint pad:5;
 266          GLuint opcode:16;
 267       } bits;
 268       GLuint dword;
 269
 270    } header;
 271
 272    GLuint buffer_start;
 273    GLuint buffer_end;
 274 };
 275
 276 /* NEW in Integrated Graphics Device */
 277 struct brw_aa_line_parameters
 278 {
 279    struct header header;
 280
 281    struct {
 282       GLuint aa_coverage_scope:8;
 283       GLuint pad0:8;
 284       GLuint aa_coverage_bias:8;
 285       GLuint pad1:8;
 286    } bits0;
 287
 288    struct {
 289       GLuint aa_coverage_endcap_slope:8;
 290       GLuint pad0:8;
 291       GLuint aa_coverage_endcap_bias:8;
 292       GLuint pad1:8;
 293    } bits1;
 294 };
 295
 296 struct brw_line_stipple
 297 {
 298    struct header header;
 299
 300    struct
 301    {
 302       GLuint pattern:16;
 303       GLuint pad:16;
 304    } bits0;
 305
 306    struct
 307    {
 308       GLuint repeat_count:9;
 309       GLuint pad:7;
 310       GLuint inverse_repeat_count:16;
 311    } bits1;
 312 };
 313
 314
 315 struct brw_pipelined_state_pointers
 316 {
 317    struct header header;
 318
 319    struct {
 320       GLuint pad:5;
 321       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 322    } vs;
 323
 324    struct
 325    {
 326       GLuint enable:1;
 327       GLuint pad:4;
 328       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 329    } gs;
 330
 331    struct
 332    {
 333       GLuint enable:1;
 334       GLuint pad:4;
 335       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 336    } clp;
 337
 338    struct
 339    {
 340       GLuint pad:5;
 341       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 342    } sf;
 343
 344    struct
 345    {
 346       GLuint pad:5;
 347       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 348    } wm;
 349
 350    struct
 351    {
 352       GLuint pad:5;
 353       GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
 354    } cc;
 355 };
 356
 357
 358 struct brw_polygon_stipple_offset
 359 {
 360    struct header header;
 361
 362    struct {
 363       GLuint y_offset:5;
 364       GLuint pad:3;
 365       GLuint x_offset:5;
 366       GLuint pad0:19;
 367    } bits0;
 368 };
 369
 370
 371
 372 struct brw_polygon_stipple
 373 {
 374    struct header header;
 375    GLuint stipple[32];
 376 };
 377
 378
 379
 380 struct brw_pipeline_select
 381 {
 382    struct
 383    {
 384       GLuint pipeline_select:1;
 385       GLuint pad:15;
 386       GLuint opcode:16;
 387    } header;
 388 };
 389
 390
 391 struct brw_pipe_control
 392 {
 393    struct
 394    {
 395       GLuint length:8;
 396       GLuint notify_enable:1;
 397       GLuint texture_cache_flush_enable:1;
 398       GLuint indirect_state_pointers_disable:1;
 399       GLuint instruction_state_cache_flush_enable:1;
 400       GLuint write_cache_flush_enable:1;
 401       GLuint depth_stall_enable:1;
 402       GLuint post_sync_operation:2;
 403
 404       GLuint opcode:16;
 405    } header;
 406
 407    struct
 408    {
 409       GLuint pad:2;
 410       GLuint dest_addr_type:1;
 411       GLuint dest_addr:29;
 412    } bits1;
 413
 414    GLuint data0;
 415    GLuint data1;
 416 };
 417
 418
 419 struct brw_urb_fence
 420 {
 421    struct
 422    {
 423       GLuint length:8;
 424       GLuint vs_realloc:1;
 425       GLuint gs_realloc:1;
 426       GLuint clp_realloc:1;
 427       GLuint sf_realloc:1;
 428       GLuint vfe_realloc:1;
 429       GLuint cs_realloc:1;
 430       GLuint pad:2;
 431       GLuint opcode:16;
 432    } header;
 433
 434    struct
 435    {
 436       GLuint vs_fence:10;
 437       GLuint gs_fence:10;
 438       GLuint clp_fence:10;
 439       GLuint pad:2;
 440    } bits0;
 441
 442    struct
 443    {
 444       GLuint sf_fence:10;
 445       GLuint vf_fence:10;
 446       GLuint cs_fence:11;
 447       GLuint pad:1;
 448    } bits1;
 449 };
 450
 451 struct brw_cs_urb_state
 452 {
 453    struct header header;
 454
 455    struct
 456    {
 457       GLuint nr_urb_entries:3;
 458       GLuint pad:1;
 459       GLuint urb_entry_size:5;
 460       GLuint pad0:23;
 461    } bits0;
 462 };
 463
 464 struct brw_constant_buffer
 465 {
 466    struct
 467    {
 468       GLuint length:8;
 469       GLuint valid:1;
 470       GLuint pad:7;
 471       GLuint opcode:16;
 472    } header;
 473
 474    struct
 475    {
 476       GLuint buffer_length:6;
 477       GLuint buffer_address:26;
 478    } bits0;
 479 };
 480
 481 struct brw_state_base_address
 482 {
 483    struct header header;
 484
 485    struct
 486    {
 487       GLuint modify_enable:1;
 488       GLuint pad:4;
 489       GLuint general_state_address:27;
 490    } bits0;
 491
 492    struct
 493    {
 494       GLuint modify_enable:1;
 495       GLuint pad:4;
 496       GLuint surface_state_address:27;
 497    } bits1;
 498
 499    struct
 500    {
 501       GLuint modify_enable:1;
 502       GLuint pad:4;
 503       GLuint indirect_object_state_address:27;
 504    } bits2;
 505
 506    struct
 507    {
 508       GLuint modify_enable:1;
 509       GLuint pad:11;
 510       GLuint general_state_upper_bound:20;
 511    } bits3;
 512
 513    struct
 514    {
 515       GLuint modify_enable:1;
 516       GLuint pad:11;
 517       GLuint indirect_object_state_upper_bound:20;
 518    } bits4;
 519 };
 520
 521 struct brw_state_prefetch
 522 {
 523    struct header header;
 524
 525    struct
 526    {
 527       GLuint prefetch_count:3;
 528       GLuint pad:3;
 529       GLuint prefetch_pointer:26;
 530    } bits0;
 531 };
 532
 533 struct brw_system_instruction_pointer
 534 {
 535    struct header header;
 536
 537    struct
 538    {
 539       GLuint pad:4;
 540       GLuint system_instruction_pointer:28;
 541    } bits0;
 542 };
 543
 544
 545
 546
 547 /* State structs for the various fixed function units:
 548  */
 549
 550
 551 struct thread0
 552 {
 553    GLuint pad0:1;
 554    GLuint grf_reg_count:3;
 555    GLuint pad1:2;
 556    GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
 557 };
 558
 559 struct thread1
 560 {
 561    GLuint ext_halt_exception_enable:1;
 562    GLuint sw_exception_enable:1;
 563    GLuint mask_stack_exception_enable:1;
 564    GLuint timeout_exception_enable:1;
 565    GLuint illegal_op_exception_enable:1;
 566    GLuint pad0:3;
 567    GLuint depth_coef_urb_read_offset:6; /* WM only */
 568    GLuint pad1:2;
 569    GLuint floating_point_mode:1;
 570    GLuint thread_priority:1;
 571    GLuint binding_table_entry_count:8;
 572    GLuint pad3:5;
 573    GLuint single_program_flow:1;
 574 };
 575
 576 struct thread2
 577 {
 578    GLuint per_thread_scratch_space:4;
 579    GLuint pad0:6;
 580    GLuint scratch_space_base_pointer:22;
 581 };
 582
 583
 584 struct thread3
 585 {
 586    GLuint dispatch_grf_start_reg:4;
 587    GLuint urb_entry_read_offset:6;
 588    GLuint pad0:1;
 589    GLuint urb_entry_read_length:6;
 590    GLuint pad1:1;
 591    GLuint const_urb_entry_read_offset:6;
 592    GLuint pad2:1;
 593    GLuint const_urb_entry_read_length:6;
 594    GLuint pad3:1;
 595 };
 596
 597
 598
 599 struct brw_clip_unit_state
 600 {
 601    struct thread0 thread0;
 602    struct
 603    {
 604       GLuint pad0:7;
 605       GLuint sw_exception_enable:1;
 606       GLuint pad1:3;
 607       GLuint mask_stack_exception_enable:1;
 608       GLuint pad2:1;
 609       GLuint illegal_op_exception_enable:1;
 610       GLuint pad3:2;
 611       GLuint floating_point_mode:1;
 612       GLuint thread_priority:1;
 613       GLuint binding_table_entry_count:8;
 614       GLuint pad4:5;
 615       GLuint single_program_flow:1;
 616    } thread1;
 617
 618    struct thread2 thread2;
 619    struct thread3 thread3;
 620
 621    struct
 622    {
 623       GLuint pad0:9;
 624       GLuint gs_output_stats:1; /* not always */
 625       GLuint stats_enable:1;
 626       GLuint nr_urb_entries:7;
 627       GLuint pad1:1;
 628       GLuint urb_entry_allocation_size:5;
 629       GLuint pad2:1;
 630       GLuint max_threads:5;     /* may be less */
 631       GLuint pad3:2;
 632    } thread4;
 633
 634    struct
 635    {
 636       GLuint pad0:13;
 637       GLuint clip_mode:3;
 638       GLuint userclip_enable_flags:8;
 639       GLuint userclip_must_clip:1;
 640       GLuint negative_w_clip_test:1;
 641       GLuint guard_band_enable:1;
 642       GLuint viewport_z_clip_enable:1;
 643       GLuint viewport_xy_clip_enable:1;
 644       GLuint vertex_position_space:1;
 645       GLuint api_mode:1;
 646       GLuint pad2:1;
 647    } clip5;
 648
 649    struct
 650    {
 651       GLuint pad0:5;
 652       GLuint clipper_viewport_state_ptr:27;
 653    } clip6;
 654
 655
 656    GLfloat viewport_xmin;
 657    GLfloat viewport_xmax;
 658    GLfloat viewport_ymin;
 659    GLfloat viewport_ymax;
 660 };
 661
 662
 663
 664 struct brw_cc_unit_state
 665 {
 666    struct brw_cc0
 667    {
 668       GLuint pad0:3;
 669       GLuint bf_stencil_pass_depth_pass_op:3;
 670       GLuint bf_stencil_pass_depth_fail_op:3;
 671       GLuint bf_stencil_fail_op:3;
 672       GLuint bf_stencil_func:3;
 673       GLuint bf_stencil_enable:1;
 674       GLuint pad1:2;
 675       GLuint stencil_write_enable:1;
 676       GLuint stencil_pass_depth_pass_op:3;
 677       GLuint stencil_pass_depth_fail_op:3;
 678       GLuint stencil_fail_op:3;
 679       GLuint stencil_func:3;
 680       GLuint stencil_enable:1;
 681    } cc0;
 682
 683
 684    struct brw_cc1
 685    {
 686       GLuint bf_stencil_ref:8;
 687       GLuint stencil_write_mask:8;
 688       GLuint stencil_test_mask:8;
 689       GLuint stencil_ref:8;
 690    } cc1;
 691
 692
 693    struct brw_cc2
 694    {
 695       GLuint logicop_enable:1;
 696       GLuint pad0:10;
 697       GLuint depth_write_enable:1;
 698       GLuint depth_test_function:3;
 699       GLuint depth_test:1;
 700       GLuint bf_stencil_write_mask:8;
 701       GLuint bf_stencil_test_mask:8;
 702    } cc2;
 703
 704
 705    struct brw_cc3
 706    {
 707       GLuint pad0:8;
 708       GLuint alpha_test_func:3;
 709       GLuint alpha_test:1;
 710       GLuint blend_enable:1;
 711       GLuint ia_blend_enable:1;
 712       GLuint pad1:1;
 713       GLuint alpha_test_format:1;
 714       GLuint pad2:16;
 715    } cc3;
 716
 717    struct brw_cc4
 718    {
 719       GLuint pad0:5;
 720       GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 721    } cc4;
 722
 723    struct brw_cc5
 724    {
 725       GLuint pad0:2;
 726       GLuint ia_dest_blend_factor:5;
 727       GLuint ia_src_blend_factor:5;
 728       GLuint ia_blend_function:3;
 729       GLuint statistics_enable:1;
 730       GLuint logicop_func:4;
 731       GLuint pad1:11;
 732       GLuint dither_enable:1;
 733    } cc5;
 734
 735    struct brw_cc6
 736    {
 737       GLuint clamp_post_alpha_blend:1;
 738       GLuint clamp_pre_alpha_blend:1;
 739       GLuint clamp_range:2;
 740       GLuint pad0:11;
 741       GLuint y_dither_offset:2;
 742       GLuint x_dither_offset:2;
 743       GLuint dest_blend_factor:5;
 744       GLuint src_blend_factor:5;
 745       GLuint blend_function:3;
 746    } cc6;
 747
 748    struct brw_cc7 {
 749       union {
 750          GLfloat f;
 751          GLubyte ub[4];
 752       } alpha_ref;
 753    } cc7;
 754 };
 755
 756
 757
 758 struct brw_sf_unit_state
 759 {
 760    struct thread0 thread0;
 761    struct thread1 thread1;
 762    struct thread2 thread2;
 763    struct thread3 thread3;
 764
 765    struct
 766    {
 767       GLuint pad0:10;
 768       GLuint stats_enable:1;
 769       GLuint nr_urb_entries:7;
 770       GLuint pad1:1;
 771       GLuint urb_entry_allocation_size:5;
 772       GLuint pad2:1;
 773       GLuint max_threads:6;
 774       GLuint pad3:1;
 775    } thread4;
 776
 777    struct
 778    {
 779       GLuint front_winding:1;
 780       GLuint viewport_transform:1;
 781       GLuint pad0:3;
 782       GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 783    } sf5;
 784
 785    struct
 786    {
 787       GLuint pad0:9;
 788       GLuint dest_org_vbias:4;
 789       GLuint dest_org_hbias:4;
 790       GLuint scissor:1;
 791       GLuint disable_2x2_trifilter:1;
 792       GLuint disable_zero_pix_trifilter:1;
 793       GLuint point_rast_rule:2;
 794       GLuint line_endcap_aa_region_width:2;
 795       GLuint line_width:4;
 796       GLuint fast_scissor_disable:1;
 797       GLuint cull_mode:2;
 798       GLuint aa_enable:1;
 799    } sf6;
 800
 801    struct
 802    {
 803       GLuint point_size:11;
 804       GLuint use_point_size_state:1;
 805       GLuint subpixel_precision:1;
 806       GLuint sprite_point:1;
 807       GLuint pad0:10;
 808       GLuint aa_line_distance_mode:1;
 809       GLuint trifan_pv:2;
 810       GLuint linestrip_pv:2;
 811       GLuint tristrip_pv:2;
 812       GLuint line_last_pixel_enable:1;
 813    } sf7;
 814
 815 };
 816
 817
 818 struct brw_gs_unit_state
 819 {
 820    struct thread0 thread0;
 821    struct thread1 thread1;
 822    struct thread2 thread2;
 823    struct thread3 thread3;
 824
 825    struct
 826    {
 827       GLuint pad0:8;
 828       GLuint rendering_enable:1; /* for IGDNG */
 829       GLuint pad4:1;
 830       GLuint stats_enable:1;
 831       GLuint nr_urb_entries:7;
 832       GLuint pad1:1;
 833       GLuint urb_entry_allocation_size:5;
 834       GLuint pad2:1;
 835       GLuint max_threads:5;
 836       GLuint pad3:2;
 837    } thread4;
 838
 839    struct
 840    {
 841       GLuint sampler_count:3;
 842       GLuint pad0:2;
 843       GLuint sampler_state_pointer:27;
 844    } gs5;
 845
 846
 847    struct
 848    {
 849       GLuint max_vp_index:4;
 850       GLuint pad0:12;
 851       GLuint svbi_post_inc_value:10;
 852       GLuint pad1:1;
 853       GLuint svbi_post_inc_enable:1;
 854       GLuint svbi_payload:1;
 855       GLuint discard_adjaceny:1;
 856       GLuint reorder_enable:1;
 857       GLuint pad2:1;
 858    } gs6;
 859 };
 860
 861
 862 struct brw_vs_unit_state
 863 {
 864    struct thread0 thread0;
 865    struct thread1 thread1;
 866    struct thread2 thread2;
 867    struct thread3 thread3;
 868
 869    struct
 870    {
 871       GLuint pad0:10;
 872       GLuint stats_enable:1;
 873       GLuint nr_urb_entries:7;
 874       GLuint pad1:1;
 875       GLuint urb_entry_allocation_size:5;
 876       GLuint pad2:1;
 877       GLuint max_threads:6;
 878       GLuint pad3:1;
 879    } thread4;
 880
 881    struct
 882    {
 883       GLuint sampler_count:3;
 884       GLuint pad0:2;
 885       GLuint sampler_state_pointer:27;
 886    } vs5;
 887
 888    struct
 889    {
 890       GLuint vs_enable:1;
 891       GLuint vert_cache_disable:1;
 892       GLuint pad0:30;
 893    } vs6;
 894 };
 895
 896
 897 struct brw_wm_unit_state
 898 {
 899    struct thread0 thread0;
 900    struct thread1 thread1;
 901    struct thread2 thread2;
 902    struct thread3 thread3;
 903
 904    struct {
 905       GLuint stats_enable:1;
 906       GLuint depth_buffer_clear:1;
 907       GLuint sampler_count:3;
 908       GLuint sampler_state_pointer:27;
 909    } wm4;
 910
 911    struct
 912    {
 913       GLuint enable_8_pix:1;
 914       GLuint enable_16_pix:1;
 915       GLuint enable_32_pix:1;
 916       GLuint enable_con_32_pix:1;
 917       GLuint enable_con_64_pix:1;
 918       GLuint pad0:5;
 919       GLuint legacy_global_depth_bias:1;
 920       GLuint line_stipple:1;
 921       GLuint depth_offset:1;
 922       GLuint polygon_stipple:1;
 923       GLuint line_aa_region_width:2;
 924       GLuint line_endcap_aa_region_width:2;
 925       GLuint early_depth_test:1;
 926       GLuint thread_dispatch_enable:1;
 927       GLuint program_uses_depth:1;
 928       GLuint program_computes_depth:1;
 929       GLuint program_uses_killpixel:1;
 930       GLuint legacy_line_rast: 1;
 931       GLuint transposed_urb_read_enable:1;
 932       GLuint max_threads:7;
 933    } wm5;
 934
 935    GLfloat global_depth_offset_constant;
 936    GLfloat global_depth_offset_scale;
 937
 938    /* for IGDNG only */
 939    struct {
 940       GLuint pad0:1;
 941       GLuint grf_reg_count_1:3;
 942       GLuint pad1:2;
 943       GLuint kernel_start_pointer_1:26;
 944    } wm8;
 945
 946    struct {
 947       GLuint pad0:1;
 948       GLuint grf_reg_count_2:3;
 949       GLuint pad1:2;
 950       GLuint kernel_start_pointer_2:26;
 951    } wm9;
 952
 953    struct {
 954       GLuint pad0:1;
 955       GLuint grf_reg_count_3:3;
 956       GLuint pad1:2;
 957       GLuint kernel_start_pointer_3:26;
 958    } wm10;
 959 };
 960
 961 struct brw_sampler_default_color {
 962    GLfloat color[4];
 963 };
 964
 965 struct brw_sampler_state
 966 {
 967
 968    struct brw_ss0
 969    {
 970       GLuint shadow_function:3;
 971       GLuint lod_bias:11;
 972       GLuint min_filter:3;
 973       GLuint mag_filter:3;
 974       GLuint mip_filter:2;
 975       GLuint base_level:5;
 976       GLuint pad:1;
 977       GLuint lod_preclamp:1;
 978       GLuint default_color_mode:1;
 979       GLuint pad0:1;
 980       GLuint disable:1;
 981    } ss0;
 982
 983    struct brw_ss1
 984    {
 985       GLuint r_wrap_mode:3;
 986       GLuint t_wrap_mode:3;
 987       GLuint s_wrap_mode:3;
 988       GLuint pad:3;
 989       GLuint max_lod:10;
 990       GLuint min_lod:10;
 991    } ss1;
 992
 993
 994    struct brw_ss2
 995    {
 996       GLuint pad:5;
 997       GLuint default_color_pointer:27;
 998    } ss2;
 999
1000    struct brw_ss3
1001    {
1002       GLuint pad:19;
1003       GLuint max_aniso:3;
1004       GLuint chroma_key_mode:1;
1005       GLuint chroma_key_index:2;
1006       GLuint chroma_key_enable:1;
1007       GLuint monochrome_filter_width:3;
1008       GLuint monochrome_filter_height:3;
1009    } ss3;
1010 };
1011
1012
1013 struct brw_clipper_viewport
1014 {
1015    GLfloat xmin;
1016    GLfloat xmax;
1017    GLfloat ymin;
1018    GLfloat ymax;
1019 };
1020
1021 struct brw_cc_viewport
1022 {
1023    GLfloat min_depth;
1024    GLfloat max_depth;
1025 };
1026
1027 struct brw_sf_viewport
1028 {
1029    struct {
1030       GLfloat m00;
1031       GLfloat m11;
1032       GLfloat m22;
1033       GLfloat m30;
1034       GLfloat m31;
1035       GLfloat m32;
1036    } viewport;
1037
1038    /* scissor coordinates are inclusive */
1039    struct {
1040       GLshort xmin;
1041       GLshort ymin;
1042       GLshort xmax;
1043       GLshort ymax;
1044    } scissor;
1045 };
1046
1047 /* Documented in the subsystem/shared-functions/sampler chapter...
1048  */
1049 struct brw_surface_state
1050 {
1051    struct brw_surf_ss0 {
1052       GLuint cube_pos_z:1;
1053       GLuint cube_neg_z:1;
1054       GLuint cube_pos_y:1;
1055       GLuint cube_neg_y:1;
1056       GLuint cube_pos_x:1;
1057       GLuint cube_neg_x:1;
1058       GLuint pad:4;
1059       GLuint mipmap_layout_mode:1;
1060       GLuint vert_line_stride_ofs:1;
1061       GLuint vert_line_stride:1;
1062       GLuint color_blend:1;
1063       GLuint writedisable_blue:1;
1064       GLuint writedisable_green:1;
1065       GLuint writedisable_red:1;
1066       GLuint writedisable_alpha:1;
1067       GLuint surface_format:9;     /**< BRW_SURFACEFORMAT_x */
1068       GLuint data_return_format:1;
1069       GLuint pad0:1;
1070       GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
1071    } ss0;
1072
1073    struct brw_surf_ss1 {
1074       GLuint base_addr;
1075    } ss1;
1076
1077    struct brw_surf_ss2 {
1078       GLuint pad:2;
1079       GLuint mip_count:4;
1080       GLuint width:13;
1081       GLuint height:13;
1082    } ss2;
1083
1084    struct brw_surf_ss3 {
1085       GLuint tile_walk:1;
1086       GLuint tiled_surface:1;
1087       GLuint pad:1;
1088       GLuint pitch:18;
1089       GLuint depth:11;
1090    } ss3;
1091
1092    struct brw_surf_ss4 {
1093       GLuint multisample_position_palette_index:3;
1094       GLuint pad1:1;
1095       GLuint num_multisamples:3;
1096       GLuint pad0:1;
1097       GLuint render_target_view_extent:9;
1098       GLuint min_array_elt:11;
1099       GLuint min_lod:4;
1100    } ss4;
1101
1102    struct brw_surf_ss5 {
1103       GLuint pad1:16;
1104       GLuint llc_mapping:1;
1105       GLuint mlc_mapping:1;
1106       GLuint gfdt:1;
1107       GLuint gfdt_src:1;
1108       GLuint y_offset:4;
1109       GLuint pad0:1;
1110       GLuint x_offset:7;
1111    } ss5;   /* New in G4X */
1112
1113 };
1114
1115
1116
1117 struct brw_vertex_buffer_state
1118 {
1119    struct {
1120       GLuint pitch:11;
1121       GLuint pad:15;
1122       GLuint access_type:1;
1123       GLuint vb_index:5;
1124    } vb0;
1125
1126    GLuint start_addr;
1127    GLuint max_index;
1128 #if 1
1129    GLuint instance_data_step_rate; /* not included for sequential/random vertices? */
1130 #endif
1131 };
1132
1133 #define BRW_VBP_MAX 17
1134
1135 struct brw_vb_array_state {
1136    struct header header;
1137    struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
1138 };
1139
1140
1141 struct brw_vertex_element_state
1142 {
1143    struct
1144    {
1145       GLuint src_offset:11;
1146       GLuint pad:5;
1147       GLuint src_format:9;
1148       GLuint pad0:1;
1149       GLuint valid:1;
1150       GLuint vertex_buffer_index:5;
1151    } ve0;
1152
1153    struct
1154    {
1155       GLuint dst_offset:8;
1156       GLuint pad:8;
1157       GLuint vfcomponent3:4;
1158       GLuint vfcomponent2:4;
1159       GLuint vfcomponent1:4;
1160       GLuint vfcomponent0:4;
1161    } ve1;
1162 };
1163
1164 #define BRW_VEP_MAX 18
1165
1166 struct brw_vertex_element_packet {
1167    struct header header;
1168    struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1169 };
1170
1171
1172 struct brw_urb_immediate {
1173    GLuint opcode:4;
1174    GLuint offset:6;
1175    GLuint swizzle_control:2;
1176    GLuint pad:1;
1177    GLuint allocate:1;
1178    GLuint used:1;
1179    GLuint complete:1;
1180    GLuint response_length:4;
1181    GLuint msg_length:4;
1182    GLuint msg_target:4;
1183    GLuint pad1:3;
1184    GLuint end_of_thread:1;
1185 };
1186
1187 /* Instruction format for the execution units:
1188  */
1189
1190 struct brw_instruction
1191 {
1192    struct
1193    {
1194       GLuint opcode:7;
1195       GLuint pad:1;
1196       GLuint access_mode:1;
1197       GLuint mask_control:1;
1198       GLuint dependency_control:2;
1199       GLuint compression_control:2;
1200       GLuint thread_control:2;
1201       GLuint predicate_control:4;
1202       GLuint predicate_inverse:1;
1203       GLuint execution_size:3;
1204       GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
1205       GLuint pad0:2;
1206       GLuint debug_control:1;
1207       GLuint saturate:1;
1208    } header;
1209
1210    union {
1211       struct
1212       {
1213          GLuint dest_reg_file:2;
1214          GLuint dest_reg_type:3;
1215          GLuint src0_reg_file:2;
1216          GLuint src0_reg_type:3;
1217          GLuint src1_reg_file:2;
1218          GLuint src1_reg_type:3;
1219          GLuint pad:1;
1220          GLuint dest_subreg_nr:5;
1221          GLuint dest_reg_nr:8;
1222          GLuint dest_horiz_stride:2;
1223          GLuint dest_address_mode:1;
1224       } da1;
1225
1226       struct
1227       {
1228          GLuint dest_reg_file:2;
1229          GLuint dest_reg_type:3;
1230          GLuint src0_reg_file:2;
1231          GLuint src0_reg_type:3;
1232          GLuint src1_reg_file:2;        /* 0x00000c00 */
1233          GLuint src1_reg_type:3;        /* 0x00007000 */
1234          GLuint pad:1;
1235          GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
1236          GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
1237          GLuint dest_horiz_stride:2;
1238          GLuint dest_address_mode:1;
1239       } ia1;
1240
1241       struct
1242       {
1243          GLuint dest_reg_file:2;
1244          GLuint dest_reg_type:3;
1245          GLuint src0_reg_file:2;
1246          GLuint src0_reg_type:3;
1247          GLuint src1_reg_file:2;
1248          GLuint src1_reg_type:3;
1249          GLuint pad:1;
1250          GLuint dest_writemask:4;
1251          GLuint dest_subreg_nr:1;
1252          GLuint dest_reg_nr:8;
1253          GLuint pad1:2;
1254          GLuint dest_address_mode:1;
1255       } da16;
1256
1257       struct
1258       {
1259          GLuint dest_reg_file:2;
1260          GLuint dest_reg_type:3;
1261          GLuint src0_reg_file:2;
1262          GLuint src0_reg_type:3;
1263          GLuint pad0:6;
1264          GLuint dest_writemask:4;
1265          GLint dest_indirect_offset:6;
1266          GLuint dest_subreg_nr:3;
1267          GLuint pad1:2;
1268          GLuint dest_address_mode:1;
1269       } ia16;
1270    } bits1;
1271
1272
1273    union {
1274       struct
1275       {
1276          GLuint src0_subreg_nr:5;
1277          GLuint src0_reg_nr:8;
1278          GLuint src0_abs:1;
1279          GLuint src0_negate:1;
1280          GLuint src0_address_mode:1;
1281          GLuint src0_horiz_stride:2;
1282          GLuint src0_width:3;
1283          GLuint src0_vert_stride:4;
1284          GLuint flag_reg_nr:1;
1285          GLuint pad:6;
1286       } da1;
1287
1288       struct
1289       {
1290          GLint src0_indirect_offset:10;
1291          GLuint src0_subreg_nr:3;
1292          GLuint src0_abs:1;
1293          GLuint src0_negate:1;
1294          GLuint src0_address_mode:1;
1295          GLuint src0_horiz_stride:2;
1296          GLuint src0_width:3;
1297          GLuint src0_vert_stride:4;
1298          GLuint flag_reg_nr:1;
1299          GLuint pad:6;
1300       } ia1;
1301
1302       struct
1303       {
1304          GLuint src0_swz_x:2;
1305          GLuint src0_swz_y:2;
1306          GLuint src0_subreg_nr:1;
1307          GLuint src0_reg_nr:8;
1308          GLuint src0_abs:1;
1309          GLuint src0_negate:1;
1310          GLuint src0_address_mode:1;
1311          GLuint src0_swz_z:2;
1312          GLuint src0_swz_w:2;
1313          GLuint pad0:1;
1314          GLuint src0_vert_stride:4;
1315          GLuint flag_reg_nr:1;
1316          GLuint pad1:6;
1317       } da16;
1318
1319       struct
1320       {
1321          GLuint src0_swz_x:2;
1322          GLuint src0_swz_y:2;
1323          GLint src0_indirect_offset:6;
1324          GLuint src0_subreg_nr:3;
1325          GLuint src0_abs:1;
1326          GLuint src0_negate:1;
1327          GLuint src0_address_mode:1;
1328          GLuint src0_swz_z:2;
1329          GLuint src0_swz_w:2;
1330          GLuint pad0:1;
1331          GLuint src0_vert_stride:4;
1332          GLuint flag_reg_nr:1;
1333          GLuint pad1:6;
1334       } ia16;
1335
1336        struct
1337        {
1338            GLuint pad:26;
1339            GLuint end_of_thread:1;
1340            GLuint pad1:1;
1341            GLuint sfid:4;
1342        } send_igdng;  /* for IGDNG only */
1343
1344    } bits2;
1345
1346    union
1347    {
1348       struct
1349       {
1350          GLuint src1_subreg_nr:5;
1351          GLuint src1_reg_nr:8;
1352          GLuint src1_abs:1;
1353          GLuint src1_negate:1;
1354          GLuint src1_address_mode:1;
1355          GLuint src1_horiz_stride:2;
1356          GLuint src1_width:3;
1357          GLuint src1_vert_stride:4;
1358          GLuint pad0:7;
1359       } da1;
1360
1361       struct
1362       {
1363          GLuint src1_swz_x:2;
1364          GLuint src1_swz_y:2;
1365          GLuint src1_subreg_nr:1;
1366          GLuint src1_reg_nr:8;
1367          GLuint src1_abs:1;
1368          GLuint src1_negate:1;
1369          GLuint src1_address_mode:1;
1370          GLuint src1_swz_z:2;
1371          GLuint src1_swz_w:2;
1372          GLuint pad1:1;
1373          GLuint src1_vert_stride:4;
1374          GLuint pad2:7;
1375       } da16;
1376
1377       struct
1378       {
1379          GLint  src1_indirect_offset:10;
1380          GLuint src1_subreg_nr:3;
1381          GLuint src1_abs:1;
1382          GLuint src1_negate:1;
1383          GLuint src1_address_mode:1;
1384          GLuint src1_horiz_stride:2;
1385          GLuint src1_width:3;
1386          GLuint src1_vert_stride:4;
1387          GLuint flag_reg_nr:1;
1388          GLuint pad1:6;
1389       } ia1;
1390
1391       struct
1392       {
1393          GLuint src1_swz_x:2;
1394          GLuint src1_swz_y:2;
1395          GLint  src1_indirect_offset:6;
1396          GLuint src1_subreg_nr:3;
1397          GLuint src1_abs:1;
1398          GLuint src1_negate:1;
1399          GLuint pad0:1;
1400          GLuint src1_swz_z:2;
1401          GLuint src1_swz_w:2;
1402          GLuint pad1:1;
1403          GLuint src1_vert_stride:4;
1404          GLuint flag_reg_nr:1;
1405          GLuint pad2:6;
1406       } ia16;
1407
1408
1409       struct
1410       {
1411          GLint  jump_count:16;  /* note: signed */
1412          GLuint  pop_count:4;
1413          GLuint  pad0:12;
1414       } if_else;
1415
1416       struct {
1417          GLuint function:4;
1418          GLuint int_type:1;
1419          GLuint precision:1;
1420          GLuint saturate:1;
1421          GLuint data_type:1;
1422          GLuint pad0:8;
1423          GLuint response_length:4;
1424          GLuint msg_length:4;
1425          GLuint msg_target:4;
1426          GLuint pad1:3;
1427          GLuint end_of_thread:1;
1428       } math;
1429
1430       struct {
1431          GLuint function:4;
1432          GLuint int_type:1;
1433          GLuint precision:1;
1434          GLuint saturate:1;
1435          GLuint data_type:1;
1436          GLuint snapshot:1;
1437          GLuint pad0:10;
1438          GLuint header_present:1;
1439          GLuint response_length:5;
1440          GLuint msg_length:4;
1441          GLuint pad1:2;
1442          GLuint end_of_thread:1;
1443       } math_igdng;
1444
1445       struct {
1446          GLuint binding_table_index:8;
1447          GLuint sampler:4;
1448          GLuint return_format:2;
1449          GLuint msg_type:2;
1450          GLuint response_length:4;
1451          GLuint msg_length:4;
1452          GLuint msg_target:4;
1453          GLuint pad1:3;
1454          GLuint end_of_thread:1;
1455       } sampler;
1456
1457       struct {
1458          GLuint binding_table_index:8;
1459          GLuint sampler:4;
1460          GLuint msg_type:4;
1461          GLuint response_length:4;
1462          GLuint msg_length:4;
1463          GLuint msg_target:4;
1464          GLuint pad1:3;
1465          GLuint end_of_thread:1;
1466       } sampler_g4x;
1467
1468       struct {
1469          GLuint binding_table_index:8;
1470          GLuint sampler:4;
1471          GLuint msg_type:4;
1472          GLuint simd_mode:2;
1473          GLuint pad0:1;
1474          GLuint header_present:1;
1475          GLuint response_length:5;
1476          GLuint msg_length:4;
1477          GLuint pad1:2;
1478          GLuint end_of_thread:1;
1479       } sampler_igdng;
1480
1481       struct brw_urb_immediate urb;
1482
1483       struct {
1484          GLuint opcode:4;
1485          GLuint offset:6;
1486          GLuint swizzle_control:2;
1487          GLuint pad:1;
1488          GLuint allocate:1;
1489          GLuint used:1;
1490          GLuint complete:1;
1491          GLuint pad0:3;
1492          GLuint header_present:1;
1493          GLuint response_length:5;
1494          GLuint msg_length:4;
1495          GLuint pad1:2;
1496          GLuint end_of_thread:1;
1497       } urb_igdng;
1498
1499       struct {
1500          GLuint binding_table_index:8;
1501          GLuint msg_control:4;
1502          GLuint msg_type:2;
1503          GLuint target_cache:2;
1504          GLuint response_length:4;
1505          GLuint msg_length:4;
1506          GLuint msg_target:4;
1507          GLuint pad1:3;
1508          GLuint end_of_thread:1;
1509       } dp_read;
1510
1511       struct {
1512          GLuint binding_table_index:8;
1513          GLuint msg_control:3;
1514          GLuint msg_type:3;
1515          GLuint target_cache:2;
1516          GLuint pad0:3;
1517          GLuint header_present:1;
1518          GLuint response_length:5;
1519          GLuint msg_length:4;
1520          GLuint pad1:2;
1521          GLuint end_of_thread:1;
1522       } dp_read_igdng;
1523
1524       struct {
1525          GLuint binding_table_index:8;
1526          GLuint msg_control:3;
1527          GLuint pixel_scoreboard_clear:1;
1528          GLuint msg_type:3;
1529          GLuint send_commit_msg:1;
1530          GLuint response_length:4;
1531          GLuint msg_length:4;
1532          GLuint msg_target:4;
1533          GLuint pad1:3;
1534          GLuint end_of_thread:1;
1535       } dp_write;
1536
1537       struct {
1538          GLuint binding_table_index:8;
1539          GLuint msg_control:3;
1540          GLuint pixel_scoreboard_clear:1;
1541          GLuint msg_type:3;
1542          GLuint send_commit_msg:1;
1543          GLuint pad0:3;
1544          GLuint header_present:1;
1545          GLuint response_length:5;
1546          GLuint msg_length:4;
1547          GLuint pad1:2;
1548          GLuint end_of_thread:1;
1549       } dp_write_igdng;
1550
1551       struct {
1552          GLuint pad:16;
1553          GLuint response_length:4;
1554          GLuint msg_length:4;
1555          GLuint msg_target:4;
1556          GLuint pad1:3;
1557          GLuint end_of_thread:1;
1558       } generic;
1559
1560       struct {
1561          GLuint pad:19;
1562          GLuint header_present:1;
1563          GLuint response_length:5;
1564          GLuint msg_length:4;
1565          GLuint pad1:2;
1566          GLuint end_of_thread:1;
1567       } generic_igdng;
1568
1569       GLint d;
1570       GLuint ud;
1571       float f;
1572    } bits3;
1573 };
1574
1575
1576 #endif