src/gallium/drivers/i965simple/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 #include "pipe/p_compiler.h"
  37
  38 /* Command packets:
  39  */
  40 struct header
  41 {
  42    unsigned length:16;
  43    unsigned opcode:16;
  44 };
  45
  46
  47 union header_union
  48 {
  49    struct header bits;
  50    unsigned dword;
  51 };
  52
  53 struct brw_3d_control
  54 {
  55    struct
  56    {
  57       unsigned length:8;
  58       unsigned notify_enable:1;
  59       unsigned pad:3;
  60       unsigned wc_flush_enable:1;
  61       unsigned depth_stall_enable:1;
  62       unsigned operation:2;
  63       unsigned opcode:16;
  64    } header;
  65
  66    struct
  67    {
  68       unsigned pad:2;
  69       unsigned dest_addr_type:1;
  70       unsigned dest_addr:29;
  71    } dest;
  72
  73    unsigned dword2;
  74    unsigned dword3;
  75 };
  76
  77
  78 struct brw_3d_primitive
  79 {
  80    struct
  81    {
  82       unsigned length:8;
  83       unsigned pad:2;
  84       unsigned topology:5;
  85       unsigned indexed:1;
  86       unsigned opcode:16;
  87    } header;
  88
  89    unsigned verts_per_instance;
  90    unsigned start_vert_location;
  91    unsigned instance_count;
  92    unsigned start_instance_location;
  93    unsigned base_vert_location;
  94 };
  95
  96 /* These seem to be passed around as function args, so it works out
  97  * better to keep them as #defines:
  98  */
  99 #define BRW_FLUSH_READ_CACHE           0x1
 100 #define BRW_FLUSH_STATE_CACHE          0x2
 101 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
 102 #define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
 103
 104 struct brw_mi_flush
 105 {
 106    unsigned flags:4;
 107    unsigned pad:12;
 108    unsigned opcode:16;
 109 };
 110
 111 struct brw_vf_statistics
 112 {
 113    unsigned statistics_enable:1;
 114    unsigned pad:15;
 115    unsigned opcode:16;
 116 };
 117
 118
 119
 120 struct brw_binding_table_pointers
 121 {
 122    struct header header;
 123    unsigned vs;
 124    unsigned gs;
 125    unsigned clp;
 126    unsigned sf;
 127    unsigned wm;
 128 };
 129
 130
 131 struct brw_blend_constant_color
 132 {
 133    struct header header;
 134    float blend_constant_color[4];
 135 };
 136
 137
 138 struct brw_depthbuffer
 139 {
 140    union header_union header;
 141
 142    union {
 143       struct {
 144          unsigned pitch:18;
 145          unsigned format:3;
 146          unsigned pad:4;
 147          unsigned depth_offset_disable:1;
 148          unsigned tile_walk:1;
 149          unsigned tiled_surface:1;
 150          unsigned pad2:1;
 151          unsigned surface_type:3;
 152       } bits;
 153       unsigned dword;
 154    } dword1;
 155
 156    unsigned dword2_base_addr;
 157
 158    union {
 159       struct {
 160          unsigned pad:1;
 161          unsigned mipmap_layout:1;
 162          unsigned lod:4;
 163          unsigned width:13;
 164          unsigned height:13;
 165       } bits;
 166       unsigned dword;
 167    } dword3;
 168
 169    union {
 170       struct {
 171          unsigned pad:12;
 172          unsigned min_array_element:9;
 173          unsigned depth:11;
 174       } bits;
 175       unsigned dword;
 176    } dword4;
 177 };
 178
 179 struct brw_drawrect
 180 {
 181    struct header header;
 182    unsigned xmin:16;
 183    unsigned ymin:16;
 184    unsigned xmax:16;
 185    unsigned ymax:16;
 186    unsigned xorg:16;
 187    unsigned yorg:16;
 188 };
 189
 190
 191
 192
 193 struct brw_global_depth_offset_clamp
 194 {
 195    struct header header;
 196    float depth_offset_clamp;
 197 };
 198
 199 struct brw_indexbuffer
 200 {
 201    union {
 202       struct
 203       {
 204          unsigned length:8;
 205          unsigned index_format:2;
 206          unsigned cut_index_enable:1;
 207          unsigned pad:5;
 208          unsigned opcode:16;
 209       } bits;
 210       unsigned dword;
 211
 212    } header;
 213
 214    unsigned buffer_start;
 215    unsigned buffer_end;
 216 };
 217
 218
 219 struct brw_line_stipple
 220 {
 221    struct header header;
 222
 223    struct
 224    {
 225       unsigned pattern:16;
 226       unsigned pad:16;
 227    } bits0;
 228
 229    struct
 230    {
 231       unsigned repeat_count:9;
 232       unsigned pad:7;
 233       unsigned inverse_repeat_count:16;
 234    } bits1;
 235 };
 236
 237
 238 struct brw_pipelined_state_pointers
 239 {
 240    struct header header;
 241
 242    struct {
 243       unsigned pad:5;
 244       unsigned offset:27;
 245    } vs;
 246
 247    struct
 248    {
 249       unsigned enable:1;
 250       unsigned pad:4;
 251       unsigned offset:27;
 252    } gs;
 253
 254    struct
 255    {
 256       unsigned enable:1;
 257       unsigned pad:4;
 258       unsigned offset:27;
 259    } clp;
 260
 261    struct
 262    {
 263       unsigned pad:5;
 264       unsigned offset:27;
 265    } sf;
 266
 267    struct
 268    {
 269       unsigned pad:5;
 270       unsigned offset:27;
 271    } wm;
 272
 273    struct
 274    {
 275       unsigned pad:5;
 276       unsigned offset:27; /* KW: check me! */
 277    } cc;
 278 };
 279
 280
 281 struct brw_polygon_stipple_offset
 282 {
 283    struct header header;
 284
 285    struct {
 286       unsigned y_offset:5;
 287       unsigned pad:3;
 288       unsigned x_offset:5;
 289       unsigned pad0:19;
 290    } bits0;
 291 };
 292
 293
 294
 295 struct brw_polygon_stipple
 296 {
 297    struct header header;
 298    unsigned stipple[32];
 299 };
 300
 301
 302
 303 struct brw_pipeline_select
 304 {
 305    struct
 306    {
 307       unsigned pipeline_select:1;
 308       unsigned pad:15;
 309       unsigned opcode:16;
 310    } header;
 311 };
 312
 313
 314 struct brw_pipe_control
 315 {
 316    struct
 317    {
 318       unsigned length:8;
 319       unsigned notify_enable:1;
 320       unsigned pad:2;
 321       unsigned instruction_state_cache_flush_enable:1;
 322       unsigned write_cache_flush_enable:1;
 323       unsigned depth_stall_enable:1;
 324       unsigned post_sync_operation:2;
 325
 326       unsigned opcode:16;
 327    } header;
 328
 329    struct
 330    {
 331       unsigned pad:2;
 332       unsigned dest_addr_type:1;
 333       unsigned dest_addr:29;
 334    } bits1;
 335
 336    unsigned data0;
 337    unsigned data1;
 338 };
 339
 340
 341 struct brw_urb_fence
 342 {
 343    struct
 344    {
 345       unsigned length:8;
 346       unsigned vs_realloc:1;
 347       unsigned gs_realloc:1;
 348       unsigned clp_realloc:1;
 349       unsigned sf_realloc:1;
 350       unsigned vfe_realloc:1;
 351       unsigned cs_realloc:1;
 352       unsigned pad:2;
 353       unsigned opcode:16;
 354    } header;
 355
 356    struct
 357    {
 358       unsigned vs_fence:10;
 359       unsigned gs_fence:10;
 360       unsigned clp_fence:10;
 361       unsigned pad:2;
 362    } bits0;
 363
 364    struct
 365    {
 366       unsigned sf_fence:10;
 367       unsigned vf_fence:10;
 368       unsigned cs_fence:10;
 369       unsigned pad:2;
 370    } bits1;
 371 };
 372
 373 struct brw_constant_buffer_state /* previously brw_command_streamer */
 374 {
 375    struct header header;
 376
 377    struct
 378    {
 379       unsigned nr_urb_entries:3;
 380       unsigned pad:1;
 381       unsigned urb_entry_size:5;
 382       unsigned pad0:23;
 383    } bits0;
 384 };
 385
 386 struct brw_constant_buffer
 387 {
 388    struct
 389    {
 390       unsigned length:8;
 391       unsigned valid:1;
 392       unsigned pad:7;
 393       unsigned opcode:16;
 394    } header;
 395
 396    struct
 397    {
 398       unsigned buffer_length:6;
 399       unsigned buffer_address:26;
 400    } bits0;
 401 };
 402
 403 struct brw_state_base_address
 404 {
 405    struct header header;
 406
 407    struct
 408    {
 409       unsigned modify_enable:1;
 410       unsigned pad:4;
 411       unsigned general_state_address:27;
 412    } bits0;
 413
 414    struct
 415    {
 416       unsigned modify_enable:1;
 417       unsigned pad:4;
 418       unsigned surface_state_address:27;
 419    } bits1;
 420
 421    struct
 422    {
 423       unsigned modify_enable:1;
 424       unsigned pad:4;
 425       unsigned indirect_object_state_address:27;
 426    } bits2;
 427
 428    struct
 429    {
 430       unsigned modify_enable:1;
 431       unsigned pad:11;
 432       unsigned general_state_upper_bound:20;
 433    } bits3;
 434
 435    struct
 436    {
 437       unsigned modify_enable:1;
 438       unsigned pad:11;
 439       unsigned indirect_object_state_upper_bound:20;
 440    } bits4;
 441 };
 442
 443 struct brw_state_prefetch
 444 {
 445    struct header header;
 446
 447    struct
 448    {
 449       unsigned prefetch_count:3;
 450       unsigned pad:3;
 451       unsigned prefetch_pointer:26;
 452    } bits0;
 453 };
 454
 455 struct brw_system_instruction_pointer
 456 {
 457    struct header header;
 458
 459    struct
 460    {
 461       unsigned pad:4;
 462       unsigned system_instruction_pointer:28;
 463    } bits0;
 464 };
 465
 466
 467
 468
 469 /* State structs for the various fixed function units:
 470  */
 471
 472
 473 struct thread0
 474 {
 475    unsigned pad0:1;
 476    unsigned grf_reg_count:3;
 477    unsigned pad1:2;
 478    unsigned kernel_start_pointer:26;
 479 };
 480
 481 struct thread1
 482 {
 483    unsigned ext_halt_exception_enable:1;
 484    unsigned sw_exception_enable:1;
 485    unsigned mask_stack_exception_enable:1;
 486    unsigned timeout_exception_enable:1;
 487    unsigned illegal_op_exception_enable:1;
 488    unsigned pad0:3;
 489    unsigned depth_coef_urb_read_offset:6;       /* WM only */
 490    unsigned pad1:2;
 491    unsigned floating_point_mode:1;
 492    unsigned thread_priority:1;
 493    unsigned binding_table_entry_count:8;
 494    unsigned pad3:5;
 495    unsigned single_program_flow:1;
 496 };
 497
 498 struct thread2
 499 {
 500    unsigned per_thread_scratch_space:4;
 501    unsigned pad0:6;
 502    unsigned scratch_space_base_pointer:22;
 503 };
 504
 505
 506 struct thread3
 507 {
 508    unsigned dispatch_grf_start_reg:4;
 509    unsigned urb_entry_read_offset:6;
 510    unsigned pad0:1;
 511    unsigned urb_entry_read_length:6;
 512    unsigned pad1:1;
 513    unsigned const_urb_entry_read_offset:6;
 514    unsigned pad2:1;
 515    unsigned const_urb_entry_read_length:6;
 516    unsigned pad3:1;
 517 };
 518
 519
 520
 521 struct brw_clip_unit_state
 522 {
 523    struct thread0 thread0;
 524    struct
 525    {
 526       unsigned pad0:7;
 527       unsigned sw_exception_enable:1;
 528       unsigned pad1:3;
 529       unsigned mask_stack_exception_enable:1;
 530       unsigned pad2:1;
 531       unsigned illegal_op_exception_enable:1;
 532       unsigned pad3:2;
 533       unsigned floating_point_mode:1;
 534       unsigned thread_priority:1;
 535       unsigned binding_table_entry_count:8;
 536       unsigned pad4:5;
 537       unsigned single_program_flow:1;
 538    } thread1;
 539
 540    struct thread2 thread2;
 541    struct thread3 thread3;
 542
 543    struct
 544    {
 545       unsigned pad0:9;
 546       unsigned gs_output_stats:1; /* not always */
 547       unsigned stats_enable:1;
 548       unsigned nr_urb_entries:7;
 549       unsigned pad1:1;
 550       unsigned urb_entry_allocation_size:5;
 551       unsigned pad2:1;
 552       unsigned max_threads:1;   /* may be less */
 553       unsigned pad3:6;
 554    } thread4;
 555
 556    struct
 557    {
 558       unsigned pad0:13;
 559       unsigned clip_mode:3;
 560       unsigned userclip_enable_flags:8;
 561       unsigned userclip_must_clip:1;
 562       unsigned pad1:1;
 563       unsigned guard_band_enable:1;
 564       unsigned viewport_z_clip_enable:1;
 565       unsigned viewport_xy_clip_enable:1;
 566       unsigned vertex_position_space:1;
 567       unsigned api_mode:1;
 568       unsigned pad2:1;
 569    } clip5;
 570
 571    struct
 572    {
 573       unsigned pad0:5;
 574       unsigned clipper_viewport_state_ptr:27;
 575    } clip6;
 576
 577
 578    float viewport_xmin;
 579    float viewport_xmax;
 580    float viewport_ymin;
 581    float viewport_ymax;
 582 };
 583
 584
 585
 586 struct brw_cc_unit_state
 587 {
 588    struct
 589    {
 590       unsigned pad0:3;
 591       unsigned bf_stencil_pass_depth_pass_op:3;
 592       unsigned bf_stencil_pass_depth_fail_op:3;
 593       unsigned bf_stencil_fail_op:3;
 594       unsigned bf_stencil_func:3;
 595       unsigned bf_stencil_enable:1;
 596       unsigned pad1:2;
 597       unsigned stencil_write_enable:1;
 598       unsigned stencil_pass_depth_pass_op:3;
 599       unsigned stencil_pass_depth_fail_op:3;
 600       unsigned stencil_fail_op:3;
 601       unsigned stencil_func:3;
 602       unsigned stencil_enable:1;
 603    } cc0;
 604
 605
 606    struct
 607    {
 608       unsigned bf_stencil_ref:8;
 609       unsigned stencil_write_mask:8;
 610       unsigned stencil_test_mask:8;
 611       unsigned stencil_ref:8;
 612    } cc1;
 613
 614
 615    struct
 616    {
 617       unsigned logicop_enable:1;
 618       unsigned pad0:10;
 619       unsigned depth_write_enable:1;
 620       unsigned depth_test_function:3;
 621       unsigned depth_test:1;
 622       unsigned bf_stencil_write_mask:8;
 623       unsigned bf_stencil_test_mask:8;
 624    } cc2;
 625
 626
 627    struct
 628    {
 629       unsigned pad0:8;
 630       unsigned alpha_test_func:3;
 631       unsigned alpha_test:1;
 632       unsigned blend_enable:1;
 633       unsigned ia_blend_enable:1;
 634       unsigned pad1:1;
 635       unsigned alpha_test_format:1;
 636       unsigned pad2:16;
 637    } cc3;
 638
 639    struct
 640    {
 641       unsigned pad0:5;
 642       unsigned cc_viewport_state_offset:27;
 643    } cc4;
 644
 645    struct
 646    {
 647       unsigned pad0:2;
 648       unsigned ia_dest_blend_factor:5;
 649       unsigned ia_src_blend_factor:5;
 650       unsigned ia_blend_function:3;
 651       unsigned statistics_enable:1;
 652       unsigned logicop_func:4;
 653       unsigned pad1:11;
 654       unsigned dither_enable:1;
 655    } cc5;
 656
 657    struct
 658    {
 659       unsigned clamp_post_alpha_blend:1;
 660       unsigned clamp_pre_alpha_blend:1;
 661       unsigned clamp_range:2;
 662       unsigned pad0:11;
 663       unsigned y_dither_offset:2;
 664       unsigned x_dither_offset:2;
 665       unsigned dest_blend_factor:5;
 666       unsigned src_blend_factor:5;
 667       unsigned blend_function:3;
 668    } cc6;
 669
 670    struct {
 671       union {
 672          float f;
 673          ubyte ub[4];
 674       } alpha_ref;
 675    } cc7;
 676 };
 677
 678
 679
 680 struct brw_sf_unit_state
 681 {
 682    struct thread0 thread0;
 683    struct thread1 thread1;
 684    struct thread2 thread2;
 685    struct thread3 thread3;
 686
 687    struct
 688    {
 689       unsigned pad0:10;
 690       unsigned stats_enable:1;
 691       unsigned nr_urb_entries:7;
 692       unsigned pad1:1;
 693       unsigned urb_entry_allocation_size:5;
 694       unsigned pad2:1;
 695       unsigned max_threads:6;
 696       unsigned pad3:1;
 697    } thread4;
 698
 699    struct
 700    {
 701       unsigned front_winding:1;
 702       unsigned viewport_transform:1;
 703       unsigned pad0:3;
 704       unsigned sf_viewport_state_offset:27;
 705    } sf5;
 706
 707    struct
 708    {
 709       unsigned pad0:9;
 710       unsigned dest_org_vbias:4;
 711       unsigned dest_org_hbias:4;
 712       unsigned scissor:1;
 713       unsigned disable_2x2_trifilter:1;
 714       unsigned disable_zero_pix_trifilter:1;
 715       unsigned point_rast_rule:2;
 716       unsigned line_endcap_aa_region_width:2;
 717       unsigned line_width:4;
 718       unsigned fast_scissor_disable:1;
 719       unsigned cull_mode:2;
 720       unsigned aa_enable:1;
 721    } sf6;
 722
 723    struct
 724    {
 725       unsigned point_size:11;
 726       unsigned use_point_size_state:1;
 727       unsigned subpixel_precision:1;
 728       unsigned sprite_point:1;
 729       unsigned pad0:11;
 730       unsigned trifan_pv:2;
 731       unsigned linestrip_pv:2;
 732       unsigned tristrip_pv:2;
 733       unsigned line_last_pixel_enable:1;
 734    } sf7;
 735
 736 };
 737
 738
 739 struct brw_gs_unit_state
 740 {
 741    struct thread0 thread0;
 742    struct thread1 thread1;
 743    struct thread2 thread2;
 744    struct thread3 thread3;
 745
 746    struct
 747    {
 748       unsigned pad0:10;
 749       unsigned stats_enable:1;
 750       unsigned nr_urb_entries:7;
 751       unsigned pad1:1;
 752       unsigned urb_entry_allocation_size:5;
 753       unsigned pad2:1;
 754       unsigned max_threads:1;
 755       unsigned pad3:6;
 756    } thread4;
 757
 758    struct
 759    {
 760       unsigned sampler_count:3;
 761       unsigned pad0:2;
 762       unsigned sampler_state_pointer:27;
 763    } gs5;
 764
 765
 766    struct
 767    {
 768       unsigned max_vp_index:4;
 769       unsigned pad0:26;
 770       unsigned reorder_enable:1;
 771       unsigned pad1:1;
 772    } gs6;
 773 };
 774
 775
 776 struct brw_vs_unit_state
 777 {
 778    struct thread0 thread0;
 779    struct thread1 thread1;
 780    struct thread2 thread2;
 781    struct thread3 thread3;
 782
 783    struct
 784    {
 785       unsigned pad0:10;
 786       unsigned stats_enable:1;
 787       unsigned nr_urb_entries:7;
 788       unsigned pad1:1;
 789       unsigned urb_entry_allocation_size:5;
 790       unsigned pad2:1;
 791       unsigned max_threads:4;
 792       unsigned pad3:3;
 793    } thread4;
 794
 795    struct
 796    {
 797       unsigned sampler_count:3;
 798       unsigned pad0:2;
 799       unsigned sampler_state_pointer:27;
 800    } vs5;
 801
 802    struct
 803    {
 804       unsigned vs_enable:1;
 805       unsigned vert_cache_disable:1;
 806       unsigned pad0:30;
 807    } vs6;
 808 };
 809
 810
 811 struct brw_wm_unit_state
 812 {
 813    struct thread0 thread0;
 814    struct thread1 thread1;
 815    struct thread2 thread2;
 816    struct thread3 thread3;
 817
 818    struct {
 819       unsigned stats_enable:1;
 820       unsigned pad0:1;
 821       unsigned sampler_count:3;
 822       unsigned sampler_state_pointer:27;
 823    } wm4;
 824
 825    struct
 826    {
 827       unsigned enable_8_pix:1;
 828       unsigned enable_16_pix:1;
 829       unsigned enable_32_pix:1;
 830       unsigned pad0:7;
 831       unsigned legacy_global_depth_bias:1;
 832       unsigned line_stipple:1;
 833       unsigned depth_offset:1;
 834       unsigned polygon_stipple:1;
 835       unsigned line_aa_region_width:2;
 836       unsigned line_endcap_aa_region_width:2;
 837       unsigned early_depth_test:1;
 838       unsigned thread_dispatch_enable:1;
 839       unsigned program_uses_depth:1;
 840       unsigned program_computes_depth:1;
 841       unsigned program_uses_killpixel:1;
 842       unsigned legacy_line_rast: 1;
 843       unsigned pad1:1;
 844       unsigned max_threads:6;
 845       unsigned pad2:1;
 846    } wm5;
 847
 848    float global_depth_offset_constant;
 849    float global_depth_offset_scale;
 850 };
 851
 852 struct brw_sampler_default_color {
 853    float color[4];
 854 };
 855
 856 struct brw_sampler_state
 857 {
 858
 859    struct
 860    {
 861       unsigned shadow_function:3;
 862       unsigned lod_bias:11;
 863       unsigned min_filter:3;
 864       unsigned mag_filter:3;
 865       unsigned mip_filter:2;
 866       unsigned base_level:5;
 867       unsigned pad:1;
 868       unsigned lod_preclamp:1;
 869       unsigned default_color_mode:1;
 870       unsigned pad0:1;
 871       unsigned disable:1;
 872    } ss0;
 873
 874    struct
 875    {
 876       unsigned r_wrap_mode:3;
 877       unsigned t_wrap_mode:3;
 878       unsigned s_wrap_mode:3;
 879       unsigned pad:3;
 880       unsigned max_lod:10;
 881       unsigned min_lod:10;
 882    } ss1;
 883
 884
 885    struct
 886    {
 887       unsigned pad:5;
 888       unsigned default_color_pointer:27;
 889    } ss2;
 890
 891    struct
 892    {
 893       unsigned pad:19;
 894       unsigned max_aniso:3;
 895       unsigned chroma_key_mode:1;
 896       unsigned chroma_key_index:2;
 897       unsigned chroma_key_enable:1;
 898       unsigned monochrome_filter_width:3;
 899       unsigned monochrome_filter_height:3;
 900    } ss3;
 901 };
 902
 903
 904 struct brw_clipper_viewport
 905 {
 906    float xmin;
 907    float xmax;
 908    float ymin;
 909    float ymax;
 910 };
 911
 912 struct brw_cc_viewport
 913 {
 914    float min_depth;
 915    float max_depth;
 916 };
 917
 918 struct brw_sf_viewport
 919 {
 920    struct {
 921       float m00;
 922       float m11;
 923       float m22;
 924       float m30;
 925       float m31;
 926       float m32;
 927    } viewport;
 928
 929    struct {
 930       short xmin;
 931       short ymin;
 932       short xmax;
 933       short ymax;
 934    } scissor;
 935 };
 936
 937 /* Documented in the subsystem/shared-functions/sampler chapter...
 938  */
 939 struct brw_surface_state
 940 {
 941    struct {
 942       unsigned cube_pos_z:1;
 943       unsigned cube_neg_z:1;
 944       unsigned cube_pos_y:1;
 945       unsigned cube_neg_y:1;
 946       unsigned cube_pos_x:1;
 947       unsigned cube_neg_x:1;
 948       unsigned pad:4;
 949       unsigned mipmap_layout_mode:1;
 950       unsigned vert_line_stride_ofs:1;
 951       unsigned vert_line_stride:1;
 952       unsigned color_blend:1;
 953       unsigned writedisable_blue:1;
 954       unsigned writedisable_green:1;
 955       unsigned writedisable_red:1;
 956       unsigned writedisable_alpha:1;
 957       unsigned surface_format:9;
 958       unsigned data_return_format:1;
 959       unsigned pad0:1;
 960       unsigned surface_type:3;
 961    } ss0;
 962
 963    struct {
 964       unsigned base_addr;
 965    } ss1;
 966
 967    struct {
 968       unsigned pad:2;
 969       unsigned mip_count:4;
 970       unsigned width:13;
 971       unsigned height:13;
 972    } ss2;
 973
 974    struct {
 975       unsigned tile_walk:1;
 976       unsigned tiled_surface:1;
 977       unsigned pad:1;
 978       unsigned pitch:18;
 979       unsigned depth:11;
 980    } ss3;
 981
 982    struct {
 983       unsigned pad:19;
 984       unsigned min_array_elt:9;
 985       unsigned min_lod:4;
 986    } ss4;
 987 };
 988
 989
 990
 991 struct brw_vertex_buffer_state
 992 {
 993    struct {
 994       unsigned pitch:11;
 995       unsigned pad:15;
 996       unsigned access_type:1;
 997       unsigned vb_index:5;
 998    } vb0;
 999
1000    unsigned start_addr;
1001    unsigned max_index;
1002 #if 1
1003    unsigned instance_data_step_rate; /* not included for sequential/random vertices? */
1004 #endif
1005 };
1006
1007 #define BRW_VBP_MAX 17
1008
1009 struct brw_vb_array_state {
1010    struct header header;
1011    struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
1012 };
1013
1014
1015 struct brw_vertex_element_state
1016 {
1017    struct
1018    {
1019       unsigned src_offset:11;
1020       unsigned pad:5;
1021       unsigned src_format:9;
1022       unsigned pad0:1;
1023       unsigned valid:1;
1024       unsigned vertex_buffer_index:5;
1025    } ve0;
1026
1027    struct
1028    {
1029       unsigned dst_offset:8;
1030       unsigned pad:8;
1031       unsigned vfcomponent3:4;
1032       unsigned vfcomponent2:4;
1033       unsigned vfcomponent1:4;
1034       unsigned vfcomponent0:4;
1035    } ve1;
1036 };
1037
1038 #define BRW_VEP_MAX 18
1039
1040 struct brw_vertex_element_packet {
1041    struct header header;
1042    struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1043 };
1044
1045
1046 struct brw_urb_immediate {
1047    unsigned opcode:4;
1048    unsigned offset:6;
1049    unsigned swizzle_control:2;
1050    unsigned pad:1;
1051    unsigned allocate:1;
1052    unsigned used:1;
1053    unsigned complete:1;
1054    unsigned response_length:4;
1055    unsigned msg_length:4;
1056    unsigned msg_target:4;
1057    unsigned pad1:3;
1058    unsigned end_of_thread:1;
1059 };
1060
1061 /* Instruction format for the execution units:
1062  */
1063
1064 struct brw_instruction
1065 {
1066    struct
1067    {
1068       unsigned opcode:7;
1069       unsigned pad:1;
1070       unsigned access_mode:1;
1071       unsigned mask_control:1;
1072       unsigned dependency_control:2;
1073       unsigned compression_control:2;
1074       unsigned thread_control:2;
1075       unsigned predicate_control:4;
1076       unsigned predicate_inverse:1;
1077       unsigned execution_size:3;
1078       unsigned destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */
1079       unsigned pad0:2;
1080       unsigned debug_control:1;
1081       unsigned saturate:1;
1082    } header;
1083
1084    union {
1085       struct
1086       {
1087          unsigned dest_reg_file:2;
1088          unsigned dest_reg_type:3;
1089          unsigned src0_reg_file:2;
1090          unsigned src0_reg_type:3;
1091          unsigned src1_reg_file:2;
1092          unsigned src1_reg_type:3;
1093          unsigned pad:1;
1094          unsigned dest_subreg_nr:5;
1095          unsigned dest_reg_nr:8;
1096          unsigned dest_horiz_stride:2;
1097          unsigned dest_address_mode:1;
1098       } da1;
1099
1100       struct
1101       {
1102          unsigned dest_reg_file:2;
1103          unsigned dest_reg_type:3;
1104          unsigned src0_reg_file:2;
1105          unsigned src0_reg_type:3;
1106          unsigned pad:6;
1107          int dest_indirect_offset:10;   /* offset against the deref'd address reg */
1108          unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
1109          unsigned dest_horiz_stride:2;
1110          unsigned dest_address_mode:1;
1111       } ia1;
1112
1113       struct
1114       {
1115          unsigned dest_reg_file:2;
1116          unsigned dest_reg_type:3;
1117          unsigned src0_reg_file:2;
1118          unsigned src0_reg_type:3;
1119          unsigned src1_reg_file:2;
1120          unsigned src1_reg_type:3;
1121          unsigned pad0:1;
1122          unsigned dest_writemask:4;
1123          unsigned dest_subreg_nr:1;
1124          unsigned dest_reg_nr:8;
1125          unsigned pad1:2;
1126          unsigned dest_address_mode:1;
1127       } da16;
1128
1129       struct
1130       {
1131          unsigned dest_reg_file:2;
1132          unsigned dest_reg_type:3;
1133          unsigned src0_reg_file:2;
1134          unsigned src0_reg_type:3;
1135          unsigned pad0:6;
1136          unsigned dest_writemask:4;
1137          int dest_indirect_offset:6;
1138          unsigned dest_subreg_nr:3;
1139          unsigned pad1:2;
1140          unsigned dest_address_mode:1;
1141       } ia16;
1142    } bits1;
1143
1144
1145    union {
1146       struct
1147       {
1148          unsigned src0_subreg_nr:5;
1149          unsigned src0_reg_nr:8;
1150          unsigned src0_abs:1;
1151          unsigned src0_negate:1;
1152          unsigned src0_address_mode:1;
1153          unsigned src0_horiz_stride:2;
1154          unsigned src0_width:3;
1155          unsigned src0_vert_stride:4;
1156          unsigned flag_reg_nr:1;
1157          unsigned pad:6;
1158       } da1;
1159
1160       struct
1161       {
1162          int src0_indirect_offset:10;
1163          unsigned src0_subreg_nr:3;
1164          unsigned src0_abs:1;
1165          unsigned src0_negate:1;
1166          unsigned src0_address_mode:1;
1167          unsigned src0_horiz_stride:2;
1168          unsigned src0_width:3;
1169          unsigned src0_vert_stride:4;
1170          unsigned flag_reg_nr:1;
1171          unsigned pad:6;
1172       } ia1;
1173
1174       struct
1175       {
1176          unsigned src0_swz_x:2;
1177          unsigned src0_swz_y:2;
1178          unsigned src0_subreg_nr:1;
1179          unsigned src0_reg_nr:8;
1180          unsigned src0_abs:1;
1181          unsigned src0_negate:1;
1182          unsigned src0_address_mode:1;
1183          unsigned src0_swz_z:2;
1184          unsigned src0_swz_w:2;
1185          unsigned pad0:1;
1186          unsigned src0_vert_stride:4;
1187          unsigned flag_reg_nr:1;
1188          unsigned pad1:6;
1189       } da16;
1190
1191       struct
1192       {
1193          unsigned src0_swz_x:2;
1194          unsigned src0_swz_y:2;
1195          int src0_indirect_offset:6;
1196          unsigned src0_subreg_nr:3;
1197          unsigned src0_abs:1;
1198          unsigned src0_negate:1;
1199          unsigned src0_address_mode:1;
1200          unsigned src0_swz_z:2;
1201          unsigned src0_swz_w:2;
1202          unsigned pad0:1;
1203          unsigned src0_vert_stride:4;
1204          unsigned flag_reg_nr:1;
1205          unsigned pad1:6;
1206       } ia16;
1207
1208    } bits2;
1209
1210    union
1211    {
1212       struct
1213       {
1214          unsigned src1_subreg_nr:5;
1215          unsigned src1_reg_nr:8;
1216          unsigned src1_abs:1;
1217          unsigned src1_negate:1;
1218          unsigned pad:1;
1219          unsigned src1_horiz_stride:2;
1220          unsigned src1_width:3;
1221          unsigned src1_vert_stride:4;
1222          unsigned pad0:7;
1223       } da1;
1224
1225       struct
1226       {
1227          unsigned src1_swz_x:2;
1228          unsigned src1_swz_y:2;
1229          unsigned src1_subreg_nr:1;
1230          unsigned src1_reg_nr:8;
1231          unsigned src1_abs:1;
1232          unsigned src1_negate:1;
1233          unsigned pad0:1;
1234          unsigned src1_swz_z:2;
1235          unsigned src1_swz_w:2;
1236          unsigned pad1:1;
1237          unsigned src1_vert_stride:4;
1238          unsigned pad2:7;
1239       } da16;
1240
1241       struct
1242       {
1243          int  src1_indirect_offset:10;
1244          unsigned src1_subreg_nr:3;
1245          unsigned src1_abs:1;
1246          unsigned src1_negate:1;
1247          unsigned pad0:1;
1248          unsigned src1_horiz_stride:2;
1249          unsigned src1_width:3;
1250          unsigned src1_vert_stride:4;
1251          unsigned flag_reg_nr:1;
1252          unsigned pad1:6;
1253       } ia1;
1254
1255       struct
1256       {
1257          unsigned src1_swz_x:2;
1258          unsigned src1_swz_y:2;
1259          int  src1_indirect_offset:6;
1260          unsigned src1_subreg_nr:3;
1261          unsigned src1_abs:1;
1262          unsigned src1_negate:1;
1263          unsigned pad0:1;
1264          unsigned src1_swz_z:2;
1265          unsigned src1_swz_w:2;
1266          unsigned pad1:1;
1267          unsigned src1_vert_stride:4;
1268          unsigned flag_reg_nr:1;
1269          unsigned pad2:6;
1270       } ia16;
1271
1272
1273       struct
1274       {
1275          int  jump_count:16;    /* note: signed */
1276          unsigned  pop_count:4;
1277          unsigned  pad0:12;
1278       } if_else;
1279
1280       struct {
1281          unsigned function:4;
1282          unsigned int_type:1;
1283          unsigned precision:1;
1284          unsigned saturate:1;
1285          unsigned data_type:1;
1286          unsigned pad0:8;
1287          unsigned response_length:4;
1288          unsigned msg_length:4;
1289          unsigned msg_target:4;
1290          unsigned pad1:3;
1291          unsigned end_of_thread:1;
1292       } math;
1293
1294       struct {
1295          unsigned binding_table_index:8;
1296          unsigned sampler:4;
1297          unsigned return_format:2;
1298          unsigned msg_type:2;
1299          unsigned response_length:4;
1300          unsigned msg_length:4;
1301          unsigned msg_target:4;
1302          unsigned pad1:3;
1303          unsigned end_of_thread:1;
1304       } sampler;
1305
1306       struct brw_urb_immediate urb;
1307
1308       struct {
1309          unsigned binding_table_index:8;
1310          unsigned msg_control:4;
1311          unsigned msg_type:2;
1312          unsigned target_cache:2;
1313          unsigned response_length:4;
1314          unsigned msg_length:4;
1315          unsigned msg_target:4;
1316          unsigned pad1:3;
1317          unsigned end_of_thread:1;
1318       } dp_read;
1319
1320       struct {
1321          unsigned binding_table_index:8;
1322          unsigned msg_control:3;
1323          unsigned pixel_scoreboard_clear:1;
1324          unsigned msg_type:3;
1325          unsigned send_commit_msg:1;
1326          unsigned response_length:4;
1327          unsigned msg_length:4;
1328          unsigned msg_target:4;
1329          unsigned pad1:3;
1330          unsigned end_of_thread:1;
1331       } dp_write;
1332
1333       struct {
1334          unsigned pad:16;
1335          unsigned response_length:4;
1336          unsigned msg_length:4;
1337          unsigned msg_target:4;
1338          unsigned pad1:3;
1339          unsigned end_of_thread:1;
1340       } generic;
1341
1342       int d;
1343       unsigned ud;
1344    } bits3;
1345 };
1346
1347
1348 #endif