2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "brw_context.h"
33 #include "brw_state.h"
34 #include "brw_defines.h"
36 static unsigned translate_tex_target( enum pipe_texture_target target
)
40 return BRW_SURFACE_1D
;
43 return BRW_SURFACE_2D
;
46 return BRW_SURFACE_3D
;
48 case PIPE_TEXTURE_CUBE
:
49 return BRW_SURFACE_CUBE
;
57 static unsigned translate_tex_format( enum pipe_format pipe_format
)
59 switch( pipe_format
) {
60 case PIPE_FORMAT_L8_UNORM
:
61 return BRW_SURFACEFORMAT_L8_UNORM
;
63 case PIPE_FORMAT_I8_UNORM
:
64 return BRW_SURFACEFORMAT_I8_UNORM
;
66 case PIPE_FORMAT_A8_UNORM
:
67 return BRW_SURFACEFORMAT_A8_UNORM
;
69 case PIPE_FORMAT_A8L8_UNORM
:
70 return BRW_SURFACEFORMAT_L8A8_UNORM
;
72 case PIPE_FORMAT_R8G8B8_UNORM
:
73 assert(0); /* not supported for sampling */
74 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
76 case PIPE_FORMAT_B8G8R8A8_UNORM
:
77 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
79 case PIPE_FORMAT_R8G8B8A8_UNORM
:
80 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
82 case PIPE_FORMAT_R5G6B5_UNORM
:
83 return BRW_SURFACEFORMAT_B5G6R5_UNORM
;
85 case PIPE_FORMAT_A1R5G5B5_UNORM
:
86 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
88 case PIPE_FORMAT_A4R4G4B4_UNORM
:
89 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
91 case PIPE_FORMAT_YCBCR_REV
:
92 return BRW_SURFACEFORMAT_YCRCB_NORMAL
;
94 case PIPE_FORMAT_YCBCR
:
95 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY
;
97 case PIPE_FORMAT_RGB_FXT1
:
98 case PIPE_FORMAT_RGBA_FXT1
:
99 return BRW_SURFACEFORMAT_FXT1
;
102 case PIPE_FORMAT_Z16_UNORM
:
103 return BRW_SURFACEFORMAT_I16_UNORM
;
105 case PIPE_FORMAT_RGB_DXT1
:
106 return BRW_SURFACEFORMAT_DXT1_RGB
;
108 case PIPE_FORMAT_RGBA_DXT1
:
109 return BRW_SURFACEFORMAT_BC1_UNORM
;
111 case PIPE_FORMAT_RGBA_DXT3
:
112 return BRW_SURFACEFORMAT_BC2_UNORM
;
114 case PIPE_FORMAT_RGBA_DXT5
:
115 return BRW_SURFACEFORMAT_BC3_UNORM
;
117 case PIPE_FORMAT_SRGBA8
:
118 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB
;
119 case PIPE_FORMAT_SRGB_DXT1
:
120 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB
;
129 static unsigned brw_buffer_offset(struct brw_context
*brw
,
130 struct pipe_buffer
*buffer
)
132 return brw
->winsys
->get_buffer_offset(brw
->winsys
,
138 void brw_update_texture_surface( struct brw_context
*brw
,
141 const struct brw_texture
*tObj
= brw
->attribs
.Texture
[unit
];
142 struct brw_surface_state surf
;
144 memset(&surf
, 0, sizeof(surf
));
146 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
147 surf
.ss0
.surface_type
= translate_tex_target(tObj
->base
.target
);
148 surf
.ss0
.surface_format
= translate_tex_format(tObj
->base
.format
);
150 /* This is ok for all textures with channel width 8bit or less:
152 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
154 /* Updated in emit_reloc */
155 surf
.ss1
.base_addr
= brw_buffer_offset( brw
, tObj
->buffer
);
157 surf
.ss2
.mip_count
= tObj
->base
.last_level
;
158 surf
.ss2
.width
= tObj
->base
.width
[0] - 1;
159 surf
.ss2
.height
= tObj
->base
.height
[0] - 1;
161 surf
.ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
162 surf
.ss3
.tiled_surface
= 0; /* always zero */
163 surf
.ss3
.pitch
= tObj
->stride
- 1;
164 surf
.ss3
.depth
= tObj
->base
.depth
[0] - 1;
166 surf
.ss4
.min_lod
= 0;
168 if (tObj
->base
.target
== PIPE_TEXTURE_CUBE
) {
169 surf
.ss0
.cube_pos_x
= 1;
170 surf
.ss0
.cube_pos_y
= 1;
171 surf
.ss0
.cube_pos_z
= 1;
172 surf
.ss0
.cube_neg_x
= 1;
173 surf
.ss0
.cube_neg_y
= 1;
174 surf
.ss0
.cube_neg_z
= 1;
177 brw
->wm
.bind
.surf_ss_offset
[unit
+ 1] =
178 brw_cache_data( &brw
->cache
[BRW_SS_SURFACE
], &surf
);
183 #define OFFSET(TYPE, FIELD) ( (unsigned)&(((TYPE *)0)->FIELD) )
186 static void upload_wm_surfaces(struct brw_context
*brw
)
191 struct brw_surface_state surf
;
193 /* BRW_NEW_FRAMEBUFFER
195 struct pipe_surface
*pipe_surface
= brw
->attribs
.FrameBuffer
.cbufs
[0];/*fixme*/
196 struct brw_texture
*tex
= (struct brw_texture
*)pipe_surface
->texture
;
198 memset(&surf
, 0, sizeof(surf
));
200 if (pipe_surface
!= NULL
) {
201 if (pipe_surface
->block
.size
== 4)
202 surf
.ss0
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
204 surf
.ss0
.surface_format
= BRW_SURFACEFORMAT_B5G6R5_UNORM
;
206 surf
.ss0
.surface_type
= BRW_SURFACE_2D
;
208 surf
.ss1
.base_addr
= brw_buffer_offset( brw
, tex
->buffer
);
210 surf
.ss2
.width
= pipe_surface
->width
- 1;
211 surf
.ss2
.height
= pipe_surface
->height
- 1;
212 surf
.ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
213 surf
.ss3
.tiled_surface
= 0;
214 surf
.ss3
.pitch
= pipe_surface
->stride
- 1;
216 surf
.ss0
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
217 surf
.ss0
.surface_type
= BRW_SURFACE_NULL
;
221 surf
.ss0
.color_blend
= (!brw
->attribs
.Blend
->logicop_enable
&&
222 brw
->attribs
.Blend
->blend_enable
);
225 surf
.ss0
.writedisable_red
= !(brw
->attribs
.Blend
->colormask
& PIPE_MASK_R
);
226 surf
.ss0
.writedisable_green
= !(brw
->attribs
.Blend
->colormask
& PIPE_MASK_G
);
227 surf
.ss0
.writedisable_blue
= !(brw
->attribs
.Blend
->colormask
& PIPE_MASK_B
);
228 surf
.ss0
.writedisable_alpha
= !(brw
->attribs
.Blend
->colormask
& PIPE_MASK_A
);
233 brw
->wm
.bind
.surf_ss_offset
[0] = brw_cache_data( &brw
->cache
[BRW_SS_SURFACE
], &surf
);
235 brw
->wm
.nr_surfaces
= 1;
241 for (i
= 0; i
< brw
->num_textures
&& i
< brw
->num_samplers
; i
++) {
242 const struct brw_texture
*texUnit
= brw
->attribs
.Texture
[i
];
245 texUnit
->base
.refcount
/*(texUnit->refcount > 0) == really used */) {
247 brw_update_texture_surface(brw
, i
);
249 brw
->wm
.nr_surfaces
= i
+2;
252 brw
->wm
.bind
.surf_ss_offset
[i
+1] = 0;
256 brw
->wm
.bind_ss_offset
= brw_cache_data( &brw
->cache
[BRW_SS_SURF_BIND
],
261 /* KW: Will find a different way to acheive this, see for example the
262 * state caches with relocs in the i915 swz driver.
265 static void emit_reloc_wm_surfaces(struct brw_context
*brw
)
269 if (brw
->state
.draw_region
!= NULL
) {
270 /* Emit framebuffer relocation */
271 dri_emit_reloc(brw_cache_buffer(brw
, BRW_SS_SURFACE
),
272 DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_READ
| DRM_BO_FLAG_WRITE
,
274 brw
->wm
.bind
.surf_ss_offset
[0] +
275 offsetof(struct brw_surface_state
, ss1
),
276 brw
->state
.draw_region
->buffer
);
279 /* Emit relocations for texture buffers */
280 for (unit
= 0; unit
< BRW_MAX_TEX_UNIT
; unit
++) {
281 struct gl_texture_unit
*texUnit
= &brw
->attribs
.Texture
->Unit
[unit
];
282 struct gl_texture_object
*tObj
= texUnit
->_Current
;
283 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
285 if (texUnit
->_ReallyEnabled
&& intelObj
->mt
!= NULL
) {
286 dri_emit_reloc(brw_cache_buffer(brw
, BRW_SS_SURFACE
),
287 DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_READ
,
289 brw
->wm
.bind
.surf_ss_offset
[unit
+ 1] +
290 offsetof(struct brw_surface_state
, ss1
),
291 intelObj
->mt
->region
->buffer
);
297 const struct brw_tracked_state brw_wm_surfaces
= {
299 .brw
= (BRW_NEW_FRAMEBUFFER
|
304 .update
= upload_wm_surfaces
,