2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice shall be included
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Batchbuffer and command submission module.
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
45 #include "drm-uapi/i915_drm.h"
47 #include "common/gen_aux_map.h"
48 #include "intel/common/gen_gem.h"
49 #include "util/hash_table.h"
51 #include "util/u_upload_mgr.h"
52 #include "main/macros.h"
65 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
68 iris_batch_reset(struct iris_batch
*batch
);
71 num_fences(struct iris_batch
*batch
)
73 return util_dynarray_num_elements(&batch
->exec_fences
,
74 struct drm_i915_gem_exec_fence
);
78 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
81 dump_fence_list(struct iris_batch
*batch
)
83 fprintf(stderr
, "Fence list (length %u): ", num_fences(batch
));
85 util_dynarray_foreach(&batch
->exec_fences
,
86 struct drm_i915_gem_exec_fence
, f
) {
87 fprintf(stderr
, "%s%u%s ",
88 (f
->flags
& I915_EXEC_FENCE_WAIT
) ? "..." : "",
90 (f
->flags
& I915_EXEC_FENCE_SIGNAL
) ? "!" : "");
93 fprintf(stderr
, "\n");
97 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
100 dump_validation_list(struct iris_batch
*batch
)
102 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
104 for (int i
= 0; i
< batch
->exec_count
; i
++) {
105 uint64_t flags
= batch
->validation_list
[i
].flags
;
106 assert(batch
->validation_list
[i
].handle
==
107 batch
->exec_bos
[i
]->gem_handle
);
108 fprintf(stderr
, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64
"B)\t %2d refs %s\n",
110 batch
->validation_list
[i
].handle
,
111 batch
->exec_bos
[i
]->name
,
112 batch
->validation_list
[i
].offset
,
113 batch
->exec_bos
[i
]->size
,
114 batch
->exec_bos
[i
]->refcount
,
115 (flags
& EXEC_OBJECT_WRITE
) ? " (write)" : "");
120 * Return BO information to the batch decoder (for debugging).
122 static struct gen_batch_decode_bo
123 decode_get_bo(void *v_batch
, bool ppgtt
, uint64_t address
)
125 struct iris_batch
*batch
= v_batch
;
129 for (int i
= 0; i
< batch
->exec_count
; i
++) {
130 struct iris_bo
*bo
= batch
->exec_bos
[i
];
131 /* The decoder zeroes out the top 16 bits, so we need to as well */
132 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
134 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
135 return (struct gen_batch_decode_bo
) {
138 .map
= iris_bo_map(batch
->dbg
, bo
, MAP_READ
) +
139 (address
- bo_address
),
144 return (struct gen_batch_decode_bo
) { };
148 decode_get_state_size(void *v_batch
,
150 UNUSED
uint64_t base_address
)
152 struct iris_batch
*batch
= v_batch
;
153 unsigned size
= (uintptr_t)
154 _mesa_hash_table_u64_search(batch
->state_sizes
, address
);
160 * Decode the current batch.
163 decode_batch(struct iris_batch
*batch
)
165 void *map
= iris_bo_map(batch
->dbg
, batch
->exec_bos
[0], MAP_READ
);
166 gen_print_batch(&batch
->decoder
, map
, batch
->primary_batch_size
,
167 batch
->exec_bos
[0]->gtt_offset
, false);
171 iris_init_batch(struct iris_context
*ice
,
172 enum iris_batch_name name
,
175 struct iris_batch
*batch
= &ice
->batches
[name
];
176 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
178 batch
->screen
= screen
;
179 batch
->dbg
= &ice
->dbg
;
180 batch
->reset
= &ice
->reset
;
181 batch
->state_sizes
= ice
->state
.sizes
;
184 batch
->fine_fences
.uploader
=
185 u_upload_create(&ice
->ctx
, 4096, PIPE_BIND_CUSTOM
,
186 PIPE_USAGE_STAGING
, 0);
187 iris_fine_fence_init(batch
);
189 batch
->hw_ctx_id
= iris_create_hw_context(screen
->bufmgr
);
190 assert(batch
->hw_ctx_id
);
192 iris_hw_context_set_priority(screen
->bufmgr
, batch
->hw_ctx_id
, priority
);
194 util_dynarray_init(&batch
->exec_fences
, ralloc_context(NULL
));
195 util_dynarray_init(&batch
->syncobjs
, ralloc_context(NULL
));
197 batch
->exec_count
= 0;
198 batch
->exec_array_size
= 100;
200 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
201 batch
->validation_list
=
202 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
204 batch
->cache
.render
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
205 _mesa_key_pointer_equal
);
207 memset(batch
->other_batches
, 0, sizeof(batch
->other_batches
));
209 for (int i
= 0, j
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
211 batch
->other_batches
[j
++] = &ice
->batches
[i
];
214 if (unlikely(INTEL_DEBUG
)) {
215 const unsigned decode_flags
=
216 GEN_BATCH_DECODE_FULL
|
217 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
218 GEN_BATCH_DECODE_OFFSETS
|
219 GEN_BATCH_DECODE_FLOATS
;
221 gen_batch_decode_ctx_init(&batch
->decoder
, &screen
->devinfo
,
222 stderr
, decode_flags
, NULL
,
223 decode_get_bo
, decode_get_state_size
, batch
);
224 batch
->decoder
.dynamic_base
= IRIS_MEMZONE_DYNAMIC_START
;
225 batch
->decoder
.instruction_base
= IRIS_MEMZONE_SHADER_START
;
226 batch
->decoder
.max_vbo_decoded_lines
= 32;
229 iris_batch_reset(batch
);
232 static struct drm_i915_gem_exec_object2
*
233 find_validation_entry(struct iris_batch
*batch
, struct iris_bo
*bo
)
235 unsigned index
= READ_ONCE(bo
->index
);
237 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
238 return &batch
->validation_list
[index
];
240 /* May have been shared between multiple active batches */
241 for (index
= 0; index
< batch
->exec_count
; index
++) {
242 if (batch
->exec_bos
[index
] == bo
)
243 return &batch
->validation_list
[index
];
250 ensure_exec_obj_space(struct iris_batch
*batch
, uint32_t count
)
252 while (batch
->exec_count
+ count
> batch
->exec_array_size
) {
253 batch
->exec_array_size
*= 2;
255 realloc(batch
->exec_bos
,
256 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
257 batch
->validation_list
=
258 realloc(batch
->validation_list
,
259 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
264 * Add a buffer to the current batch's validation list.
266 * You must call this on any BO you wish to use in this batch, to ensure
267 * that it's resident when the GPU commands execute.
270 iris_use_pinned_bo(struct iris_batch
*batch
,
272 bool writable
, enum iris_domain access
)
274 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
276 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
277 * about the order of any writes to that buffer, and marking it writable
278 * would introduce data dependencies between multiple batches which share
281 if (bo
== batch
->screen
->workaround_bo
)
284 if (access
< NUM_IRIS_DOMAINS
) {
285 assert(batch
->sync_region_depth
);
286 iris_bo_bump_seqno(bo
, batch
->next_seqno
, access
);
289 struct drm_i915_gem_exec_object2
*existing_entry
=
290 find_validation_entry(batch
, bo
);
292 if (existing_entry
) {
293 /* The BO is already in the validation list; mark it writable */
295 existing_entry
->flags
|= EXEC_OBJECT_WRITE
;
300 if (bo
!= batch
->bo
) {
301 /* This is the first time our batch has seen this BO. Before we use it,
302 * we may need to flush and synchronize with other batches.
304 for (int b
= 0; b
< ARRAY_SIZE(batch
->other_batches
); b
++) {
305 struct drm_i915_gem_exec_object2
*other_entry
=
306 find_validation_entry(batch
->other_batches
[b
], bo
);
308 /* If the buffer is referenced by another batch, and either batch
309 * intends to write it, then flush the other batch and synchronize.
311 * Consider these cases:
313 * 1. They read, we read => No synchronization required.
314 * 2. They read, we write => Synchronize (they need the old value)
315 * 3. They write, we read => Synchronize (we need their new value)
316 * 4. They write, we write => Synchronize (order writes)
318 * The read/read case is very common, as multiple batches usually
319 * share a streaming state buffer or shader assembly buffer, and
320 * we want to avoid synchronizing in this case.
323 ((other_entry
->flags
& EXEC_OBJECT_WRITE
) || writable
)) {
324 iris_batch_flush(batch
->other_batches
[b
]);
325 iris_batch_add_syncobj(batch
,
326 batch
->other_batches
[b
]->last_fence
->syncobj
,
327 I915_EXEC_FENCE_WAIT
);
332 /* Now, take a reference and add it to the validation list. */
333 iris_bo_reference(bo
);
335 ensure_exec_obj_space(batch
, 1);
337 batch
->validation_list
[batch
->exec_count
] =
338 (struct drm_i915_gem_exec_object2
) {
339 .handle
= bo
->gem_handle
,
340 .offset
= bo
->gtt_offset
,
341 .flags
= bo
->kflags
| (writable
? EXEC_OBJECT_WRITE
: 0),
344 bo
->index
= batch
->exec_count
;
345 batch
->exec_bos
[batch
->exec_count
] = bo
;
346 batch
->aperture_space
+= bo
->size
;
352 create_batch(struct iris_batch
*batch
)
354 struct iris_screen
*screen
= batch
->screen
;
355 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
357 batch
->bo
= iris_bo_alloc(bufmgr
, "command buffer",
358 BATCH_SZ
+ BATCH_RESERVED
, IRIS_MEMZONE_OTHER
);
359 batch
->bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
360 batch
->map
= iris_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
361 batch
->map_next
= batch
->map
;
363 iris_use_pinned_bo(batch
, batch
->bo
, false, IRIS_DOMAIN_NONE
);
367 iris_batch_maybe_noop(struct iris_batch
*batch
)
369 /* We only insert the NOOP at the beginning of the batch. */
370 assert(iris_batch_bytes_used(batch
) == 0);
372 if (batch
->noop_enabled
) {
373 /* Emit MI_BATCH_BUFFER_END to prevent any further command to be
376 uint32_t *map
= batch
->map_next
;
378 map
[0] = (0xA << 23);
380 batch
->map_next
+= 4;
385 iris_batch_reset(struct iris_batch
*batch
)
387 struct iris_screen
*screen
= batch
->screen
;
389 iris_bo_unreference(batch
->bo
);
390 batch
->primary_batch_size
= 0;
391 batch
->total_chained_batch_size
= 0;
392 batch
->contains_draw
= false;
393 batch
->decoder
.surface_base
= batch
->last_surface_base_address
;
396 assert(batch
->bo
->index
== 0);
398 struct iris_syncobj
*syncobj
= iris_create_syncobj(screen
);
399 iris_batch_add_syncobj(batch
, syncobj
, I915_EXEC_FENCE_SIGNAL
);
400 iris_syncobj_reference(screen
, &syncobj
, NULL
);
402 assert(!batch
->sync_region_depth
);
403 iris_batch_sync_boundary(batch
);
404 iris_batch_mark_reset_sync(batch
);
406 /* Always add the workaround BO, it contains a driver identifier at the
407 * beginning quite helpful to debug error states.
409 iris_use_pinned_bo(batch
, screen
->workaround_bo
, false, IRIS_DOMAIN_NONE
);
411 iris_batch_maybe_noop(batch
);
415 iris_batch_free(struct iris_batch
*batch
)
417 struct iris_screen
*screen
= batch
->screen
;
418 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
420 for (int i
= 0; i
< batch
->exec_count
; i
++) {
421 iris_bo_unreference(batch
->exec_bos
[i
]);
423 free(batch
->exec_bos
);
424 free(batch
->validation_list
);
426 ralloc_free(batch
->exec_fences
.mem_ctx
);
428 pipe_resource_reference(&batch
->fine_fences
.ref
.res
, NULL
);
430 util_dynarray_foreach(&batch
->syncobjs
, struct iris_syncobj
*, s
)
431 iris_syncobj_reference(screen
, s
, NULL
);
432 ralloc_free(batch
->syncobjs
.mem_ctx
);
434 iris_fine_fence_reference(batch
->screen
, &batch
->last_fence
, NULL
);
435 u_upload_destroy(batch
->fine_fences
.uploader
);
437 iris_bo_unreference(batch
->bo
);
440 batch
->map_next
= NULL
;
442 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
444 _mesa_hash_table_destroy(batch
->cache
.render
, NULL
);
446 if (unlikely(INTEL_DEBUG
))
447 gen_batch_decode_ctx_finish(&batch
->decoder
);
451 * If we've chained to a secondary batch, or are getting near to the end,
452 * then flush. This should only be called between draws.
455 iris_batch_maybe_flush(struct iris_batch
*batch
, unsigned estimate
)
457 if (batch
->bo
!= batch
->exec_bos
[0] ||
458 iris_batch_bytes_used(batch
) + estimate
>= BATCH_SZ
) {
459 iris_batch_flush(batch
);
464 record_batch_sizes(struct iris_batch
*batch
)
466 unsigned batch_size
= iris_batch_bytes_used(batch
);
468 VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch
->map
, batch_size
));
470 if (batch
->bo
== batch
->exec_bos
[0])
471 batch
->primary_batch_size
= batch_size
;
473 batch
->total_chained_batch_size
+= batch_size
;
477 iris_chain_to_new_batch(struct iris_batch
*batch
)
479 uint32_t *cmd
= batch
->map_next
;
480 uint64_t *addr
= batch
->map_next
+ 4;
481 batch
->map_next
+= 12;
483 record_batch_sizes(batch
);
485 /* No longer held by batch->bo, still held by validation list */
486 iris_bo_unreference(batch
->bo
);
489 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
490 *cmd
= (0x31 << 23) | (1 << 8) | (3 - 2);
491 *addr
= batch
->bo
->gtt_offset
;
495 add_aux_map_bos_to_batch(struct iris_batch
*batch
)
497 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(batch
->screen
->bufmgr
);
501 uint32_t count
= gen_aux_map_get_num_buffers(aux_map_ctx
);
502 ensure_exec_obj_space(batch
, count
);
503 gen_aux_map_fill_bos(aux_map_ctx
,
504 (void**)&batch
->exec_bos
[batch
->exec_count
], count
);
505 for (uint32_t i
= 0; i
< count
; i
++) {
506 struct iris_bo
*bo
= batch
->exec_bos
[batch
->exec_count
];
507 iris_bo_reference(bo
);
508 batch
->validation_list
[batch
->exec_count
] =
509 (struct drm_i915_gem_exec_object2
) {
510 .handle
= bo
->gem_handle
,
511 .offset
= bo
->gtt_offset
,
514 batch
->aperture_space
+= bo
->size
;
520 finish_seqno(struct iris_batch
*batch
)
522 struct iris_fine_fence
*sq
= iris_fine_fence_new(batch
, IRIS_FENCE_END
);
526 iris_fine_fence_reference(batch
->screen
, &batch
->last_fence
, sq
);
527 iris_fine_fence_reference(batch
->screen
, &sq
, NULL
);
531 * Terminate a batch with MI_BATCH_BUFFER_END.
534 iris_finish_batch(struct iris_batch
*batch
)
536 add_aux_map_bos_to_batch(batch
);
540 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
541 uint32_t *map
= batch
->map_next
;
543 map
[0] = (0xA << 23);
545 batch
->map_next
+= 4;
547 record_batch_sizes(batch
);
551 * Replace our current GEM context with a new one (in case it got banned).
554 replace_hw_ctx(struct iris_batch
*batch
)
556 struct iris_screen
*screen
= batch
->screen
;
557 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
559 uint32_t new_ctx
= iris_clone_hw_context(bufmgr
, batch
->hw_ctx_id
);
563 iris_destroy_hw_context(bufmgr
, batch
->hw_ctx_id
);
564 batch
->hw_ctx_id
= new_ctx
;
566 /* Notify the context that state must be re-initialized. */
567 iris_lost_context_state(batch
);
572 enum pipe_reset_status
573 iris_batch_check_for_reset(struct iris_batch
*batch
)
575 struct iris_screen
*screen
= batch
->screen
;
576 enum pipe_reset_status status
= PIPE_NO_RESET
;
577 struct drm_i915_reset_stats stats
= { .ctx_id
= batch
->hw_ctx_id
};
579 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
))
580 DBG("DRM_IOCTL_I915_GET_RESET_STATS failed: %s\n", strerror(errno
));
582 if (stats
.batch_active
!= 0) {
583 /* A reset was observed while a batch from this hardware context was
584 * executing. Assume that this context was at fault.
586 status
= PIPE_GUILTY_CONTEXT_RESET
;
587 } else if (stats
.batch_pending
!= 0) {
588 /* A reset was observed while a batch from this context was in progress,
589 * but the batch was not executing. In this case, assume that the
590 * context was not at fault.
592 status
= PIPE_INNOCENT_CONTEXT_RESET
;
595 if (status
!= PIPE_NO_RESET
) {
596 /* Our context is likely banned, or at least in an unknown state.
597 * Throw it away and start with a fresh context. Ideally this may
598 * catch the problem before our next execbuf fails with -EIO.
600 replace_hw_ctx(batch
);
607 * Submit the batch to the GPU via execbuffer2.
610 submit_batch(struct iris_batch
*batch
)
612 iris_bo_unmap(batch
->bo
);
614 /* The requirement for using I915_EXEC_NO_RELOC are:
616 * The addresses written in the objects must match the corresponding
617 * reloc.gtt_offset which in turn must match the corresponding
620 * Any render targets written to in the batch must be flagged with
623 * To avoid stalling, execobject.offset should match the current
624 * address of that object within the active context.
626 struct drm_i915_gem_execbuffer2 execbuf
= {
627 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
628 .buffer_count
= batch
->exec_count
,
629 .batch_start_offset
= 0,
630 /* This must be QWord aligned. */
631 .batch_len
= ALIGN(batch
->primary_batch_size
, 8),
632 .flags
= I915_EXEC_RENDER
|
634 I915_EXEC_BATCH_FIRST
|
635 I915_EXEC_HANDLE_LUT
,
636 .rsvd1
= batch
->hw_ctx_id
, /* rsvd1 is actually the context ID */
639 if (num_fences(batch
)) {
640 execbuf
.flags
|= I915_EXEC_FENCE_ARRAY
;
641 execbuf
.num_cliprects
= num_fences(batch
);
642 execbuf
.cliprects_ptr
=
643 (uintptr_t)util_dynarray_begin(&batch
->exec_fences
);
647 if (!batch
->screen
->no_hw
&&
648 gen_ioctl(batch
->screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
))
651 for (int i
= 0; i
< batch
->exec_count
; i
++) {
652 struct iris_bo
*bo
= batch
->exec_bos
[i
];
657 iris_bo_unreference(bo
);
664 batch_name_to_string(enum iris_batch_name name
)
666 const char *names
[IRIS_BATCH_COUNT
] = {
667 [IRIS_BATCH_RENDER
] = "render",
668 [IRIS_BATCH_COMPUTE
] = "compute",
674 * Flush the batch buffer, submitting it to the GPU and resetting it so
675 * we're ready to emit the next batch.
678 _iris_batch_flush(struct iris_batch
*batch
, const char *file
, int line
)
680 struct iris_screen
*screen
= batch
->screen
;
682 if (iris_batch_bytes_used(batch
) == 0)
685 iris_finish_batch(batch
);
687 if (unlikely(INTEL_DEBUG
&
688 (DEBUG_BATCH
| DEBUG_SUBMIT
| DEBUG_PIPE_CONTROL
))) {
689 const char *basefile
= strstr(file
, "iris/");
693 fprintf(stderr
, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
694 "(cmds), %4d BOs (%0.1fMb aperture)\n",
695 file
, line
, batch_name_to_string(batch
->name
), batch
->hw_ctx_id
,
696 batch
->total_chained_batch_size
,
697 100.0f
* batch
->total_chained_batch_size
/ BATCH_SZ
,
699 (float) batch
->aperture_space
/ (1024 * 1024));
701 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
702 dump_fence_list(batch
);
703 dump_validation_list(batch
);
706 if (INTEL_DEBUG
& DEBUG_BATCH
) {
711 int ret
= submit_batch(batch
);
713 batch
->exec_count
= 0;
714 batch
->aperture_space
= 0;
716 util_dynarray_foreach(&batch
->syncobjs
, struct iris_syncobj
*, s
)
717 iris_syncobj_reference(screen
, s
, NULL
);
718 util_dynarray_clear(&batch
->syncobjs
);
720 util_dynarray_clear(&batch
->exec_fences
);
722 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
723 dbg_printf("waiting for idle\n");
724 iris_bo_wait_rendering(batch
->bo
); /* if execbuf failed; this is a nop */
727 /* Start a new batch buffer. */
728 iris_batch_reset(batch
);
730 /* EIO means our context is banned. In this case, try and replace it
731 * with a new logical context, and inform iris_context that all state
732 * has been lost and needs to be re-initialized. If this succeeds,
733 * dubiously claim success...
735 if (ret
== -EIO
&& replace_hw_ctx(batch
)) {
736 if (batch
->reset
->reset
) {
737 /* Tell gallium frontends the device is lost and it was our fault. */
738 batch
->reset
->reset(batch
->reset
->data
, PIPE_GUILTY_CONTEXT_RESET
);
746 const bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
747 fprintf(stderr
, "%siris: Failed to submit batchbuffer: %-80s%s\n",
748 color
? "\e[1;41m" : "", strerror(-ret
), color
? "\e[0m" : "");
755 * Does the current batch refer to the given BO?
757 * (In other words, is the BO in the current batch's validation list?)
760 iris_batch_references(struct iris_batch
*batch
, struct iris_bo
*bo
)
762 return find_validation_entry(batch
, bo
) != NULL
;
766 * Updates the state of the noop feature. Returns true if there was a noop
767 * transition that led to state invalidation.
770 iris_batch_prepare_noop(struct iris_batch
*batch
, bool noop_enable
)
772 if (batch
->noop_enabled
== noop_enable
)
775 batch
->noop_enabled
= noop_enable
;
777 iris_batch_flush(batch
);
779 /* If the batch was empty, flush had no effect, so insert our noop. */
780 if (iris_batch_bytes_used(batch
) == 0)
781 iris_batch_maybe_noop(batch
);
783 /* We only need to update the entire state if we transition from noop ->
786 return !batch
->noop_enabled
;