2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * The Iris buffer manager.
28 * XXX: write better comments
31 * - main interface to GEM in the kernel
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
49 #include <sys/types.h>
54 #include "common/gen_aux_map.h"
55 #include "common/gen_clflush.h"
56 #include "dev/gen_debug.h"
57 #include "common/gen_gem.h"
58 #include "dev/gen_device_info.h"
59 #include "main/macros.h"
60 #include "util/debug.h"
61 #include "util/macros.h"
62 #include "util/hash_table.h"
63 #include "util/list.h"
64 #include "util/u_dynarray.h"
66 #include "iris_bufmgr.h"
67 #include "iris_context.h"
70 #include "drm-uapi/i915_drm.h"
80 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
81 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
82 * leaked. All because it does not call VG(cli_free) from its
83 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
84 * and allocation, we mark it available for use upon mmapping and remove
87 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
88 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
90 #define PAGE_SIZE 4096
92 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
95 atomic_add_unless(int *v
, int add
, int unless
)
99 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
105 memzone_name(enum iris_memory_zone memzone
)
107 const char *names
[] = {
108 [IRIS_MEMZONE_SHADER
] = "shader",
109 [IRIS_MEMZONE_BINDER
] = "binder",
110 [IRIS_MEMZONE_SURFACE
] = "surface",
111 [IRIS_MEMZONE_DYNAMIC
] = "dynamic",
112 [IRIS_MEMZONE_OTHER
] = "other",
113 [IRIS_MEMZONE_BORDER_COLOR_POOL
] = "bordercolor",
115 assert(memzone
< ARRAY_SIZE(names
));
116 return names
[memzone
];
119 struct bo_cache_bucket
{
120 /** List of cached BOs. */
121 struct list_head head
;
123 /** Size of this bucket, in bytes. */
132 /** Array of lists of cached gem objects of power-of-two sizes */
133 struct bo_cache_bucket cache_bucket
[14 * 4];
137 struct hash_table
*name_table
;
138 struct hash_table
*handle_table
;
141 * List of BOs which we've effectively freed, but are hanging on to
142 * until they're idle before closing and returning the VMA.
144 struct list_head zombie_list
;
146 struct util_vma_heap vma_allocator
[IRIS_MEMZONE_COUNT
];
151 struct gen_aux_map_context
*aux_map_ctx
;
154 static int bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
157 static void bo_free(struct iris_bo
*bo
);
159 static uint64_t vma_alloc(struct iris_bufmgr
*bufmgr
,
160 enum iris_memory_zone memzone
,
161 uint64_t size
, uint64_t alignment
);
164 key_hash_uint(const void *key
)
166 return _mesa_hash_data(key
, 4);
170 key_uint_equal(const void *a
, const void *b
)
172 return *((unsigned *) a
) == *((unsigned *) b
);
175 static struct iris_bo
*
176 find_and_ref_external_bo(struct hash_table
*ht
, unsigned int key
)
178 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
179 struct iris_bo
*bo
= entry
? entry
->data
: NULL
;
182 assert(bo
->external
);
183 assert(!bo
->reusable
);
185 /* Being non-reusable, the BO cannot be in the cache lists, but it
186 * may be in the zombie list if it had reached zero references, but
187 * we hadn't yet closed it...and then reimported the same BO. If it
188 * is, then remove it since it's now been resurrected.
190 if (bo
->head
.prev
|| bo
->head
.next
)
193 iris_bo_reference(bo
);
200 * This function finds the correct bucket fit for the input size.
201 * The function works with O(1) complexity when the requested size
202 * was queried instead of iterating the size through all the buckets.
204 static struct bo_cache_bucket
*
205 bucket_for_size(struct iris_bufmgr
*bufmgr
, uint64_t size
)
207 /* Calculating the pages and rounding up to the page size. */
208 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
210 /* Row Bucket sizes clz((x-1) | 3) Row Column
211 * in pages stride size
212 * 0: 1 2 3 4 -> 30 30 30 30 4 1
213 * 1: 5 6 7 8 -> 29 29 29 29 4 1
214 * 2: 10 12 14 16 -> 28 28 28 28 8 2
215 * 3: 20 24 28 32 -> 27 27 27 27 16 4
217 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
218 const unsigned row_max_pages
= 4 << row
;
220 /* The '& ~2' is the special case for row 1. In row 1, max pages /
221 * 2 is 2, but the previous row maximum is zero (because there is
222 * no previous row). All row maximum sizes are power of 2, so that
223 * is the only case where that bit will be set.
225 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
226 int col_size_log2
= row
- 1;
227 col_size_log2
+= (col_size_log2
< 0);
229 const unsigned col
= (pages
- prev_row_max_pages
+
230 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
232 /* Calculating the index based on the row and column. */
233 const unsigned index
= (row
* 4) + (col
- 1);
235 return (index
< bufmgr
->num_buckets
) ?
236 &bufmgr
->cache_bucket
[index
] : NULL
;
239 enum iris_memory_zone
240 iris_memzone_for_address(uint64_t address
)
242 STATIC_ASSERT(IRIS_MEMZONE_OTHER_START
> IRIS_MEMZONE_DYNAMIC_START
);
243 STATIC_ASSERT(IRIS_MEMZONE_DYNAMIC_START
> IRIS_MEMZONE_SURFACE_START
);
244 STATIC_ASSERT(IRIS_MEMZONE_SURFACE_START
> IRIS_MEMZONE_BINDER_START
);
245 STATIC_ASSERT(IRIS_MEMZONE_BINDER_START
> IRIS_MEMZONE_SHADER_START
);
246 STATIC_ASSERT(IRIS_BORDER_COLOR_POOL_ADDRESS
== IRIS_MEMZONE_DYNAMIC_START
);
248 if (address
>= IRIS_MEMZONE_OTHER_START
)
249 return IRIS_MEMZONE_OTHER
;
251 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
252 return IRIS_MEMZONE_BORDER_COLOR_POOL
;
254 if (address
> IRIS_MEMZONE_DYNAMIC_START
)
255 return IRIS_MEMZONE_DYNAMIC
;
257 if (address
>= IRIS_MEMZONE_SURFACE_START
)
258 return IRIS_MEMZONE_SURFACE
;
260 if (address
>= IRIS_MEMZONE_BINDER_START
)
261 return IRIS_MEMZONE_BINDER
;
263 return IRIS_MEMZONE_SHADER
;
267 * Allocate a section of virtual memory for a buffer, assigning an address.
269 * This uses either the bucket allocator for the given size, or the large
270 * object allocator (util_vma).
273 vma_alloc(struct iris_bufmgr
*bufmgr
,
274 enum iris_memory_zone memzone
,
278 /* Force alignment to be some number of pages */
279 alignment
= ALIGN(alignment
, PAGE_SIZE
);
281 if (memzone
== IRIS_MEMZONE_BORDER_COLOR_POOL
)
282 return IRIS_BORDER_COLOR_POOL_ADDRESS
;
284 /* The binder handles its own allocations. Return non-zero here. */
285 if (memzone
== IRIS_MEMZONE_BINDER
)
286 return IRIS_MEMZONE_BINDER_START
;
289 util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
, alignment
);
291 assert((addr
>> 48ull) == 0);
292 assert((addr
% alignment
) == 0);
294 return gen_canonical_address(addr
);
298 vma_free(struct iris_bufmgr
*bufmgr
,
302 if (address
== IRIS_BORDER_COLOR_POOL_ADDRESS
)
305 /* Un-canonicalize the address. */
306 address
= gen_48b_address(address
);
311 enum iris_memory_zone memzone
= iris_memzone_for_address(address
);
313 /* The binder handles its own allocations. */
314 if (memzone
== IRIS_MEMZONE_BINDER
)
317 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
321 iris_bo_busy(struct iris_bo
*bo
)
323 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
324 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
326 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
328 bo
->idle
= !busy
.busy
;
335 iris_bo_madvise(struct iris_bo
*bo
, int state
)
337 struct drm_i915_gem_madvise madv
= {
338 .handle
= bo
->gem_handle
,
343 gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
345 return madv
.retained
;
348 static struct iris_bo
*
351 struct iris_bo
*bo
= calloc(1, sizeof(*bo
));
353 bo
->hash
= _mesa_hash_pointer(bo
);
358 static struct iris_bo
*
359 alloc_bo_from_cache(struct iris_bufmgr
*bufmgr
,
360 struct bo_cache_bucket
*bucket
,
362 enum iris_memory_zone memzone
,
369 struct iris_bo
*bo
= NULL
;
371 list_for_each_entry_safe(struct iris_bo
, cur
, &bucket
->head
, head
) {
372 /* Try a little harder to find one that's already in the right memzone */
373 if (match_zone
&& memzone
!= iris_memzone_for_address(cur
->gtt_offset
))
376 /* If the last BO in the cache is busy, there are no idle BOs. Bail,
377 * either falling back to a non-matching memzone, or if that fails,
378 * allocating a fresh buffer.
380 if (iris_bo_busy(cur
))
383 list_del(&cur
->head
);
385 /* Tell the kernel we need this BO. If it still exists, we're done! */
386 if (iris_bo_madvise(cur
, I915_MADV_WILLNEED
)) {
391 /* This BO was purged, throw it out and keep looking. */
398 if (bo
->aux_map_address
) {
399 /* This buffer was associated with an aux-buffer range. We make sure
400 * that buffers are not reused from the cache while the buffer is (busy)
401 * being used by an executing batch. Since we are here, the buffer is no
402 * longer being used by a batch and the buffer was deleted (in order to
403 * end up in the cache). Therefore its old aux-buffer range can be
404 * removed from the aux-map.
406 if (bo
->bufmgr
->aux_map_ctx
)
407 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
409 bo
->aux_map_address
= 0;
412 /* If the cached BO isn't in the right memory zone, or the alignment
413 * isn't sufficient, free the old memory and assign it a new address.
415 if (memzone
!= iris_memzone_for_address(bo
->gtt_offset
) ||
416 bo
->gtt_offset
% alignment
!= 0) {
417 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
418 bo
->gtt_offset
= 0ull;
421 /* Zero the contents if necessary. If this fails, fall back to
422 * allocating a fresh BO, which will always be zeroed by the kernel.
424 if (flags
& BO_ALLOC_ZEROED
) {
425 void *map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
427 memset(map
, 0, bo
->size
);
437 static struct iris_bo
*
438 alloc_fresh_bo(struct iris_bufmgr
*bufmgr
, uint64_t bo_size
)
440 struct iris_bo
*bo
= bo_calloc();
444 struct drm_i915_gem_create create
= { .size
= bo_size
};
446 /* All new BOs we get from the kernel are zeroed, so we don't need to
447 * worry about that here.
449 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
) != 0) {
454 bo
->gem_handle
= create
.handle
;
458 bo
->tiling_mode
= I915_TILING_NONE
;
459 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
462 /* Calling set_domain() will allocate pages for the BO outside of the
463 * struct mutex lock in the kernel, which is more efficient than waiting
464 * to create them during the first execbuf that uses the BO.
466 struct drm_i915_gem_set_domain sd
= {
467 .handle
= bo
->gem_handle
,
468 .read_domains
= I915_GEM_DOMAIN_CPU
,
472 if (gen_ioctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
480 static struct iris_bo
*
481 bo_alloc_internal(struct iris_bufmgr
*bufmgr
,
485 enum iris_memory_zone memzone
,
487 uint32_t tiling_mode
,
491 unsigned int page_size
= getpagesize();
492 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
494 /* Round the size up to the bucket size, or if we don't have caching
495 * at this size, a multiple of the page size.
498 bucket
? bucket
->size
: MAX2(ALIGN(size
, page_size
), page_size
);
500 mtx_lock(&bufmgr
->lock
);
502 /* Get a buffer out of the cache if available. First, we try to find
503 * one with a matching memory zone so we can avoid reallocating VMA.
505 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
, true);
507 /* If that fails, we try for any cached BO, without matching memzone. */
509 bo
= alloc_bo_from_cache(bufmgr
, bucket
, alignment
, memzone
, flags
,
513 mtx_unlock(&bufmgr
->lock
);
516 bo
= alloc_fresh_bo(bufmgr
, bo_size
);
521 if (bo
->gtt_offset
== 0ull) {
522 mtx_lock(&bufmgr
->lock
);
523 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, alignment
);
524 mtx_unlock(&bufmgr
->lock
);
526 if (bo
->gtt_offset
== 0ull)
530 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
534 p_atomic_set(&bo
->refcount
, 1);
535 bo
->reusable
= bucket
&& bufmgr
->bo_reuse
;
536 bo
->cache_coherent
= bufmgr
->has_llc
;
538 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
540 /* By default, capture all driver-internal buffers like shader kernels,
541 * surface states, dynamic states, border colors, and so on.
543 if (memzone
< IRIS_MEMZONE_OTHER
)
544 bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
546 if ((flags
& BO_ALLOC_COHERENT
) && !bo
->cache_coherent
) {
547 struct drm_i915_gem_caching arg
= {
548 .handle
= bo
->gem_handle
,
551 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_CACHING
, &arg
) == 0) {
552 bo
->cache_coherent
= true;
553 bo
->reusable
= false;
557 DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo
->gem_handle
,
558 bo
->name
, memzone_name(memzone
), (unsigned long long) size
);
568 iris_bo_alloc(struct iris_bufmgr
*bufmgr
,
571 enum iris_memory_zone memzone
)
573 return bo_alloc_internal(bufmgr
, name
, size
, 1, memzone
,
574 0, I915_TILING_NONE
, 0);
578 iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
, const char *name
,
579 uint64_t size
, uint32_t alignment
,
580 enum iris_memory_zone memzone
,
581 uint32_t tiling_mode
, uint32_t pitch
, unsigned flags
)
583 return bo_alloc_internal(bufmgr
, name
, size
, alignment
, memzone
,
584 flags
, tiling_mode
, pitch
);
588 iris_bo_create_userptr(struct iris_bufmgr
*bufmgr
, const char *name
,
589 void *ptr
, size_t size
,
590 enum iris_memory_zone memzone
)
598 struct drm_i915_gem_userptr arg
= {
599 .user_ptr
= (uintptr_t)ptr
,
602 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_USERPTR
, &arg
))
604 bo
->gem_handle
= arg
.handle
;
606 /* Check the buffer for validity before we try and use it in a batch */
607 struct drm_i915_gem_set_domain sd
= {
608 .handle
= bo
->gem_handle
,
609 .read_domains
= I915_GEM_DOMAIN_CPU
,
611 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
))
619 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
621 mtx_lock(&bufmgr
->lock
);
622 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, size
, 1);
623 mtx_unlock(&bufmgr
->lock
);
625 if (bo
->gtt_offset
== 0ull)
628 p_atomic_set(&bo
->refcount
, 1);
630 bo
->cache_coherent
= true;
637 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &bo
->gem_handle
);
644 * Returns a iris_bo wrapping the given buffer object handle.
646 * This can be used when one application needs to pass a buffer object
650 iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
651 const char *name
, unsigned int handle
)
655 /* At the moment most applications only have a few named bo.
656 * For instance, in a DRI client only the render buffers passed
657 * between X and the client are named. And since X returns the
658 * alternating names for the front/back buffer a linear search
659 * provides a sufficiently fast match.
661 mtx_lock(&bufmgr
->lock
);
662 bo
= find_and_ref_external_bo(bufmgr
->name_table
, handle
);
666 struct drm_gem_open open_arg
= { .name
= handle
};
667 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
669 DBG("Couldn't reference %s handle 0x%08x: %s\n",
670 name
, handle
, strerror(errno
));
674 /* Now see if someone has used a prime handle to get this
675 * object from the kernel before by looking through the list
676 * again for a matching gem_handle
678 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, open_arg
.handle
);
686 p_atomic_set(&bo
->refcount
, 1);
688 bo
->size
= open_arg
.size
;
691 bo
->gem_handle
= open_arg
.handle
;
693 bo
->global_name
= handle
;
694 bo
->reusable
= false;
696 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
697 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
699 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
700 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
702 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
703 ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
707 bo
->tiling_mode
= get_tiling
.tiling_mode
;
708 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
709 /* XXX stride is unknown */
710 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
713 mtx_unlock(&bufmgr
->lock
);
718 mtx_unlock(&bufmgr
->lock
);
723 bo_close(struct iris_bo
*bo
)
725 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
728 struct hash_entry
*entry
;
730 if (bo
->global_name
) {
731 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
732 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
735 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
736 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
739 /* Close this object */
740 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
741 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
743 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
744 bo
->gem_handle
, bo
->name
, strerror(errno
));
747 if (bo
->aux_map_address
&& bo
->bufmgr
->aux_map_ctx
) {
748 gen_aux_map_unmap_range(bo
->bufmgr
->aux_map_ctx
, bo
->gtt_offset
,
752 /* Return the VMA for reuse */
753 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
759 bo_free(struct iris_bo
*bo
)
761 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
763 if (bo
->map_cpu
&& !bo
->userptr
) {
764 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
765 munmap(bo
->map_cpu
, bo
->size
);
768 VG_NOACCESS(bo
->map_wc
, bo
->size
);
769 munmap(bo
->map_wc
, bo
->size
);
772 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
773 munmap(bo
->map_gtt
, bo
->size
);
779 /* Defer closing the GEM BO and returning the VMA for reuse until the
780 * BO is idle. Just move it to the dead list for now.
782 list_addtail(&bo
->head
, &bufmgr
->zombie_list
);
786 /** Frees all cached buffers significantly older than @time. */
788 cleanup_bo_cache(struct iris_bufmgr
*bufmgr
, time_t time
)
792 if (bufmgr
->time
== time
)
795 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
796 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
798 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
799 if (time
- bo
->free_time
<= 1)
808 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
809 /* Stop once we reach a busy BO - all others past this point were
810 * freed more recently so are likely also busy.
812 if (!bo
->idle
&& iris_bo_busy(bo
))
823 bo_unreference_final(struct iris_bo
*bo
, time_t time
)
825 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
826 struct bo_cache_bucket
*bucket
;
828 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
832 bucket
= bucket_for_size(bufmgr
, bo
->size
);
833 /* Put the buffer into our internal cache for reuse if we can. */
834 if (bucket
&& iris_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
835 bo
->free_time
= time
;
838 list_addtail(&bo
->head
, &bucket
->head
);
845 iris_bo_unreference(struct iris_bo
*bo
)
850 assert(p_atomic_read(&bo
->refcount
) > 0);
852 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
853 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
854 struct timespec time
;
856 clock_gettime(CLOCK_MONOTONIC
, &time
);
858 mtx_lock(&bufmgr
->lock
);
860 if (p_atomic_dec_zero(&bo
->refcount
)) {
861 bo_unreference_final(bo
, time
.tv_sec
);
862 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
865 mtx_unlock(&bufmgr
->lock
);
870 bo_wait_with_stall_warning(struct pipe_debug_callback
*dbg
,
874 bool busy
= dbg
&& !bo
->idle
;
875 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
877 iris_bo_wait_rendering(bo
);
879 if (unlikely(busy
)) {
880 elapsed
+= get_time();
881 if (elapsed
> 1e-5) /* 0.01ms */ {
882 perf_debug(dbg
, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
883 action
, bo
->name
, elapsed
* 1000);
889 print_flags(unsigned flags
)
891 if (flags
& MAP_READ
)
893 if (flags
& MAP_WRITE
)
895 if (flags
& MAP_ASYNC
)
897 if (flags
& MAP_PERSISTENT
)
899 if (flags
& MAP_COHERENT
)
907 iris_bo_map_cpu(struct pipe_debug_callback
*dbg
,
908 struct iris_bo
*bo
, unsigned flags
)
910 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
912 /* We disallow CPU maps for writing to non-coherent buffers, as the
913 * CPU map can become invalidated when a batch is flushed out, which
914 * can happen at unpredictable times. You should use WC maps instead.
916 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
919 DBG("iris_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
921 struct drm_i915_gem_mmap mmap_arg
= {
922 .handle
= bo
->gem_handle
,
925 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
927 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
928 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
931 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
932 VG_DEFINED(map
, bo
->size
);
934 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
935 VG_NOACCESS(map
, bo
->size
);
936 munmap(map
, bo
->size
);
941 DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
945 if (!(flags
& MAP_ASYNC
)) {
946 bo_wait_with_stall_warning(dbg
, bo
, "CPU mapping");
949 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
950 /* If we're reusing an existing CPU mapping, the CPU caches may
951 * contain stale data from the last time we read from that mapping.
952 * (With the BO cache, it might even be data from a previous buffer!)
953 * Even if it's a brand new mapping, the kernel may have zeroed the
954 * buffer via CPU writes.
956 * We need to invalidate those cachelines so that we see the latest
957 * contents, and so long as we only read from the CPU mmap we do not
958 * need to write those cachelines back afterwards.
960 * On LLC, the emprical evidence suggests that writes from the GPU
961 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
962 * cachelines. (Other reads, such as the display engine, bypass the
963 * LLC entirely requiring us to keep dirty pixels for the scanout
966 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
973 iris_bo_map_wc(struct pipe_debug_callback
*dbg
,
974 struct iris_bo
*bo
, unsigned flags
)
976 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
979 DBG("iris_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
981 struct drm_i915_gem_mmap mmap_arg
= {
982 .handle
= bo
->gem_handle
,
984 .flags
= I915_MMAP_WC
,
986 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
988 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
989 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
993 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
994 VG_DEFINED(map
, bo
->size
);
996 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
997 VG_NOACCESS(map
, bo
->size
);
998 munmap(map
, bo
->size
);
1003 DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1006 if (!(flags
& MAP_ASYNC
)) {
1007 bo_wait_with_stall_warning(dbg
, bo
, "WC mapping");
1014 * Perform an uncached mapping via the GTT.
1016 * Write access through the GTT is not quite fully coherent. On low power
1017 * systems especially, like modern Atoms, we can observe reads from RAM before
1018 * the write via GTT has landed. A write memory barrier that flushes the Write
1019 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1020 * read after the write as the GTT write suffers a small delay through the GTT
1021 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1022 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1023 * flushes prior to execbuf submission. However, if we are not informing the
1024 * kernel about our GTT writes, it will not flush before earlier access, such
1025 * as when using the cmdparser. Similarly, we need to be careful if we should
1026 * ever issue a CPU read immediately following a GTT write.
1028 * Telling the kernel about write access also has one more important
1029 * side-effect. Upon receiving notification about the write, it cancels any
1030 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1031 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1032 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1033 * tracking is handled on the buffer exchange instead.
1036 iris_bo_map_gtt(struct pipe_debug_callback
*dbg
,
1037 struct iris_bo
*bo
, unsigned flags
)
1039 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1041 /* Get a mapping of the buffer if we haven't before. */
1042 if (bo
->map_gtt
== NULL
) {
1043 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1045 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1047 /* Get the fake offset back... */
1048 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1050 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1051 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1056 void *map
= mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1057 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1058 if (map
== MAP_FAILED
) {
1059 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1060 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1064 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1065 * already intercept this mmap call. However, for consistency between
1066 * all the mmap paths, we mark the pointer as defined now and mark it
1067 * as inaccessible afterwards.
1069 VG_DEFINED(map
, bo
->size
);
1071 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1072 VG_NOACCESS(map
, bo
->size
);
1073 munmap(map
, bo
->size
);
1076 assert(bo
->map_gtt
);
1078 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1081 if (!(flags
& MAP_ASYNC
)) {
1082 bo_wait_with_stall_warning(dbg
, bo
, "GTT mapping");
1089 can_map_cpu(struct iris_bo
*bo
, unsigned flags
)
1091 if (bo
->cache_coherent
)
1094 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1095 * an LLC platform reads always are coherent (as they are performed via the
1096 * central system agent). It is just the writes that we need to take special
1097 * care to ensure that land in main memory and not stick in the CPU cache.
1099 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1102 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1103 * across batch flushes where the kernel will change cache domains of the
1104 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1106 * Similarly, ASYNC typically means that the buffer will be accessed via
1107 * both the CPU and the GPU simultaneously. Batches may be executed that
1108 * use the BO even while it is mapped. While OpenGL technically disallows
1109 * most drawing while non-persistent mappings are active, we may still use
1110 * the GPU for blits or other operations, causing batches to happen at
1111 * inconvenient times.
1113 * If RAW is set, we expect the caller to be able to handle a WC buffer
1114 * more efficiently than the involuntary clflushes.
1116 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
| MAP_RAW
))
1119 return !(flags
& MAP_WRITE
);
1123 iris_bo_map(struct pipe_debug_callback
*dbg
,
1124 struct iris_bo
*bo
, unsigned flags
)
1126 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1127 return iris_bo_map_gtt(dbg
, bo
, flags
);
1131 if (can_map_cpu(bo
, flags
))
1132 map
= iris_bo_map_cpu(dbg
, bo
, flags
);
1134 map
= iris_bo_map_wc(dbg
, bo
, flags
);
1136 /* Allow the attempt to fail by falling back to the GTT where necessary.
1138 * Not every buffer can be mmaped directly using the CPU (or WC), for
1139 * example buffers that wrap stolen memory or are imported from other
1140 * devices. For those, we have little choice but to use a GTT mmapping.
1141 * However, if we use a slow GTT mmapping for reads where we expected fast
1142 * access, that order of magnitude difference in throughput will be clearly
1143 * expressed by angry users.
1145 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1147 if (!map
&& !(flags
& MAP_RAW
)) {
1148 perf_debug(dbg
, "Fallback GTT mapping for %s with access flags %x\n",
1150 map
= iris_bo_map_gtt(dbg
, bo
, flags
);
1156 /** Waits for all GPU rendering with the object to have completed. */
1158 iris_bo_wait_rendering(struct iris_bo
*bo
)
1160 /* We require a kernel recent enough for WAIT_IOCTL support.
1161 * See intel_init_bufmgr()
1163 iris_bo_wait(bo
, -1);
1167 * Waits on a BO for the given amount of time.
1169 * @bo: buffer object to wait for
1170 * @timeout_ns: amount of time to wait in nanoseconds.
1171 * If value is less than 0, an infinite wait will occur.
1173 * Returns 0 if the wait was successful ie. the last batch referencing the
1174 * object has completed within the allotted time. Otherwise some negative return
1175 * value describes the error. Of particular interest is -ETIME when the wait has
1176 * failed to yield the desired result.
1178 * Similar to iris_bo_wait_rendering except a timeout parameter allows
1179 * the operation to give up after a certain amount of time. Another subtle
1180 * difference is the internal locking semantics are different (this variant does
1181 * not hold the lock for the duration of the wait). This makes the wait subject
1182 * to a larger userspace race window.
1184 * The implementation shall wait until the object is no longer actively
1185 * referenced within a batch buffer at the time of the call. The wait will
1186 * not guarantee that the buffer is re-issued via another thread, or an flinked
1187 * handle. Userspace must make sure this race does not occur if such precision
1190 * Note that some kernels have broken the inifite wait for negative values
1191 * promise, upgrade to latest stable kernels if this is the case.
1194 iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
)
1196 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1198 /* If we know it's idle, don't bother with the kernel round trip */
1199 if (bo
->idle
&& !bo
->external
)
1202 struct drm_i915_gem_wait wait
= {
1203 .bo_handle
= bo
->gem_handle
,
1204 .timeout_ns
= timeout_ns
,
1206 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1216 iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
)
1218 /* Free aux-map buffers */
1219 gen_aux_map_finish(bufmgr
->aux_map_ctx
);
1221 /* bufmgr will no longer try to free VMA entries in the aux-map */
1222 bufmgr
->aux_map_ctx
= NULL
;
1224 mtx_destroy(&bufmgr
->lock
);
1226 /* Free any cached buffer objects we were going to reuse */
1227 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1228 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1230 list_for_each_entry_safe(struct iris_bo
, bo
, &bucket
->head
, head
) {
1231 list_del(&bo
->head
);
1237 /* Close any buffer objects on the dead list. */
1238 list_for_each_entry_safe(struct iris_bo
, bo
, &bufmgr
->zombie_list
, head
) {
1239 list_del(&bo
->head
);
1243 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1244 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1246 for (int z
= 0; z
< IRIS_MEMZONE_COUNT
; z
++) {
1247 if (z
!= IRIS_MEMZONE_BINDER
)
1248 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1255 bo_set_tiling_internal(struct iris_bo
*bo
, uint32_t tiling_mode
,
1258 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1259 struct drm_i915_gem_set_tiling set_tiling
;
1262 if (bo
->global_name
== 0 &&
1263 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1266 memset(&set_tiling
, 0, sizeof(set_tiling
));
1268 /* set_tiling is slightly broken and overwrites the
1269 * input on the error path, so we have to open code
1272 set_tiling
.handle
= bo
->gem_handle
;
1273 set_tiling
.tiling_mode
= tiling_mode
;
1274 set_tiling
.stride
= stride
;
1276 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1277 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1281 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1282 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1283 bo
->stride
= set_tiling
.stride
;
1288 iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
1289 uint32_t *swizzle_mode
)
1291 *tiling_mode
= bo
->tiling_mode
;
1292 *swizzle_mode
= bo
->swizzle_mode
;
1297 iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
,
1298 uint32_t tiling
, uint32_t stride
)
1303 mtx_lock(&bufmgr
->lock
);
1304 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1306 DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
1308 mtx_unlock(&bufmgr
->lock
);
1313 * See if the kernel has already returned this buffer to us. Just as
1314 * for named buffers, we must not create two bo's pointing at the same
1317 bo
= find_and_ref_external_bo(bufmgr
->handle_table
, handle
);
1325 p_atomic_set(&bo
->refcount
, 1);
1327 /* Determine size of bo. The fd-to-handle ioctl really should
1328 * return the size, but it doesn't. If we have kernel 3.12 or
1329 * later, we can lseek on the prime fd to get the size. Older
1330 * kernels will just fail, in which case we fall back to the
1331 * provided (estimated or guess size). */
1332 ret
= lseek(prime_fd
, 0, SEEK_END
);
1336 bo
->bufmgr
= bufmgr
;
1338 bo
->reusable
= false;
1339 bo
->external
= true;
1340 bo
->kflags
= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
| EXEC_OBJECT_PINNED
;
1341 bo
->gtt_offset
= vma_alloc(bufmgr
, IRIS_MEMZONE_OTHER
, bo
->size
, 1);
1342 bo
->gem_handle
= handle
;
1343 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1345 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1346 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1349 if (get_tiling
.tiling_mode
== tiling
|| tiling
> I915_TILING_LAST
) {
1350 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1351 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1352 /* XXX stride is unknown */
1354 if (bo_set_tiling_internal(bo
, tiling
, stride
)) {
1360 mtx_unlock(&bufmgr
->lock
);
1365 mtx_unlock(&bufmgr
->lock
);
1370 iris_bo_make_external_locked(struct iris_bo
*bo
)
1372 if (!bo
->external
) {
1373 _mesa_hash_table_insert(bo
->bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1374 bo
->external
= true;
1375 bo
->reusable
= false;
1380 iris_bo_make_external(struct iris_bo
*bo
)
1382 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1385 assert(!bo
->reusable
);
1389 mtx_lock(&bufmgr
->lock
);
1390 iris_bo_make_external_locked(bo
);
1391 mtx_unlock(&bufmgr
->lock
);
1395 iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
)
1397 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1399 iris_bo_make_external(bo
);
1401 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1402 DRM_CLOEXEC
, prime_fd
) != 0)
1409 iris_bo_export_gem_handle(struct iris_bo
*bo
)
1411 iris_bo_make_external(bo
);
1413 return bo
->gem_handle
;
1417 iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
)
1419 struct iris_bufmgr
*bufmgr
= bo
->bufmgr
;
1421 if (!bo
->global_name
) {
1422 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1424 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1427 mtx_lock(&bufmgr
->lock
);
1428 if (!bo
->global_name
) {
1429 iris_bo_make_external_locked(bo
);
1430 bo
->global_name
= flink
.name
;
1431 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1433 mtx_unlock(&bufmgr
->lock
);
1436 *name
= bo
->global_name
;
1441 add_bucket(struct iris_bufmgr
*bufmgr
, int size
)
1443 unsigned int i
= bufmgr
->num_buckets
;
1445 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1447 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1448 bufmgr
->cache_bucket
[i
].size
= size
;
1449 bufmgr
->num_buckets
++;
1451 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1452 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1453 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1457 init_cache_buckets(struct iris_bufmgr
*bufmgr
)
1459 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1461 /* OK, so power of two buckets was too wasteful of memory.
1462 * Give 3 other sizes between each power of two, to hopefully
1463 * cover things accurately enough. (The alternative is
1464 * probably to just go for exact matching of sizes, and assume
1465 * that for things like composited window resize the tiled
1466 * width/height alignment and rounding of sizes to pages will
1467 * get us useful cache hit rates anyway)
1469 add_bucket(bufmgr
, PAGE_SIZE
);
1470 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1471 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1473 /* Initialize the linked lists for BO reuse cache. */
1474 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1475 add_bucket(bufmgr
, size
);
1477 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1478 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1479 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1484 iris_create_hw_context(struct iris_bufmgr
*bufmgr
)
1486 struct drm_i915_gem_context_create create
= { };
1487 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1489 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1493 /* Upon declaring a GPU hang, the kernel will zap the guilty context
1494 * back to the default logical HW state and attempt to continue on to
1495 * our next submitted batchbuffer. However, our render batches assume
1496 * the previous GPU state is preserved, and only emit commands needed
1497 * to incrementally change that state. In particular, we inherit the
1498 * STATE_BASE_ADDRESS and PIPELINE_SELECT settings, which are critical.
1499 * With default base addresses, our next batches will almost certainly
1500 * cause more GPU hangs, leading to repeated hangs until we're banned
1501 * or the machine is dead.
1503 * Here we tell the kernel not to attempt to recover our context but
1504 * immediately (on the next batchbuffer submission) report that the
1505 * context is lost, and we will do the recovery ourselves. Ideally,
1506 * we'll have two lost batches instead of a continual stream of hangs.
1508 struct drm_i915_gem_context_param p
= {
1509 .ctx_id
= create
.ctx_id
,
1510 .param
= I915_CONTEXT_PARAM_RECOVERABLE
,
1513 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
);
1515 return create
.ctx_id
;
1519 iris_hw_context_get_priority(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1521 struct drm_i915_gem_context_param p
= {
1523 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1525 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
);
1526 return p
.value
; /* on error, return 0 i.e. default priority */
1530 iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
1534 struct drm_i915_gem_context_param p
= {
1536 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1542 if (gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1549 iris_clone_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1551 uint32_t new_ctx
= iris_create_hw_context(bufmgr
);
1554 int priority
= iris_hw_context_get_priority(bufmgr
, ctx_id
);
1555 iris_hw_context_set_priority(bufmgr
, new_ctx
, priority
);
1562 iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
)
1564 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1567 gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1568 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1574 iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1576 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1577 int ret
= gen_ioctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1579 *result
= reg_read
.val
;
1584 iris_gtt_size(int fd
)
1586 /* We use the default (already allocated) context to determine
1587 * the default configuration of the virtual address space.
1589 struct drm_i915_gem_context_param p
= {
1590 .param
= I915_CONTEXT_PARAM_GTT_SIZE
,
1592 if (!gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &p
))
1598 static struct gen_buffer
*
1599 gen_aux_map_buffer_alloc(void *driver_ctx
, uint32_t size
)
1601 struct gen_buffer
*buf
= malloc(sizeof(struct gen_buffer
));
1605 struct iris_bufmgr
*bufmgr
= (struct iris_bufmgr
*)driver_ctx
;
1607 struct iris_bo
*bo
=
1608 iris_bo_alloc_tiled(bufmgr
, "aux-map", size
, 64 * 1024,
1609 IRIS_MEMZONE_OTHER
, I915_TILING_NONE
, 0, 0);
1611 buf
->driver_bo
= bo
;
1612 buf
->gpu
= bo
->gtt_offset
;
1613 buf
->gpu_end
= buf
->gpu
+ bo
->size
;
1614 buf
->map
= iris_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
1619 gen_aux_map_buffer_free(void *driver_ctx
, struct gen_buffer
*buffer
)
1621 iris_bo_unreference((struct iris_bo
*)buffer
->driver_bo
);
1625 static struct gen_mapped_pinned_buffer_alloc aux_map_allocator
= {
1626 .alloc
= gen_aux_map_buffer_alloc
,
1627 .free
= gen_aux_map_buffer_free
,
1631 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1632 * and manage map buffer objections.
1634 * \param fd File descriptor of the opened DRM device.
1636 struct iris_bufmgr
*
1637 iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1639 uint64_t gtt_size
= iris_gtt_size(fd
);
1640 if (gtt_size
<= IRIS_MEMZONE_OTHER_START
)
1643 struct iris_bufmgr
*bufmgr
= calloc(1, sizeof(*bufmgr
));
1647 /* Handles to buffer objects belong to the device fd and are not
1648 * reference counted by the kernel. If the same fd is used by
1649 * multiple parties (threads sharing the same screen bufmgr, or
1650 * even worse the same device fd passed to multiple libraries)
1651 * ownership of those handles is shared by those independent parties.
1653 * Don't do this! Ensure that each library/bufmgr has its own device
1654 * fd so that its namespace does not clash with another.
1658 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1663 list_inithead(&bufmgr
->zombie_list
);
1665 bufmgr
->has_llc
= devinfo
->has_llc
;
1666 bufmgr
->bo_reuse
= bo_reuse
;
1668 STATIC_ASSERT(IRIS_MEMZONE_SHADER_START
== 0ull);
1669 const uint64_t _4GB
= 1ull << 32;
1670 const uint64_t _2GB
= 1ul << 31;
1672 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1673 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1675 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SHADER
],
1676 PAGE_SIZE
, _4GB_minus_1
- PAGE_SIZE
);
1677 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_SURFACE
],
1678 IRIS_MEMZONE_SURFACE_START
,
1679 _4GB_minus_1
- IRIS_MAX_BINDERS
* IRIS_BINDER_SIZE
);
1680 /* TODO: Why does limiting to 2GB help some state items on gen12?
1681 * - CC Viewport Pointer
1682 * - Blend State Pointer
1683 * - Color Calc State Pointer
1685 const uint64_t dynamic_pool_size
=
1686 (devinfo
->gen
>= 12 ? _2GB
: _4GB_minus_1
) - IRIS_BORDER_COLOR_POOL_SIZE
;
1687 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_DYNAMIC
],
1688 IRIS_MEMZONE_DYNAMIC_START
+ IRIS_BORDER_COLOR_POOL_SIZE
,
1691 /* Leave the last 4GB out of the high vma range, so that no state
1692 * base address + size can overflow 48 bits.
1694 util_vma_heap_init(&bufmgr
->vma_allocator
[IRIS_MEMZONE_OTHER
],
1695 IRIS_MEMZONE_OTHER_START
,
1696 (gtt_size
- _4GB
) - IRIS_MEMZONE_OTHER_START
);
1698 init_cache_buckets(bufmgr
);
1700 bufmgr
->name_table
=
1701 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1702 bufmgr
->handle_table
=
1703 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1705 if (devinfo
->gen
>= 12) {
1706 bufmgr
->aux_map_ctx
= gen_aux_map_init(bufmgr
, &aux_map_allocator
,
1708 assert(bufmgr
->aux_map_ctx
);
1715 iris_bufmgr_get_aux_map_context(struct iris_bufmgr
*bufmgr
)
1717 return bufmgr
->aux_map_ctx
;