2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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30 #include <sys/types.h>
31 #include "util/macros.h"
32 #include "util/u_atomic.h"
33 #include "util/list.h"
35 struct gen_device_info
;
36 struct pipe_debug_callback
;
40 * Size in bytes of the buffer object.
42 * The size may be larger than the size originally requested for the
43 * allocation, such as being aligned to page size.
48 * Alignment requirement for object
50 * Used for GTT mapping & pinning the object.
54 /** Buffer manager context associated with this buffer object */
55 struct iris_bufmgr
*bufmgr
;
57 /** The GEM handle for this buffer object. */
61 * Offset of the buffer inside the Graphics Translation Table.
63 * This is effectively our GPU address for the buffer and we use it
64 * as our base for all state pointers into the buffer. However, since the
65 * kernel may be forced to move it around during the course of the
66 * buffer's lifetime, we can only know where the buffer was on the last
67 * execbuf. We presume, and are usually right, that the buffer will not
68 * move and so we use that last offset for the next batch and by doing
69 * so we can avoid having the kernel perform a relocation fixup pass as
70 * our pointers inside the batch will be using the correct base offset.
72 * Since we do use it as a base address for the next batch of pointers,
73 * the kernel treats our offset as a request, and if possible will
74 * arrange the buffer to placed at that address (trying to balance
75 * the cost of buffer migration versus the cost of performing
76 * relocations). Furthermore, we can force the kernel to place the buffer,
77 * or report a failure if we specified a conflicting offset, at our chosen
78 * offset by specifying EXEC_OBJECT_PINNED.
80 * Note the GTT may be either per context, or shared globally across the
81 * system. On a shared system, our buffers have to contend for address
82 * space with both aperture mappings and framebuffers and so are more
83 * likely to be moved. On a full ppGTT system, each batch exists in its
84 * own GTT, and so each buffer may have their own offset within each
90 * The validation list index for this buffer, or -1 when not in a batch.
91 * Note that a single buffer may be in multiple batches (contexts), and
92 * this is a global field, which refers to the last batch using the BO.
93 * It should not be considered authoritative, but can be used to avoid a
94 * linear walk of the validation list in the common case by guessing that
95 * exec_bos[bo->index] == bo and confirming whether that's the case.
100 * Boolean of whether the GPU is definitely not accessing the buffer.
102 * This is only valid when reusable, since non-reusable
103 * buffers are those that have been shared with other
104 * processes, so we don't know their state.
114 * Kenel-assigned global name for this object
116 * List contains both flink named and prime fd'd objects
118 unsigned global_name
;
121 * Current tiling mode
123 uint32_t tiling_mode
;
124 uint32_t swizzle_mode
;
129 /** Mapped address for the buffer, saved across map/unmap cycles */
131 /** GTT virtual address for the buffer, saved across map/unmap cycles */
133 /** WC CPU address for the buffer, saved across map/unmap cycles */
137 struct list_head head
;
140 * Boolean of whether this buffer can be re-used
145 * Boolean of whether this buffer has been shared with an external client.
150 * Boolean of whether this buffer is cache coherent
155 #define BO_ALLOC_BUSY (1<<0)
156 #define BO_ALLOC_ZEROED (1<<1)
159 * Allocate a buffer object.
161 * Buffer objects are not necessarily initially mapped into CPU virtual
162 * address space or graphics device aperture. They must be mapped
163 * using iris_bo_map() to be used by the CPU.
165 struct iris_bo
*iris_bo_alloc(struct iris_bufmgr
*bufmgr
, const char *name
,
166 uint64_t size
, uint64_t alignment
);
169 * Allocate a tiled buffer object.
171 * Alignment for tiled objects is set automatically; the 'flags'
172 * argument provides a hint about how the object will be used initially.
174 * Valid tiling formats are:
179 struct iris_bo
*iris_bo_alloc_tiled(struct iris_bufmgr
*bufmgr
,
182 uint32_t tiling_mode
,
186 /** Takes a reference on a buffer object */
188 iris_bo_reference(struct iris_bo
*bo
)
190 p_atomic_inc(&bo
->refcount
);
194 * Releases a reference on a buffer object, freeing the data if
195 * no references remain.
197 void iris_bo_unreference(struct iris_bo
*bo
);
199 #define MAP_READ 0x01
200 #define MAP_WRITE 0x02
201 #define MAP_ASYNC 0x20
202 #define MAP_PERSISTENT 0x40
203 #define MAP_COHERENT 0x80
205 #define MAP_INTERNAL_MASK (0xff << 24)
206 #define MAP_RAW (0x01 << 24)
209 * Maps the buffer into userspace.
211 * This function will block waiting for any existing execution on the
212 * buffer to complete, first. The resulting mapping is returned.
214 MUST_CHECK
void *iris_bo_map(struct pipe_debug_callback
*dbg
,
215 struct iris_bo
*bo
, unsigned flags
);
218 * Reduces the refcount on the userspace mapping of the buffer
221 static inline int iris_bo_unmap(struct iris_bo
*bo
) { return 0; }
223 /** Write data into an object. */
224 int iris_bo_subdata(struct iris_bo
*bo
, uint64_t offset
,
225 uint64_t size
, const void *data
);
227 * Waits for rendering to an object by the GPU to have completed.
229 * This is not required for any access to the BO by bo_map,
230 * bo_subdata, etc. It is merely a way for the driver to implement
233 void iris_bo_wait_rendering(struct iris_bo
*bo
);
236 * Tears down the buffer manager instance.
238 void iris_bufmgr_destroy(struct iris_bufmgr
*bufmgr
);
241 * Get the current tiling (and resulting swizzling) mode for the bo.
243 * \param buf Buffer to get tiling mode for
244 * \param tiling_mode returned tiling mode
245 * \param swizzle_mode returned swizzling mode
247 int iris_bo_get_tiling(struct iris_bo
*bo
, uint32_t *tiling_mode
,
248 uint32_t *swizzle_mode
);
251 * Create a visible name for a buffer which can be used by other apps
253 * \param buf Buffer to create a name for
254 * \param name Returned name
256 int iris_bo_flink(struct iris_bo
*bo
, uint32_t *name
);
259 * Returns 1 if mapping the buffer for write could cause the process
260 * to block, due to the object being active in the GPU.
262 int iris_bo_busy(struct iris_bo
*bo
);
265 * Specify the volatility of the buffer.
266 * \param bo Buffer to create a name for
267 * \param madv The purgeable status
269 * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
270 * reclaimed under memory pressure. If you subsequently require the buffer,
271 * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
273 * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
274 * marked as I915_MADV_DONTNEED.
276 int iris_bo_madvise(struct iris_bo
*bo
, int madv
);
278 /* drm_bacon_bufmgr_gem.c */
279 struct iris_bufmgr
*iris_bufmgr_init(struct gen_device_info
*devinfo
, int fd
);
280 struct iris_bo
*iris_bo_gem_create_from_name(struct iris_bufmgr
*bufmgr
,
283 void iris_bufmgr_enable_reuse(struct iris_bufmgr
*bufmgr
);
285 int iris_bo_wait(struct iris_bo
*bo
, int64_t timeout_ns
);
287 uint32_t iris_create_hw_context(struct iris_bufmgr
*bufmgr
);
289 #define IRIS_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
290 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
291 #define IRIS_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
293 int iris_hw_context_set_priority(struct iris_bufmgr
*bufmgr
,
294 uint32_t ctx_id
, int priority
);
296 void iris_destroy_hw_context(struct iris_bufmgr
*bufmgr
, uint32_t ctx_id
);
298 int iris_bo_export_dmabuf(struct iris_bo
*bo
, int *prime_fd
);
299 struct iris_bo
*iris_bo_import_dmabuf(struct iris_bufmgr
*bufmgr
, int prime_fd
);
301 uint32_t iris_bo_export_gem_handle(struct iris_bo
*bo
);
303 int iris_reg_read(struct iris_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *out
);
305 int drm_ioctl(int fd
, unsigned long request
, void *arg
);
308 #endif /* IRIS_BUFMGR_H */