2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
79 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
84 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
87 /* Surface state can only record one fast clear color value. Therefore
88 * unless different levels/layers agree on the color it can be used to
89 * represent only single level/layer. Here it will be reserved for the
90 * first slice (level 0, layer 0).
92 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
95 /* Check for partial clear */
96 if (box
->x
> 0 || box
->y
> 0 ||
97 box
->width
< p_res
->width0
||
98 box
->height
< p_res
->height0
) {
102 /* We store clear colors as floats or uints as needed. If there are
103 * texture views in play, the formats will not properly be respected
104 * during resolves because the resolve operations only know about the
105 * resource and not the renderbuffer.
107 if (render_format
!= format
)
110 /* XXX: if (irb->mt->supports_fast_clear)
111 * see intel_miptree_create_for_dri_image()
114 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
120 static union isl_color_value
121 convert_fast_clear_color(struct iris_context
*ice
,
122 struct iris_resource
*res
,
123 const union isl_color_value color
)
125 union isl_color_value override_color
= color
;
126 struct pipe_resource
*p_res
= (void *) res
;
128 const enum pipe_format format
= p_res
->format
;
129 const struct util_format_description
*desc
=
130 util_format_description(format
);
131 unsigned colormask
= util_format_colormask(desc
);
133 if (util_format_is_intensity(format
) ||
134 util_format_is_luminance(format
) ||
135 util_format_is_luminance_alpha(format
)) {
136 override_color
.u32
[1] = override_color
.u32
[0];
137 override_color
.u32
[2] = override_color
.u32
[0];
138 if (util_format_is_intensity(format
))
139 override_color
.u32
[3] = override_color
.u32
[0];
141 for (int chan
= 0; chan
< 3; chan
++) {
142 if (!(colormask
& (1 << chan
)))
143 override_color
.u32
[chan
] = 0;
147 if (util_format_is_unorm(format
)) {
148 for (int i
= 0; i
< 4; i
++)
149 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
150 } else if (util_format_is_snorm(format
)) {
151 for (int i
= 0; i
< 4; i
++)
152 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
153 } else if (util_format_is_pure_uint(format
)) {
154 for (int i
= 0; i
< 4; i
++) {
155 unsigned bits
= util_format_get_component_bits(
156 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
158 uint32_t max
= (1u << bits
) - 1;
159 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
162 } else if (util_format_is_pure_sint(format
)) {
163 for (int i
= 0; i
< 4; i
++) {
164 unsigned bits
= util_format_get_component_bits(
165 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
167 int32_t max
= (1 << (bits
- 1)) - 1;
168 int32_t min
= -(1 << (bits
- 1));
169 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
172 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
173 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
174 /* these packed float formats only store unsigned values */
175 for (int i
= 0; i
< 4; i
++)
176 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
179 if (!(colormask
& 1 << 3)) {
180 if (util_format_is_pure_integer(format
))
181 override_color
.u32
[3] = 1;
183 override_color
.f32
[3] = 1.0f
;
186 /* Handle linear to SRGB conversion */
187 if (util_format_is_srgb(format
)) {
188 for (int i
= 0; i
< 3; i
++) {
189 override_color
.f32
[i
] =
190 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
194 return override_color
;
198 fast_clear_color(struct iris_context
*ice
,
199 struct iris_resource
*res
,
201 const struct pipe_box
*box
,
202 enum isl_format format
,
203 union isl_color_value color
,
204 enum blorp_batch_flags blorp_flags
)
206 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
207 struct pipe_resource
*p_res
= (void *) res
;
208 const enum isl_aux_state aux_state
=
209 iris_resource_get_aux_state(res
, level
, box
->z
);
211 color
= convert_fast_clear_color(ice
, res
, color
);
213 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
217 /* We decided that we are going to fast clear, and the color is
218 * changing. But if we have a predicate bit set, the predication
219 * affects whether we should clear or not, and if we shouldn't, we
220 * also shouldn't update the clear color.
222 * However, we can't simply predicate-update the clear color (the
223 * commands don't support that). And we would lose track of the
224 * color, preventing us from doing some optimizations later.
226 * Since changing the clear color when the predication bit is enabled
227 * is not something that should happen often, we stall on the CPU here
228 * to resolve the predication, and then proceed.
230 iris_resolve_conditional_render(ice
);
231 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
235 iris_resource_set_clear_color(ice
, res
, color
);
237 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
238 * changed, the clear is redundant and can be skipped.
240 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
243 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
245 * "Any transition from any value in {Clear, Render, Resolve} to a
246 * different value in {Clear, Render, Resolve} requires end of pipe
249 * In other words, fast clear ops are not properly synchronized with
250 * other drawing. We need to use a PIPE_CONTROL to ensure that the
251 * contents of the previous draw hit the render target before we resolve
252 * and again afterwards to ensure that the resolve is complete before we
253 * do any more regular drawing.
255 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
257 /* If we reach this point, we need to fast clear to change the state to
258 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
260 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
262 struct blorp_batch blorp_batch
;
263 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
265 struct blorp_surf surf
;
266 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
269 blorp_fast_clear(&blorp_batch
, &surf
, format
,
270 level
, box
->z
, box
->depth
,
271 box
->x
, box
->y
, box
->x
+ box
->width
,
272 box
->y
+ box
->height
);
273 blorp_batch_finish(&blorp_batch
);
274 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
276 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
277 box
->depth
, ISL_AUX_STATE_CLEAR
);
278 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
283 clear_color(struct iris_context
*ice
,
284 struct pipe_resource
*p_res
,
286 const struct pipe_box
*box
,
287 bool render_condition_enabled
,
288 enum isl_format format
,
289 struct isl_swizzle swizzle
,
290 union isl_color_value color
)
292 struct iris_resource
*res
= (void *) p_res
;
294 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
295 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
296 enum blorp_batch_flags blorp_flags
= 0;
298 if (render_condition_enabled
) {
299 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
302 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
303 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
306 iris_batch_maybe_flush(batch
, 1500);
308 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
309 res
->surf
.format
, format
, color
);
310 if (can_fast_clear
) {
311 fast_clear_color(ice
, res
, level
, box
, format
, color
,
316 bool color_write_disable
[4] = { false, false, false, false };
317 enum isl_aux_usage aux_usage
=
318 iris_resource_render_aux_usage(ice
, res
, format
,
321 iris_resource_prepare_render(ice
, batch
, res
, level
,
322 box
->z
, box
->depth
, aux_usage
);
324 struct blorp_surf surf
;
325 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
328 struct blorp_batch blorp_batch
;
329 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
331 if (!isl_format_supports_rendering(devinfo
, format
) &&
332 isl_format_is_rgbx(format
))
333 format
= isl_format_rgbx_to_rgba(format
);
335 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
336 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
337 box
->x
+ box
->width
, box
->y
+ box
->height
,
338 color
, color_write_disable
);
340 blorp_batch_finish(&blorp_batch
);
341 iris_flush_and_dirty_for_history(ice
, batch
, res
);
343 iris_resource_finish_render(ice
, res
, level
,
344 box
->z
, box
->depth
, aux_usage
);
348 can_fast_clear_depth(struct iris_context
*ice
,
349 struct iris_resource
*res
,
351 const struct pipe_box
*box
,
354 struct pipe_resource
*p_res
= (void *) res
;
356 /* Check for partial clears */
357 if (box
->x
> 0 || box
->y
> 0 ||
358 box
->width
< u_minify(p_res
->width0
, level
) ||
359 box
->height
< u_minify(p_res
->height0
, level
)) {
363 if (!(res
->aux
.has_hiz
& (1 << level
)))
370 fast_clear_depth(struct iris_context
*ice
,
371 struct iris_resource
*res
,
373 const struct pipe_box
*box
,
376 struct pipe_resource
*p_res
= (void *) res
;
377 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
379 /* Quantize the clear value to what can be stored in the actual depth
380 * buffer. This makes the following check more accurate because it now
381 * checks if the actual depth bits will match. It also prevents us from
382 * getting a too-accurate depth value during depth testing or when sampling
385 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
386 const uint32_t depth_max
= (1 << nbits
) - 1;
387 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
388 (unsigned)(depth
* depth_max
) / (float)depth_max
;
390 bool update_clear_depth
= false;
392 /* If we're clearing to a new clear value, then we need to resolve any clear
393 * flags out of the HiZ buffer into the real depth buffer.
395 if (res
->aux
.clear_color
.f32
[0] != depth
) {
396 /* We decided that we are going to fast clear, and the color is
397 * changing. But if we have a predicate bit set, the predication
398 * affects whether we should clear or not, and if we shouldn't, we
399 * also shouldn't update the clear color.
401 * However, we can't simply predicate-update the clear color (the
402 * commands don't support that). And we would lose track of the
403 * color, preventing us from doing some optimizations later.
405 * For depth clears, things are even more complicated, because here we
406 * resolve the other levels/layers if they have a different color than
407 * the current one. That resolve can be predicated, but we also set those
408 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
409 * Keeping track of the aux state when predication is involved is just
410 * even more complex, so the easiest thing to do when the fast clear
411 * depth is changing is to stall on the CPU and resolve the predication.
413 iris_resolve_conditional_render(ice
);
414 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
417 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
418 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
421 const unsigned level_layers
=
422 iris_get_num_logical_layers(res
, res_level
);
423 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
424 if (res_level
== level
&&
426 layer
< box
->z
+ box
->depth
) {
427 /* We're going to clear this layer anyway. Leave it alone. */
431 enum isl_aux_state aux_state
=
432 iris_resource_get_aux_state(res
, res_level
, layer
);
434 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
435 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
436 /* This slice doesn't have any fast-cleared bits. */
440 /* If we got here, then the level may have fast-clear bits that
441 * use the old clear value. We need to do a depth resolve to get
442 * rid of their use of the clear value before we can change it.
443 * Fortunately, few applications ever change their depth clear
444 * value so this shouldn't happen often.
446 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
447 ISL_AUX_OP_FULL_RESOLVE
, false);
448 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
449 ISL_AUX_STATE_RESOLVED
);
452 const union isl_color_value clear_value
= { .f32
= {depth
, } };
453 iris_resource_set_clear_color(ice
, res
, clear_value
);
454 update_clear_depth
= true;
457 for (unsigned l
= 0; l
< box
->depth
; l
++) {
458 enum isl_aux_state aux_state
=
459 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
460 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
461 iris_hiz_exec(ice
, batch
, res
, level
,
462 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
467 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
468 ISL_AUX_STATE_CLEAR
);
469 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
473 clear_depth_stencil(struct iris_context
*ice
,
474 struct pipe_resource
*p_res
,
476 const struct pipe_box
*box
,
477 bool render_condition_enabled
,
483 struct iris_resource
*res
= (void *) p_res
;
485 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
486 enum blorp_batch_flags blorp_flags
= 0;
488 if (render_condition_enabled
) {
489 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
492 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
493 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
496 iris_batch_maybe_flush(batch
, 1500);
498 struct iris_resource
*z_res
;
499 struct iris_resource
*stencil_res
;
500 struct blorp_surf z_surf
;
501 struct blorp_surf stencil_surf
;
503 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
504 if (z_res
&& clear_depth
&&
505 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
506 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
507 iris_flush_and_dirty_for_history(ice
, batch
, res
);
512 /* At this point, we might have fast cleared the depth buffer. So if there's
513 * no stencil clear pending, return early.
515 if (!(clear_depth
|| clear_stencil
)) {
520 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
521 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
522 z_res
->aux
.usage
, level
, true);
525 struct blorp_batch blorp_batch
;
526 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
529 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
530 &stencil_res
->base
, stencil_res
->aux
.usage
,
534 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
535 level
, box
->z
, box
->depth
,
538 box
->y
+ box
->height
,
539 clear_depth
&& z_res
, depth
,
540 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
542 blorp_batch_finish(&blorp_batch
);
543 iris_flush_and_dirty_for_history(ice
, batch
, res
);
546 iris_resource_finish_depth(ice
, z_res
, level
,
547 box
->z
, box
->depth
, true);
552 * The pipe->clear() driver hook.
554 * This clears buffers attached to the current draw framebuffer.
557 iris_clear(struct pipe_context
*ctx
,
559 const union pipe_color_union
*p_color
,
563 struct iris_context
*ice
= (void *) ctx
;
564 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
566 assert(buffers
!= 0);
568 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
569 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
570 struct pipe_box box
= {
571 .width
= cso_fb
->width
,
572 .height
= cso_fb
->height
,
573 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
574 .z
= psurf
->u
.tex
.first_layer
,
577 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
578 buffers
& PIPE_CLEAR_DEPTH
,
579 buffers
& PIPE_CLEAR_STENCIL
,
583 if (buffers
& PIPE_CLEAR_COLOR
) {
584 /* pipe_color_union and isl_color_value are interchangeable */
585 union isl_color_value
*color
= (void *) p_color
;
587 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
588 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
589 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
590 struct iris_surface
*isurf
= (void *) psurf
;
591 struct pipe_box box
= {
592 .width
= cso_fb
->width
,
593 .height
= cso_fb
->height
,
594 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
595 .z
= psurf
->u
.tex
.first_layer
,
598 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
599 true, isurf
->view
.format
, isurf
->view
.swizzle
,
607 * The pipe->clear_texture() driver hook.
609 * This clears the given texture resource.
612 iris_clear_texture(struct pipe_context
*ctx
,
613 struct pipe_resource
*p_res
,
615 const struct pipe_box
*box
,
618 struct iris_context
*ice
= (void *) ctx
;
619 struct iris_screen
*screen
= (void *) ctx
->screen
;
620 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
622 if (util_format_is_depth_or_stencil(p_res
->format
)) {
623 const struct util_format_description
*fmt_desc
=
624 util_format_description(p_res
->format
);
629 if (fmt_desc
->unpack_z_float
)
630 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
632 if (fmt_desc
->unpack_s_8uint
)
633 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
635 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
638 union isl_color_value color
;
639 struct iris_resource
*res
= (void *) p_res
;
640 enum isl_format format
= res
->surf
.format
;
642 if (!isl_format_supports_rendering(devinfo
, format
)) {
643 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
644 // XXX: actually just get_copy_format_for_bpb from BLORP
645 // XXX: don't cut and paste this
647 case 8: format
= ISL_FORMAT_R8_UINT
; break;
648 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
649 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
650 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
651 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
652 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
653 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
654 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
656 unreachable("Unknown format bpb");
659 /* No aux surfaces for non-renderable surfaces */
660 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
663 isl_color_value_unpack(&color
, format
, data
);
665 clear_color(ice
, p_res
, level
, box
, true, format
,
666 ISL_SWIZZLE_IDENTITY
, color
);
671 * The pipe->clear_render_target() driver hook.
673 * This clears the given render target surface.
676 iris_clear_render_target(struct pipe_context
*ctx
,
677 struct pipe_surface
*psurf
,
678 const union pipe_color_union
*p_color
,
679 unsigned dst_x
, unsigned dst_y
,
680 unsigned width
, unsigned height
,
681 bool render_condition_enabled
)
683 struct iris_context
*ice
= (void *) ctx
;
684 struct iris_surface
*isurf
= (void *) psurf
;
685 struct pipe_box box
= {
688 .z
= psurf
->u
.tex
.first_layer
,
691 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
694 /* pipe_color_union and isl_color_value are interchangeable */
695 union isl_color_value
*color
= (void *) p_color
;
697 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
698 render_condition_enabled
,
699 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
703 * The pipe->clear_depth_stencil() driver hook.
705 * This clears the given depth/stencil surface.
708 iris_clear_depth_stencil(struct pipe_context
*ctx
,
709 struct pipe_surface
*psurf
,
713 unsigned dst_x
, unsigned dst_y
,
714 unsigned width
, unsigned height
,
715 bool render_condition_enabled
)
717 struct iris_context
*ice
= (void *) ctx
;
718 struct pipe_box box
= {
721 .z
= psurf
->u
.tex
.first_layer
,
724 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
727 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
729 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
730 render_condition_enabled
,
731 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
736 iris_init_clear_functions(struct pipe_context
*ctx
)
738 ctx
->clear
= iris_clear
;
739 ctx
->clear_texture
= iris_clear_texture
;
740 ctx
->clear_render_target
= iris_clear_render_target
;
741 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;