src/gallium/drivers/iris/iris_clear.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_format.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "util/ralloc.h"
  33 #include "iris_context.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36 #include "intel/compiler/brw_compiler.h"
  37 #include "util/format_srgb.h"
  38
  39 static union isl_color_value
  40 convert_fast_clear_color(struct iris_context *ice,
  41                          struct iris_resource *res,
  42                          const union isl_color_value color)
  43 {
  44    union isl_color_value override_color = color;
  45    struct pipe_resource *p_res = (void *) res;
  46
  47    const enum pipe_format format = p_res->format;
  48    const struct util_format_description *desc =
  49       util_format_description(format);
  50    unsigned colormask = util_format_colormask(desc);
  51
  52    /* The sampler doesn't look at the format of the surface when the fast
  53     * clear color is used so we need to implement luminance, intensity and
  54     * missing components manually.
  55     */
  56    if (util_format_is_intensity(format) ||
  57        util_format_is_luminance(format) ||
  58        util_format_is_luminance_alpha(format)) {
  59       override_color.u32[1] = override_color.u32[0];
  60       override_color.u32[2] = override_color.u32[0];
  61       if (util_format_is_intensity(format))
  62          override_color.u32[3] = override_color.u32[0];
  63    } else {
  64       for (int chan = 0; chan < 3; chan++) {
  65          if (!(colormask & (1 << chan)))
  66             override_color.u32[chan] = 0;
  67       }
  68    }
  69
  70    if (util_format_is_unorm(format)) {
  71       for (int i = 0; i < 4; i++)
  72          override_color.f32[i] = CLAMP(override_color.f32[i], 0.0f, 1.0f);
  73    } else if (util_format_is_snorm(format)) {
  74       for (int i = 0; i < 4; i++)
  75          override_color.f32[i] = CLAMP(override_color.f32[i], -1.0f, 1.0f);
  76    } else if (util_format_is_pure_uint(format)) {
  77       for (int i = 0; i < 4; i++) {
  78          unsigned bits = util_format_get_component_bits(
  79             format, UTIL_FORMAT_COLORSPACE_RGB, i);
  80          if (bits < 32) {
  81             uint32_t max = (1u << bits) - 1;
  82             override_color.u32[i] = MIN2(override_color.u32[i], max);
  83          }
  84       }
  85    } else if (util_format_is_pure_sint(format)) {
  86       for (int i = 0; i < 4; i++) {
  87          unsigned bits = util_format_get_component_bits(
  88             format, UTIL_FORMAT_COLORSPACE_RGB, i);
  89          if (bits < 32) {
  90             int32_t max = (1 << (bits - 1)) - 1;
  91             int32_t min = -(1 << (bits - 1));
  92             override_color.i32[i] = CLAMP(override_color.i32[i], min, max);
  93          }
  94       }
  95    } else if (format == PIPE_FORMAT_R11G11B10_FLOAT ||
  96               format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
  97       /* these packed float formats only store unsigned values */
  98       for (int i = 0; i < 4; i++)
  99          override_color.f32[i] = MAX2(override_color.f32[i], 0.0f);
 100    }
 101
 102    if (!(colormask & 1 << 3)) {
 103       if (util_format_is_pure_integer(format))
 104          override_color.u32[3] = 1;
 105       else
 106          override_color.f32[3] = 1.0f;
 107    }
 108
 109    /* Handle linear to SRGB conversion */
 110    if (util_format_is_srgb(format)) {
 111       for (int i = 0; i < 3; i++) {
 112          override_color.f32[i] =
 113             util_format_linear_to_srgb_float(override_color.f32[i]);
 114       }
 115    }
 116
 117    return override_color;
 118 }
 119
 120 static void
 121 clear_color(struct iris_context *ice,
 122             struct pipe_resource *p_res,
 123             unsigned level,
 124             const struct pipe_box *box,
 125             bool render_condition_enabled,
 126             enum isl_format format,
 127             struct isl_swizzle swizzle,
 128             union isl_color_value color)
 129 {
 130    struct iris_resource *res = (void *) p_res;
 131
 132    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 133    const struct gen_device_info *devinfo = &batch->screen->devinfo;
 134    enum blorp_batch_flags blorp_flags = 0;
 135
 136    if (render_condition_enabled) {
 137       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
 138          return;
 139
 140       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
 141          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
 142    }
 143
 144    iris_batch_maybe_flush(batch, 1500);
 145
 146    struct blorp_batch blorp_batch;
 147    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
 148
 149    bool color_write_disable[4] = { false, false, false, false };
 150    enum isl_aux_usage aux_usage =
 151       iris_resource_render_aux_usage(ice, res, format,
 152                                      false, false);
 153
 154    iris_resource_prepare_render(ice, batch, res, level,
 155                                 box->z, box->depth, aux_usage);
 156
 157    struct blorp_surf surf;
 158    iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level,
 159                                 true);
 160
 161    if (!isl_format_supports_rendering(devinfo, format) &&
 162        isl_format_is_rgbx(format))
 163       format = isl_format_rgbx_to_rgba(format);
 164
 165    blorp_clear(&blorp_batch, &surf, format, swizzle,
 166                level, box->z, box->depth, box->x, box->y,
 167                box->x + box->width, box->y + box->height,
 168                color, color_write_disable);
 169
 170    blorp_batch_finish(&blorp_batch);
 171    iris_flush_and_dirty_for_history(ice, batch, res);
 172
 173    iris_resource_finish_render(ice, res, level,
 174                                box->z, box->depth, aux_usage);
 175 }
 176
 177 static bool
 178 can_fast_clear_depth(struct iris_context *ice,
 179                      struct iris_resource *res,
 180                      unsigned level,
 181                      const struct pipe_box *box,
 182                      float depth)
 183 {
 184    struct pipe_resource *p_res = (void *) res;
 185
 186    /* Check for partial clears */
 187    if (box->x > 0 || box->y > 0 ||
 188        box->width < u_minify(p_res->width0, level) ||
 189        box->height < u_minify(p_res->height0, level)) {
 190       return false;
 191    }
 192
 193    if (!(res->aux.has_hiz & (1 << level)))
 194       return false;
 195
 196    return true;
 197 }
 198
 199 static void
 200 fast_clear_depth(struct iris_context *ice,
 201                  struct iris_resource *res,
 202                  unsigned level,
 203                  const struct pipe_box *box,
 204                  float depth)
 205 {
 206    struct pipe_resource *p_res = (void *) res;
 207    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 208
 209    /* Quantize the clear value to what can be stored in the actual depth
 210     * buffer.  This makes the following check more accurate because it now
 211     * checks if the actual depth bits will match.  It also prevents us from
 212     * getting a too-accurate depth value during depth testing or when sampling
 213     * with HiZ enabled.
 214     */
 215    const unsigned nbits = p_res->format == PIPE_FORMAT_Z16_UNORM ? 16 : 24;
 216    const uint32_t depth_max = (1 << nbits) - 1;
 217    depth = p_res->format == PIPE_FORMAT_Z32_FLOAT ? depth :
 218       (unsigned)(depth * depth_max) / (float)depth_max;
 219
 220    /* If we're clearing to a new clear value, then we need to resolve any clear
 221     * flags out of the HiZ buffer into the real depth buffer.
 222     */
 223    if (res->aux.clear_color.f32[0] != depth) {
 224       for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) {
 225          if (!(res->aux.has_hiz & (1 << res_level)))
 226             continue;
 227
 228          const unsigned level_layers =
 229             iris_get_num_logical_layers(res, res_level);
 230          for (unsigned layer = 0; layer < level_layers; layer++) {
 231             if (res_level == level &&
 232                 layer >= box->z &&
 233                 layer < box->z + box->depth) {
 234                /* We're going to clear this layer anyway.  Leave it alone. */
 235                continue;
 236             }
 237
 238             enum isl_aux_state aux_state =
 239                iris_resource_get_aux_state(res, res_level, layer);
 240
 241             if (aux_state != ISL_AUX_STATE_CLEAR &&
 242                 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
 243                /* This slice doesn't have any fast-cleared bits. */
 244                continue;
 245             }
 246
 247             /* If we got here, then the level may have fast-clear bits that
 248              * use the old clear value.  We need to do a depth resolve to get
 249              * rid of their use of the clear value before we can change it.
 250              * Fortunately, few applications ever change their depth clear
 251              * value so this shouldn't happen often.
 252              */
 253             iris_hiz_exec(ice, batch, res, res_level, layer, 1,
 254                           ISL_AUX_OP_FULL_RESOLVE);
 255             iris_resource_set_aux_state(ice, res, res_level, layer, 1,
 256                                         ISL_AUX_STATE_RESOLVED);
 257          }
 258       }
 259       const union isl_color_value clear_color = { .f32 = {depth, } };
 260       iris_resource_set_clear_color(ice, res, clear_color);
 261    }
 262
 263    for (unsigned l = 0; l < box->depth; l++) {
 264       enum isl_aux_state aux_state =
 265          iris_resource_get_aux_state(res, level, box->z + l);
 266       if (aux_state != ISL_AUX_STATE_CLEAR) {
 267          iris_hiz_exec(ice, batch, res, level,
 268                        box->z + l, 1, ISL_AUX_OP_FAST_CLEAR);
 269       }
 270    }
 271
 272    iris_resource_set_aux_state(ice, res, level, box->z, box->depth,
 273                                ISL_AUX_STATE_CLEAR);
 274    ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
 275 }
 276
 277 static void
 278 clear_depth_stencil(struct iris_context *ice,
 279                     struct pipe_resource *p_res,
 280                     unsigned level,
 281                     const struct pipe_box *box,
 282                     bool render_condition_enabled,
 283                     bool clear_depth,
 284                     bool clear_stencil,
 285                     float depth,
 286                     uint8_t stencil)
 287 {
 288    struct iris_resource *res = (void *) p_res;
 289
 290    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 291    enum blorp_batch_flags blorp_flags = 0;
 292
 293    if (render_condition_enabled) {
 294       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
 295          return;
 296
 297       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
 298          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
 299    }
 300
 301    iris_batch_maybe_flush(batch, 1500);
 302
 303    struct iris_resource *z_res;
 304    struct iris_resource *stencil_res;
 305    struct blorp_surf z_surf;
 306    struct blorp_surf stencil_surf;
 307
 308    iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
 309    if (z_res && clear_depth &&
 310        can_fast_clear_depth(ice, z_res, level, box, depth)) {
 311       fast_clear_depth(ice, z_res, level, box, depth);
 312       iris_flush_and_dirty_for_history(ice, batch, res);
 313       clear_depth = false;
 314       z_res = false;
 315    }
 316
 317    /* At this point, we might have fast cleared the depth buffer. So if there's
 318     * no stencil clear pending, return early.
 319     */
 320    if (!(clear_depth || clear_stencil)) {
 321       return;
 322    }
 323
 324    if (z_res) {
 325       iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
 326       iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base,
 327                                    z_res->aux.usage, level, true);
 328    }
 329
 330    struct blorp_batch blorp_batch;
 331    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
 332
 333    if (stencil_res) {
 334       iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf,
 335                                    &stencil_res->base, stencil_res->aux.usage,
 336                                    level, true);
 337    }
 338
 339    blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
 340                              level, box->z, box->depth,
 341                              box->x, box->y,
 342                              box->x + box->width,
 343                              box->y + box->height,
 344                              clear_depth && z_res, depth,
 345                              clear_stencil && stencil_res ? 0xff : 0, stencil);
 346
 347    blorp_batch_finish(&blorp_batch);
 348    iris_flush_and_dirty_for_history(ice, batch, res);
 349
 350    if (z_res) {
 351       iris_resource_finish_depth(ice, z_res, level,
 352                                  box->z, box->depth, true);
 353    }
 354 }
 355
 356 /**
 357  * The pipe->clear() driver hook.
 358  *
 359  * This clears buffers attached to the current draw framebuffer.
 360  */
 361 static void
 362 iris_clear(struct pipe_context *ctx,
 363            unsigned buffers,
 364            const union pipe_color_union *p_color,
 365            double depth,
 366            unsigned stencil)
 367 {
 368    struct iris_context *ice = (void *) ctx;
 369    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
 370
 371    assert(buffers != 0);
 372
 373    if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
 374       struct pipe_surface *psurf = cso_fb->zsbuf;
 375       struct pipe_box box = {
 376          .width = cso_fb->width,
 377          .height = cso_fb->height,
 378          .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 379          .z = psurf->u.tex.first_layer,
 380       };
 381
 382       clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
 383                           buffers & PIPE_CLEAR_DEPTH,
 384                           buffers & PIPE_CLEAR_STENCIL,
 385                           depth, stencil);
 386    }
 387
 388    if (buffers & PIPE_CLEAR_COLOR) {
 389       /* pipe_color_union and isl_color_value are interchangeable */
 390       union isl_color_value *color = (void *) p_color;
 391
 392       for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
 393          if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
 394             struct pipe_surface *psurf = cso_fb->cbufs[i];
 395             struct iris_surface *isurf = (void *) psurf;
 396             struct pipe_box box = {
 397                .width = cso_fb->width,
 398                .height = cso_fb->height,
 399                .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 400                .z = psurf->u.tex.first_layer,
 401             };
 402
 403             clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 404                         true, isurf->view.format, isurf->view.swizzle,
 405                         *color);
 406          }
 407       }
 408    }
 409 }
 410
 411 /**
 412  * The pipe->clear_texture() driver hook.
 413  *
 414  * This clears the given texture resource.
 415  */
 416 static void
 417 iris_clear_texture(struct pipe_context *ctx,
 418                    struct pipe_resource *p_res,
 419                    unsigned level,
 420                    const struct pipe_box *box,
 421                    const void *data)
 422 {
 423    struct iris_context *ice = (void *) ctx;
 424    struct iris_screen *screen = (void *) ctx->screen;
 425    const struct gen_device_info *devinfo = &screen->devinfo;
 426
 427    if (util_format_is_depth_or_stencil(p_res->format)) {
 428       const struct util_format_description *fmt_desc =
 429          util_format_description(p_res->format);
 430
 431       float depth = 0.0;
 432       uint8_t stencil = 0;
 433
 434       if (fmt_desc->unpack_z_float)
 435          fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 436
 437       if (fmt_desc->unpack_s_8uint)
 438          fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 439
 440       clear_depth_stencil(ice, p_res, level, box, true, true, true,
 441                           depth, stencil);
 442    } else {
 443       union isl_color_value color;
 444       struct iris_resource *res = (void *) p_res;
 445       enum isl_format format = res->surf.format;
 446
 447       if (!isl_format_supports_rendering(devinfo, format)) {
 448          const struct isl_format_layout *fmtl = isl_format_get_layout(format);
 449          // XXX: actually just get_copy_format_for_bpb from BLORP
 450          // XXX: don't cut and paste this
 451          switch (fmtl->bpb) {
 452          case 8:   format = ISL_FORMAT_R8_UINT;           break;
 453          case 16:  format = ISL_FORMAT_R8G8_UINT;         break;
 454          case 24:  format = ISL_FORMAT_R8G8B8_UINT;       break;
 455          case 32:  format = ISL_FORMAT_R8G8B8A8_UINT;     break;
 456          case 48:  format = ISL_FORMAT_R16G16B16_UINT;    break;
 457          case 64:  format = ISL_FORMAT_R16G16B16A16_UINT; break;
 458          case 96:  format = ISL_FORMAT_R32G32B32_UINT;    break;
 459          case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
 460          default:
 461             unreachable("Unknown format bpb");
 462          }
 463
 464          /* No aux surfaces for non-renderable surfaces */
 465          assert(res->aux.usage == ISL_AUX_USAGE_NONE);
 466       }
 467
 468       isl_color_value_unpack(&color, format, data);
 469
 470       clear_color(ice, p_res, level, box, true, format,
 471                   ISL_SWIZZLE_IDENTITY, color);
 472    }
 473 }
 474
 475 /**
 476  * The pipe->clear_render_target() driver hook.
 477  *
 478  * This clears the given render target surface.
 479  */
 480 static void
 481 iris_clear_render_target(struct pipe_context *ctx,
 482                          struct pipe_surface *psurf,
 483                          const union pipe_color_union *p_color,
 484                          unsigned dst_x, unsigned dst_y,
 485                          unsigned width, unsigned height,
 486                          bool render_condition_enabled)
 487 {
 488    struct iris_context *ice = (void *) ctx;
 489    struct iris_surface *isurf = (void *) psurf;
 490    struct pipe_box box = {
 491       .x = dst_x,
 492       .y = dst_y,
 493       .z = psurf->u.tex.first_layer,
 494       .width = width,
 495       .height = height,
 496       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 497    };
 498
 499    /* pipe_color_union and isl_color_value are interchangeable */
 500    union isl_color_value *color = (void *) p_color;
 501
 502    clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 503                render_condition_enabled,
 504                isurf->view.format, isurf->view.swizzle, *color);
 505 }
 506
 507 /**
 508  * The pipe->clear_depth_stencil() driver hook.
 509  *
 510  * This clears the given depth/stencil surface.
 511  */
 512 static void
 513 iris_clear_depth_stencil(struct pipe_context *ctx,
 514                          struct pipe_surface *psurf,
 515                          unsigned flags,
 516                          double depth,
 517                          unsigned stencil,
 518                          unsigned dst_x, unsigned dst_y,
 519                          unsigned width, unsigned height,
 520                          bool render_condition_enabled)
 521 {
 522    struct iris_context *ice = (void *) ctx;
 523    struct pipe_box box = {
 524       .x = dst_x,
 525       .y = dst_y,
 526       .z = psurf->u.tex.first_layer,
 527       .width = width,
 528       .height = height,
 529       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 530    };
 531
 532    assert(util_format_is_depth_or_stencil(psurf->texture->format));
 533
 534    clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
 535                        render_condition_enabled,
 536                        flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
 537                        depth, stencil);
 538 }
 539
 540 void
 541 iris_init_clear_functions(struct pipe_context *ctx)
 542 {
 543    ctx->clear = iris_clear;
 544    ctx->clear_texture = iris_clear_texture;
 545    ctx->clear_render_target = iris_clear_render_target;
 546    ctx->clear_depth_stencil = iris_clear_depth_stencil;
 547 }