2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format render_format
,
73 union isl_color_value color
)
75 struct iris_resource
*res
= (void *) p_res
;
77 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
80 if (!isl_aux_usage_has_fast_clears(res
->aux
.usage
))
83 /* Check for partial clear */
84 if (box
->x
> 0 || box
->y
> 0 ||
85 box
->width
< minify(p_res
->width0
, level
) ||
86 box
->height
< minify(p_res
->height0
, level
)) {
90 /* We store clear colors as floats or uints as needed. If there are
91 * texture views in play, the formats will not properly be respected
92 * during resolves because the resolve operations only know about the
93 * resource and not the renderbuffer.
95 if (!iris_render_formats_color_compatible(render_format
, res
->surf
.format
,
100 /* XXX: if (irb->mt->supports_fast_clear)
101 * see intel_miptree_create_for_dri_image()
104 if (!iris_is_color_fast_clear_compatible(ice
, res
->surf
.format
, color
))
110 static union isl_color_value
111 convert_fast_clear_color(struct iris_context
*ice
,
112 struct iris_resource
*res
,
113 enum isl_format render_format
,
114 const union isl_color_value color
)
116 union isl_color_value override_color
= color
;
117 struct pipe_resource
*p_res
= (void *) res
;
119 const enum pipe_format format
= p_res
->format
;
120 const struct util_format_description
*desc
=
121 util_format_description(format
);
122 unsigned colormask
= util_format_colormask(desc
);
124 if (util_format_is_intensity(format
) ||
125 util_format_is_luminance(format
) ||
126 util_format_is_luminance_alpha(format
)) {
127 override_color
.u32
[1] = override_color
.u32
[0];
128 override_color
.u32
[2] = override_color
.u32
[0];
129 if (util_format_is_intensity(format
))
130 override_color
.u32
[3] = override_color
.u32
[0];
132 for (int chan
= 0; chan
< 3; chan
++) {
133 if (!(colormask
& (1 << chan
)))
134 override_color
.u32
[chan
] = 0;
138 if (util_format_is_unorm(format
)) {
139 for (int i
= 0; i
< 4; i
++)
140 override_color
.f32
[i
] = SATURATE(override_color
.f32
[i
]);
141 } else if (util_format_is_snorm(format
)) {
142 for (int i
= 0; i
< 4; i
++)
143 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
144 } else if (util_format_is_pure_uint(format
)) {
145 for (int i
= 0; i
< 4; i
++) {
146 unsigned bits
= util_format_get_component_bits(
147 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
149 uint32_t max
= (1u << bits
) - 1;
150 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
153 } else if (util_format_is_pure_sint(format
)) {
154 for (int i
= 0; i
< 4; i
++) {
155 unsigned bits
= util_format_get_component_bits(
156 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
158 int32_t max
= (1 << (bits
- 1)) - 1;
159 int32_t min
= -(1 << (bits
- 1));
160 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
163 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
164 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
165 /* these packed float formats only store unsigned values */
166 for (int i
= 0; i
< 4; i
++)
167 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
170 if (!(colormask
& 1 << 3)) {
171 if (util_format_is_pure_integer(format
))
172 override_color
.u32
[3] = 1;
174 override_color
.f32
[3] = 1.0f
;
177 /* Handle linear to SRGB conversion */
178 if (isl_format_is_srgb(render_format
)) {
179 for (int i
= 0; i
< 3; i
++) {
180 override_color
.f32
[i
] =
181 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
185 return override_color
;
189 fast_clear_color(struct iris_context
*ice
,
190 struct iris_resource
*res
,
192 const struct pipe_box
*box
,
193 enum isl_format format
,
194 union isl_color_value color
,
195 enum blorp_batch_flags blorp_flags
)
197 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
198 struct pipe_resource
*p_res
= (void *) res
;
199 const enum isl_aux_state aux_state
=
200 iris_resource_get_aux_state(res
, level
, box
->z
);
202 color
= convert_fast_clear_color(ice
, res
, format
, color
);
204 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
208 /* We decided that we are going to fast clear, and the color is
209 * changing. But if we have a predicate bit set, the predication
210 * affects whether we should clear or not, and if we shouldn't, we
211 * also shouldn't update the clear color.
213 * However, we can't simply predicate-update the clear color (the
214 * commands don't support that). And we would lose track of the
215 * color, preventing us from doing some optimizations later.
217 * Since changing the clear color when the predication bit is enabled
218 * is not something that should happen often, we stall on the CPU here
219 * to resolve the predication, and then proceed.
221 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
222 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
225 /* If we are clearing to a new clear value, we need to resolve fast
226 * clears from other levels/layers first, since we can't have different
227 * levels/layers with different fast clear colors.
229 for (unsigned res_lvl
= 0; res_lvl
< res
->surf
.levels
; res_lvl
++) {
230 const unsigned level_layers
=
231 iris_get_num_logical_layers(res
, res_lvl
);
232 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
233 if (res_lvl
== level
&&
235 layer
< box
->z
+ box
->depth
) {
236 /* We're going to clear this layer anyway. Leave it alone. */
240 enum isl_aux_state aux_state
=
241 iris_resource_get_aux_state(res
, res_lvl
, layer
);
243 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
244 aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
&&
245 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
246 /* This slice doesn't have any fast-cleared bits. */
250 /* If we got here, then the level may have fast-clear bits that use
251 * the old clear value. We need to do a color resolve to get rid
252 * of their use of the clear color before we can change it.
253 * Fortunately, few applications ever change their clear color at
254 * different levels/layers, so this shouldn't happen often.
256 iris_resource_prepare_access(ice
, res
,
257 res_lvl
, 1, layer
, 1,
260 perf_debug(&ice
->dbg
,
261 "Resolving resource (%p) level %d, layer %d: color changing from "
262 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
263 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
265 res
->aux
.clear_color
.f32
[0],
266 res
->aux
.clear_color
.f32
[1],
267 res
->aux
.clear_color
.f32
[2],
268 res
->aux
.clear_color
.f32
[3],
269 color
.f32
[0], color
.f32
[1], color
.f32
[2], color
.f32
[3]);
274 iris_resource_set_clear_color(ice
, res
, color
);
276 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
277 * changed, the clear is redundant and can be skipped.
279 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
282 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
284 * "Any transition from any value in {Clear, Render, Resolve} to a
285 * different value in {Clear, Render, Resolve} requires end of pipe
288 * In other words, fast clear ops are not properly synchronized with
289 * other drawing. We need to use a PIPE_CONTROL to ensure that the
290 * contents of the previous draw hit the render target before we resolve
291 * and again afterwards to ensure that the resolve is complete before we
292 * do any more regular drawing.
294 iris_emit_end_of_pipe_sync(batch
,
295 "fast clear: pre-flush",
296 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
298 iris_batch_sync_region_start(batch
);
300 /* If we reach this point, we need to fast clear to change the state to
301 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
303 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
305 struct blorp_batch blorp_batch
;
306 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
308 struct blorp_surf surf
;
309 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
310 p_res
, res
->aux
.usage
, level
, true);
312 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
313 * the clear color during the fast clear, if the surface format is of sRGB
314 * type. We use the linear version of the surface format here to prevent
315 * that from happening, since we already do our own linear -> sRGB
316 * conversion in convert_fast_clear_color().
318 blorp_fast_clear(&blorp_batch
, &surf
, isl_format_srgb_to_linear(format
),
319 ISL_SWIZZLE_IDENTITY
,
320 level
, box
->z
, box
->depth
,
321 box
->x
, box
->y
, box
->x
+ box
->width
,
322 box
->y
+ box
->height
);
323 blorp_batch_finish(&blorp_batch
);
324 iris_emit_end_of_pipe_sync(batch
,
325 "fast clear: post flush",
326 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
327 iris_batch_sync_region_end(batch
);
329 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
330 box
->depth
, ISL_AUX_STATE_CLEAR
);
331 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
332 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
337 clear_color(struct iris_context
*ice
,
338 struct pipe_resource
*p_res
,
340 const struct pipe_box
*box
,
341 bool render_condition_enabled
,
342 enum isl_format format
,
343 struct isl_swizzle swizzle
,
344 union isl_color_value color
)
346 struct iris_resource
*res
= (void *) p_res
;
348 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
349 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
350 enum blorp_batch_flags blorp_flags
= 0;
352 if (render_condition_enabled
) {
353 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
356 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
357 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
360 if (p_res
->target
== PIPE_BUFFER
)
361 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
363 iris_batch_maybe_flush(batch
, 1500);
365 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
367 if (can_fast_clear
) {
368 fast_clear_color(ice
, res
, level
, box
, format
, color
,
373 bool color_write_disable
[4] = { false, false, false, false };
374 enum isl_aux_usage aux_usage
=
375 iris_resource_render_aux_usage(ice
, res
, format
,
378 iris_resource_prepare_render(ice
, batch
, res
, level
,
379 box
->z
, box
->depth
, aux_usage
);
380 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_RENDER_WRITE
);
382 struct blorp_surf surf
;
383 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
384 p_res
, aux_usage
, level
, true);
386 iris_batch_sync_region_start(batch
);
388 struct blorp_batch blorp_batch
;
389 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
391 if (!isl_format_supports_rendering(devinfo
, format
) &&
392 isl_format_is_rgbx(format
))
393 format
= isl_format_rgbx_to_rgba(format
);
395 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
396 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
397 box
->x
+ box
->width
, box
->y
+ box
->height
,
398 color
, color_write_disable
);
400 blorp_batch_finish(&blorp_batch
);
401 iris_batch_sync_region_end(batch
);
403 iris_flush_and_dirty_for_history(ice
, batch
, res
,
404 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
405 "cache history: post color clear");
407 iris_resource_finish_render(ice
, res
, level
,
408 box
->z
, box
->depth
, aux_usage
);
412 can_fast_clear_depth(struct iris_context
*ice
,
413 struct iris_resource
*res
,
415 const struct pipe_box
*box
,
418 struct pipe_resource
*p_res
= (void *) res
;
419 struct pipe_context
*ctx
= (void *) ice
;
420 struct iris_screen
*screen
= (void *) ctx
->screen
;
421 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
423 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
426 /* Check for partial clears */
427 if (box
->x
> 0 || box
->y
> 0 ||
428 box
->width
< u_minify(p_res
->width0
, level
) ||
429 box
->height
< u_minify(p_res
->height0
, level
)) {
433 if (!(res
->aux
.has_hiz
& (1 << level
)))
436 return blorp_can_hiz_clear_depth(devinfo
, &res
->surf
, res
->aux
.usage
,
437 level
, box
->z
, box
->x
, box
->y
,
439 box
->y
+ box
->height
);
443 fast_clear_depth(struct iris_context
*ice
,
444 struct iris_resource
*res
,
446 const struct pipe_box
*box
,
449 struct pipe_resource
*p_res
= (void *) res
;
450 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
452 /* Quantize the clear value to what can be stored in the actual depth
453 * buffer. This makes the following check more accurate because it now
454 * checks if the actual depth bits will match. It also prevents us from
455 * getting a too-accurate depth value during depth testing or when sampling
458 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
459 const uint32_t depth_max
= (1 << nbits
) - 1;
460 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
461 (unsigned)(depth
* depth_max
) / (float)depth_max
;
463 bool update_clear_depth
= false;
465 /* If we're clearing to a new clear value, then we need to resolve any clear
466 * flags out of the HiZ buffer into the real depth buffer.
468 if (res
->aux
.clear_color
.f32
[0] != depth
) {
469 /* We decided that we are going to fast clear, and the color is
470 * changing. But if we have a predicate bit set, the predication
471 * affects whether we should clear or not, and if we shouldn't, we
472 * also shouldn't update the clear color.
474 * However, we can't simply predicate-update the clear color (the
475 * commands don't support that). And we would lose track of the
476 * color, preventing us from doing some optimizations later.
478 * For depth clears, things are even more complicated, because here we
479 * resolve the other levels/layers if they have a different color than
480 * the current one. That resolve can be predicated, but we also set those
481 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
482 * Keeping track of the aux state when predication is involved is just
483 * even more complex, so the easiest thing to do when the fast clear
484 * depth is changing is to stall on the CPU and resolve the predication.
486 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
487 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
490 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
491 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
494 const unsigned level_layers
=
495 iris_get_num_logical_layers(res
, res_level
);
496 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
497 if (res_level
== level
&&
499 layer
< box
->z
+ box
->depth
) {
500 /* We're going to clear this layer anyway. Leave it alone. */
504 enum isl_aux_state aux_state
=
505 iris_resource_get_aux_state(res
, res_level
, layer
);
507 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
508 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
509 /* This slice doesn't have any fast-cleared bits. */
513 /* If we got here, then the level may have fast-clear bits that
514 * use the old clear value. We need to do a depth resolve to get
515 * rid of their use of the clear value before we can change it.
516 * Fortunately, few applications ever change their depth clear
517 * value so this shouldn't happen often.
519 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
520 ISL_AUX_OP_FULL_RESOLVE
, false);
521 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
522 ISL_AUX_STATE_RESOLVED
);
525 const union isl_color_value clear_value
= { .f32
= {depth
, } };
526 iris_resource_set_clear_color(ice
, res
, clear_value
);
527 update_clear_depth
= true;
530 for (unsigned l
= 0; l
< box
->depth
; l
++) {
531 enum isl_aux_state aux_state
=
532 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
533 if (update_clear_depth
|| aux_state
!= ISL_AUX_STATE_CLEAR
) {
534 if (aux_state
== ISL_AUX_STATE_CLEAR
) {
535 perf_debug(&ice
->dbg
, "Performing HiZ clear just to update the "
536 "depth clear value\n");
538 iris_hiz_exec(ice
, batch
, res
, level
,
539 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
544 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
545 ISL_AUX_STATE_CLEAR
);
546 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
550 clear_depth_stencil(struct iris_context
*ice
,
551 struct pipe_resource
*p_res
,
553 const struct pipe_box
*box
,
554 bool render_condition_enabled
,
560 struct iris_resource
*res
= (void *) p_res
;
562 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
563 enum blorp_batch_flags blorp_flags
= 0;
565 if (render_condition_enabled
) {
566 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
569 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
570 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
573 iris_batch_maybe_flush(batch
, 1500);
575 struct iris_resource
*z_res
;
576 struct iris_resource
*stencil_res
;
577 struct blorp_surf z_surf
;
578 struct blorp_surf stencil_surf
;
580 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
581 if (z_res
&& clear_depth
&&
582 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
583 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
584 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
585 "cache history: post fast Z clear");
590 /* At this point, we might have fast cleared the depth buffer. So if there's
591 * no stencil clear pending, return early.
593 if (!(clear_depth
|| clear_stencil
)) {
597 if (clear_depth
&& z_res
) {
598 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
599 iris_emit_buffer_barrier_for(batch
, z_res
->bo
, IRIS_DOMAIN_DEPTH_WRITE
);
600 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
601 &z_surf
, &z_res
->base
, z_res
->aux
.usage
,
605 uint8_t stencil_mask
= clear_stencil
&& stencil_res
? 0xff : 0;
607 iris_resource_prepare_access(ice
, stencil_res
, level
, 1, box
->z
,
608 box
->depth
, stencil_res
->aux
.usage
, false);
609 iris_emit_buffer_barrier_for(batch
, stencil_res
->bo
,
610 IRIS_DOMAIN_DEPTH_WRITE
);
611 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
612 &stencil_surf
, &stencil_res
->base
,
613 stencil_res
->aux
.usage
, level
, true);
616 iris_batch_sync_region_start(batch
);
618 struct blorp_batch blorp_batch
;
619 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
621 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
622 level
, box
->z
, box
->depth
,
625 box
->y
+ box
->height
,
626 clear_depth
&& z_res
, depth
,
627 stencil_mask
, stencil
);
629 blorp_batch_finish(&blorp_batch
);
630 iris_batch_sync_region_end(batch
);
632 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
633 "cache history: post slow ZS clear");
635 if (clear_depth
&& z_res
) {
636 iris_resource_finish_depth(ice
, z_res
, level
,
637 box
->z
, box
->depth
, true);
641 iris_resource_finish_write(ice
, stencil_res
, level
, box
->z
, box
->depth
,
642 stencil_res
->aux
.usage
);
647 * The pipe->clear() driver hook.
649 * This clears buffers attached to the current draw framebuffer.
652 iris_clear(struct pipe_context
*ctx
,
654 const struct pipe_scissor_state
*scissor_state
,
655 const union pipe_color_union
*p_color
,
659 struct iris_context
*ice
= (void *) ctx
;
660 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
662 assert(buffers
!= 0);
664 struct pipe_box box
= {
665 .width
= cso_fb
->width
,
666 .height
= cso_fb
->height
,
670 box
.x
= scissor_state
->minx
;
671 box
.y
= scissor_state
->miny
;
672 box
.width
= MIN2(box
.width
, scissor_state
->maxx
- scissor_state
->minx
);
673 box
.height
= MIN2(box
.height
, scissor_state
->maxy
- scissor_state
->miny
);
676 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
677 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
679 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1;
680 box
.z
= psurf
->u
.tex
.first_layer
,
681 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
682 buffers
& PIPE_CLEAR_DEPTH
,
683 buffers
& PIPE_CLEAR_STENCIL
,
687 if (buffers
& PIPE_CLEAR_COLOR
) {
688 /* pipe_color_union and isl_color_value are interchangeable */
689 union isl_color_value
*color
= (void *) p_color
;
691 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
692 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
693 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
694 struct iris_surface
*isurf
= (void *) psurf
;
695 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
696 box
.z
= psurf
->u
.tex
.first_layer
,
698 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
699 true, isurf
->view
.format
, isurf
->view
.swizzle
,
707 * The pipe->clear_texture() driver hook.
709 * This clears the given texture resource.
712 iris_clear_texture(struct pipe_context
*ctx
,
713 struct pipe_resource
*p_res
,
715 const struct pipe_box
*box
,
718 struct iris_context
*ice
= (void *) ctx
;
719 struct iris_screen
*screen
= (void *) ctx
->screen
;
720 struct iris_resource
*res
= (void *) p_res
;
721 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
723 if (iris_resource_unfinished_aux_import(res
))
724 iris_resource_finish_aux_import(ctx
->screen
, res
);
726 if (util_format_is_depth_or_stencil(p_res
->format
)) {
727 const struct util_format_description
*fmt_desc
=
728 util_format_description(p_res
->format
);
733 if (fmt_desc
->unpack_z_float
)
734 util_format_unpack_z_float(p_res
->format
, &depth
, data
, 1);
736 if (fmt_desc
->unpack_s_8uint
)
737 util_format_unpack_s_8uint(p_res
->format
, &stencil
, data
, 1);
739 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
742 union isl_color_value color
;
743 struct iris_resource
*res
= (void *) p_res
;
744 enum isl_format format
= res
->surf
.format
;
746 if (!isl_format_supports_rendering(devinfo
, format
)) {
747 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
748 // XXX: actually just get_copy_format_for_bpb from BLORP
749 // XXX: don't cut and paste this
751 case 8: format
= ISL_FORMAT_R8_UINT
; break;
752 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
753 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
754 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
755 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
756 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
757 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
758 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
760 unreachable("Unknown format bpb");
763 /* No aux surfaces for non-renderable surfaces */
764 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
767 isl_color_value_unpack(&color
, format
, data
);
769 clear_color(ice
, p_res
, level
, box
, true, format
,
770 ISL_SWIZZLE_IDENTITY
, color
);
775 * The pipe->clear_render_target() driver hook.
777 * This clears the given render target surface.
780 iris_clear_render_target(struct pipe_context
*ctx
,
781 struct pipe_surface
*psurf
,
782 const union pipe_color_union
*p_color
,
783 unsigned dst_x
, unsigned dst_y
,
784 unsigned width
, unsigned height
,
785 bool render_condition_enabled
)
787 struct iris_context
*ice
= (void *) ctx
;
788 struct iris_surface
*isurf
= (void *) psurf
;
789 struct pipe_box box
= {
792 .z
= psurf
->u
.tex
.first_layer
,
795 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
798 /* pipe_color_union and isl_color_value are interchangeable */
799 union isl_color_value
*color
= (void *) p_color
;
801 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
802 render_condition_enabled
,
803 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
807 * The pipe->clear_depth_stencil() driver hook.
809 * This clears the given depth/stencil surface.
812 iris_clear_depth_stencil(struct pipe_context
*ctx
,
813 struct pipe_surface
*psurf
,
817 unsigned dst_x
, unsigned dst_y
,
818 unsigned width
, unsigned height
,
819 bool render_condition_enabled
)
821 struct iris_context
*ice
= (void *) ctx
;
822 struct pipe_box box
= {
825 .z
= psurf
->u
.tex
.first_layer
,
828 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
831 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
833 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
834 render_condition_enabled
,
835 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
840 iris_init_clear_functions(struct pipe_context
*ctx
)
842 ctx
->clear
= iris_clear
;
843 ctx
->clear_texture
= iris_clear_texture
;
844 ctx
->clear_render_target
= iris_clear_render_target
;
845 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;