2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
79 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
81 /* XXX: Need to fix channel select for gen8 before enabling this. */
82 if (devinfo
->gen
!= 9)
85 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
88 /* Surface state can only record one fast clear color value. Therefore
89 * unless different levels/layers agree on the color it can be used to
90 * represent only single level/layer. Here it will be reserved for the
91 * first slice (level 0, layer 0).
93 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
96 /* Check for partial clear */
97 if (box
->x
> 0 || box
->y
> 0 ||
98 box
->width
< p_res
->width0
||
99 box
->height
< p_res
->height0
) {
103 /* We store clear colors as floats or uints as needed. If there are
104 * texture views in play, the formats will not properly be respected
105 * during resolves because the resolve operations only know about the
106 * resource and not the renderbuffer.
108 if (render_format
!= format
)
111 /* XXX: if (irb->mt->supports_fast_clear)
112 * see intel_miptree_create_for_dri_image()
115 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
121 static union isl_color_value
122 convert_fast_clear_color(struct iris_context
*ice
,
123 struct iris_resource
*res
,
124 const union isl_color_value color
,
125 struct isl_swizzle swizzle
)
127 union isl_color_value override_color
= color
;
128 struct pipe_resource
*p_res
= (void *) res
;
130 const enum pipe_format format
= p_res
->format
;
131 const struct util_format_description
*desc
=
132 util_format_description(format
);
133 unsigned colormask
= util_format_colormask(desc
);
135 override_color
= swizzle_color_value(color
, swizzle
);
137 if (util_format_is_unorm(format
)) {
138 for (int i
= 0; i
< 4; i
++)
139 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
140 } else if (util_format_is_snorm(format
)) {
141 for (int i
= 0; i
< 4; i
++)
142 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
143 } else if (util_format_is_pure_uint(format
)) {
144 for (int i
= 0; i
< 4; i
++) {
145 unsigned bits
= util_format_get_component_bits(
146 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
148 uint32_t max
= (1u << bits
) - 1;
149 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
152 } else if (util_format_is_pure_sint(format
)) {
153 for (int i
= 0; i
< 4; i
++) {
154 unsigned bits
= util_format_get_component_bits(
155 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
157 int32_t max
= (1 << (bits
- 1)) - 1;
158 int32_t min
= -(1 << (bits
- 1));
159 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
162 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
163 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
164 /* these packed float formats only store unsigned values */
165 for (int i
= 0; i
< 4; i
++)
166 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
169 if (!(colormask
& 1 << 3)) {
170 if (util_format_is_pure_integer(format
))
171 override_color
.u32
[3] = 1;
173 override_color
.f32
[3] = 1.0f
;
176 /* Handle linear to SRGB conversion */
177 if (util_format_is_srgb(format
)) {
178 for (int i
= 0; i
< 3; i
++) {
179 override_color
.f32
[i
] =
180 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
184 return override_color
;
188 fast_clear_color(struct iris_context
*ice
,
189 struct iris_resource
*res
,
191 const struct pipe_box
*box
,
192 enum isl_format format
,
193 union isl_color_value color
,
194 struct isl_swizzle swizzle
,
195 enum blorp_batch_flags blorp_flags
)
197 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
198 struct pipe_resource
*p_res
= (void *) res
;
199 const enum isl_aux_state aux_state
=
200 iris_resource_get_aux_state(res
, level
, box
->z
);
202 color
= convert_fast_clear_color(ice
, res
, color
, swizzle
);
204 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
205 /* We decided that we are going to fast clear, and the color is
206 * changing. But if we have a predicate bit set, the predication
207 * affects whether we should clear or not, and if we shouldn't, we
208 * also shouldn't update the clear color.
210 * However, we can't simply predicate-update the clear color (the
211 * commands don't support that). And we would lose track of the
212 * color, preventing us from doing some optimizations later.
214 * Since changing the clear color when the predication bit is enabled
215 * is not something that should happen often, we stall on the CPU here
216 * to resolve the predication, and then proceed.
218 iris_resolve_conditional_render(ice
);
219 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
223 iris_resource_set_clear_color(ice
, res
, color
);
225 /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
226 * is redundant and can be skipped.
228 if (aux_state
== ISL_AUX_STATE_CLEAR
)
231 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
233 * "Any transition from any value in {Clear, Render, Resolve} to a
234 * different value in {Clear, Render, Resolve} requires end of pipe
237 * In other words, fast clear ops are not properly synchronized with
238 * other drawing. We need to use a PIPE_CONTROL to ensure that the
239 * contents of the previous draw hit the render target before we resolve
240 * and again afterwards to ensure that the resolve is complete before we
241 * do any more regular drawing.
243 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
245 struct blorp_batch blorp_batch
;
246 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
248 struct blorp_surf surf
;
249 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
252 blorp_fast_clear(&blorp_batch
, &surf
, format
,
253 level
, box
->z
, box
->depth
,
254 box
->x
, box
->y
, box
->x
+ box
->width
,
255 box
->y
+ box
->height
);
256 blorp_batch_finish(&blorp_batch
);
257 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
259 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
260 box
->depth
, ISL_AUX_STATE_CLEAR
);
261 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
266 clear_color(struct iris_context
*ice
,
267 struct pipe_resource
*p_res
,
269 const struct pipe_box
*box
,
270 bool render_condition_enabled
,
271 enum isl_format format
,
272 struct isl_swizzle swizzle
,
273 union isl_color_value color
)
275 struct iris_resource
*res
= (void *) p_res
;
277 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
278 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
279 enum blorp_batch_flags blorp_flags
= BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
281 if (render_condition_enabled
) {
282 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
285 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
286 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
289 iris_batch_maybe_flush(batch
, 1500);
291 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
292 res
->surf
.format
, format
, color
);
293 if (can_fast_clear
) {
294 fast_clear_color(ice
, res
, level
, box
, format
, color
,
295 swizzle
, blorp_flags
);
299 bool color_write_disable
[4] = { false, false, false, false };
300 enum isl_aux_usage aux_usage
=
301 iris_resource_render_aux_usage(ice
, res
, format
,
304 iris_resource_prepare_render(ice
, batch
, res
, level
,
305 box
->z
, box
->depth
, aux_usage
);
307 struct blorp_surf surf
;
308 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
311 struct blorp_batch blorp_batch
;
312 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
314 if (!isl_format_supports_rendering(devinfo
, format
) &&
315 isl_format_is_rgbx(format
))
316 format
= isl_format_rgbx_to_rgba(format
);
318 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
319 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
320 box
->x
+ box
->width
, box
->y
+ box
->height
,
321 color
, color_write_disable
);
323 blorp_batch_finish(&blorp_batch
);
324 iris_flush_and_dirty_for_history(ice
, batch
, res
);
326 iris_resource_finish_render(ice
, res
, level
,
327 box
->z
, box
->depth
, aux_usage
);
331 can_fast_clear_depth(struct iris_context
*ice
,
332 struct iris_resource
*res
,
334 const struct pipe_box
*box
,
337 struct pipe_resource
*p_res
= (void *) res
;
339 /* Check for partial clears */
340 if (box
->x
> 0 || box
->y
> 0 ||
341 box
->width
< u_minify(p_res
->width0
, level
) ||
342 box
->height
< u_minify(p_res
->height0
, level
)) {
346 if (!(res
->aux
.has_hiz
& (1 << level
)))
353 fast_clear_depth(struct iris_context
*ice
,
354 struct iris_resource
*res
,
356 const struct pipe_box
*box
,
359 struct pipe_resource
*p_res
= (void *) res
;
360 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
362 /* Quantize the clear value to what can be stored in the actual depth
363 * buffer. This makes the following check more accurate because it now
364 * checks if the actual depth bits will match. It also prevents us from
365 * getting a too-accurate depth value during depth testing or when sampling
368 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
369 const uint32_t depth_max
= (1 << nbits
) - 1;
370 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
371 (unsigned)(depth
* depth_max
) / (float)depth_max
;
373 /* If we're clearing to a new clear value, then we need to resolve any clear
374 * flags out of the HiZ buffer into the real depth buffer.
376 if (res
->aux
.clear_color
.f32
[0] != depth
) {
377 /* We decided that we are going to fast clear, and the color is
378 * changing. But if we have a predicate bit set, the predication
379 * affects whether we should clear or not, and if we shouldn't, we
380 * also shouldn't update the clear color.
382 * However, we can't simply predicate-update the clear color (the
383 * commands don't support that). And we would lose track of the
384 * color, preventing us from doing some optimizations later.
386 * For depth clears, things are even more complicated, because here we
387 * resolve the other levels/layers if they have a different color than
388 * the current one. That resolve can be predicated, but we also set those
389 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
390 * Keeping track of the aux state when predication is involved is just
391 * even more complex, so the easiest thing to do when the fast clear
392 * depth is changing is to stall on the CPU and resolve the predication.
394 iris_resolve_conditional_render(ice
);
395 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
398 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
399 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
402 const unsigned level_layers
=
403 iris_get_num_logical_layers(res
, res_level
);
404 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
405 if (res_level
== level
&&
407 layer
< box
->z
+ box
->depth
) {
408 /* We're going to clear this layer anyway. Leave it alone. */
412 enum isl_aux_state aux_state
=
413 iris_resource_get_aux_state(res
, res_level
, layer
);
415 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
416 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
417 /* This slice doesn't have any fast-cleared bits. */
421 /* If we got here, then the level may have fast-clear bits that
422 * use the old clear value. We need to do a depth resolve to get
423 * rid of their use of the clear value before we can change it.
424 * Fortunately, few applications ever change their depth clear
425 * value so this shouldn't happen often.
427 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
428 ISL_AUX_OP_FULL_RESOLVE
);
429 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
430 ISL_AUX_STATE_RESOLVED
);
433 const union isl_color_value clear_value
= { .f32
= {depth
, } };
434 iris_resource_set_clear_color(ice
, res
, clear_value
);
437 for (unsigned l
= 0; l
< box
->depth
; l
++) {
438 enum isl_aux_state aux_state
=
439 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
440 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
441 iris_hiz_exec(ice
, batch
, res
, level
,
442 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
);
446 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
447 ISL_AUX_STATE_CLEAR
);
448 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
452 clear_depth_stencil(struct iris_context
*ice
,
453 struct pipe_resource
*p_res
,
455 const struct pipe_box
*box
,
456 bool render_condition_enabled
,
462 struct iris_resource
*res
= (void *) p_res
;
464 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
465 enum blorp_batch_flags blorp_flags
= 0;
467 if (render_condition_enabled
) {
468 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
471 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
472 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
475 iris_batch_maybe_flush(batch
, 1500);
477 struct iris_resource
*z_res
;
478 struct iris_resource
*stencil_res
;
479 struct blorp_surf z_surf
;
480 struct blorp_surf stencil_surf
;
482 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
483 if (z_res
&& clear_depth
&&
484 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
485 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
486 iris_flush_and_dirty_for_history(ice
, batch
, res
);
491 /* At this point, we might have fast cleared the depth buffer. So if there's
492 * no stencil clear pending, return early.
494 if (!(clear_depth
|| clear_stencil
)) {
499 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
500 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
501 z_res
->aux
.usage
, level
, true);
504 struct blorp_batch blorp_batch
;
505 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
508 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
509 &stencil_res
->base
, stencil_res
->aux
.usage
,
513 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
514 level
, box
->z
, box
->depth
,
517 box
->y
+ box
->height
,
518 clear_depth
&& z_res
, depth
,
519 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
521 blorp_batch_finish(&blorp_batch
);
522 iris_flush_and_dirty_for_history(ice
, batch
, res
);
525 iris_resource_finish_depth(ice
, z_res
, level
,
526 box
->z
, box
->depth
, true);
531 * The pipe->clear() driver hook.
533 * This clears buffers attached to the current draw framebuffer.
536 iris_clear(struct pipe_context
*ctx
,
538 const union pipe_color_union
*p_color
,
542 struct iris_context
*ice
= (void *) ctx
;
543 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
545 assert(buffers
!= 0);
547 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
548 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
549 struct pipe_box box
= {
550 .width
= cso_fb
->width
,
551 .height
= cso_fb
->height
,
552 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
553 .z
= psurf
->u
.tex
.first_layer
,
556 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
557 buffers
& PIPE_CLEAR_DEPTH
,
558 buffers
& PIPE_CLEAR_STENCIL
,
562 if (buffers
& PIPE_CLEAR_COLOR
) {
563 /* pipe_color_union and isl_color_value are interchangeable */
564 union isl_color_value
*color
= (void *) p_color
;
566 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
567 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
568 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
569 struct iris_surface
*isurf
= (void *) psurf
;
570 struct pipe_box box
= {
571 .width
= cso_fb
->width
,
572 .height
= cso_fb
->height
,
573 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
574 .z
= psurf
->u
.tex
.first_layer
,
577 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
578 true, isurf
->view
.format
, isurf
->view
.swizzle
,
586 * The pipe->clear_texture() driver hook.
588 * This clears the given texture resource.
591 iris_clear_texture(struct pipe_context
*ctx
,
592 struct pipe_resource
*p_res
,
594 const struct pipe_box
*box
,
597 struct iris_context
*ice
= (void *) ctx
;
598 struct iris_screen
*screen
= (void *) ctx
->screen
;
599 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
601 if (util_format_is_depth_or_stencil(p_res
->format
)) {
602 const struct util_format_description
*fmt_desc
=
603 util_format_description(p_res
->format
);
608 if (fmt_desc
->unpack_z_float
)
609 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
611 if (fmt_desc
->unpack_s_8uint
)
612 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
614 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
617 union isl_color_value color
;
618 struct iris_resource
*res
= (void *) p_res
;
619 enum isl_format format
= res
->surf
.format
;
621 if (!isl_format_supports_rendering(devinfo
, format
)) {
622 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
623 // XXX: actually just get_copy_format_for_bpb from BLORP
624 // XXX: don't cut and paste this
626 case 8: format
= ISL_FORMAT_R8_UINT
; break;
627 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
628 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
629 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
630 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
631 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
632 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
633 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
635 unreachable("Unknown format bpb");
638 /* No aux surfaces for non-renderable surfaces */
639 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
642 isl_color_value_unpack(&color
, format
, data
);
644 clear_color(ice
, p_res
, level
, box
, true, format
,
645 ISL_SWIZZLE_IDENTITY
, color
);
650 * The pipe->clear_render_target() driver hook.
652 * This clears the given render target surface.
655 iris_clear_render_target(struct pipe_context
*ctx
,
656 struct pipe_surface
*psurf
,
657 const union pipe_color_union
*p_color
,
658 unsigned dst_x
, unsigned dst_y
,
659 unsigned width
, unsigned height
,
660 bool render_condition_enabled
)
662 struct iris_context
*ice
= (void *) ctx
;
663 struct iris_surface
*isurf
= (void *) psurf
;
664 struct pipe_box box
= {
667 .z
= psurf
->u
.tex
.first_layer
,
670 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
673 /* pipe_color_union and isl_color_value are interchangeable */
674 union isl_color_value
*color
= (void *) p_color
;
676 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
677 render_condition_enabled
,
678 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
682 * The pipe->clear_depth_stencil() driver hook.
684 * This clears the given depth/stencil surface.
687 iris_clear_depth_stencil(struct pipe_context
*ctx
,
688 struct pipe_surface
*psurf
,
692 unsigned dst_x
, unsigned dst_y
,
693 unsigned width
, unsigned height
,
694 bool render_condition_enabled
)
696 struct iris_context
*ice
= (void *) ctx
;
697 struct pipe_box box
= {
700 .z
= psurf
->u
.tex
.first_layer
,
703 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
706 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
708 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
709 render_condition_enabled
,
710 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
715 iris_init_clear_functions(struct pipe_context
*ctx
)
717 ctx
->clear
= iris_clear
;
718 ctx
->clear_texture
= iris_clear_texture
;
719 ctx
->clear_render_target
= iris_clear_render_target
;
720 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;