2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
81 if (!isl_aux_usage_has_fast_clears(res
->aux
.usage
))
84 /* Check for partial clear */
85 if (box
->x
> 0 || box
->y
> 0 ||
86 box
->width
< minify(p_res
->width0
, level
) ||
87 box
->height
< minify(p_res
->height0
, level
)) {
91 /* We store clear colors as floats or uints as needed. If there are
92 * texture views in play, the formats will not properly be respected
93 * during resolves because the resolve operations only know about the
94 * resource and not the renderbuffer.
96 if (isl_format_srgb_to_linear(render_format
) !=
97 isl_format_srgb_to_linear(format
)) {
101 /* XXX: if (irb->mt->supports_fast_clear)
102 * see intel_miptree_create_for_dri_image()
105 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
111 static union isl_color_value
112 convert_fast_clear_color(struct iris_context
*ice
,
113 struct iris_resource
*res
,
114 enum isl_format render_format
,
115 const union isl_color_value color
)
117 union isl_color_value override_color
= color
;
118 struct pipe_resource
*p_res
= (void *) res
;
120 const enum pipe_format format
= p_res
->format
;
121 const struct util_format_description
*desc
=
122 util_format_description(format
);
123 unsigned colormask
= util_format_colormask(desc
);
125 if (util_format_is_intensity(format
) ||
126 util_format_is_luminance(format
) ||
127 util_format_is_luminance_alpha(format
)) {
128 override_color
.u32
[1] = override_color
.u32
[0];
129 override_color
.u32
[2] = override_color
.u32
[0];
130 if (util_format_is_intensity(format
))
131 override_color
.u32
[3] = override_color
.u32
[0];
133 for (int chan
= 0; chan
< 3; chan
++) {
134 if (!(colormask
& (1 << chan
)))
135 override_color
.u32
[chan
] = 0;
139 if (util_format_is_unorm(format
)) {
140 for (int i
= 0; i
< 4; i
++)
141 override_color
.f32
[i
] = SATURATE(override_color
.f32
[i
]);
142 } else if (util_format_is_snorm(format
)) {
143 for (int i
= 0; i
< 4; i
++)
144 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
145 } else if (util_format_is_pure_uint(format
)) {
146 for (int i
= 0; i
< 4; i
++) {
147 unsigned bits
= util_format_get_component_bits(
148 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
150 uint32_t max
= (1u << bits
) - 1;
151 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
154 } else if (util_format_is_pure_sint(format
)) {
155 for (int i
= 0; i
< 4; i
++) {
156 unsigned bits
= util_format_get_component_bits(
157 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
159 int32_t max
= (1 << (bits
- 1)) - 1;
160 int32_t min
= -(1 << (bits
- 1));
161 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
164 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
165 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
166 /* these packed float formats only store unsigned values */
167 for (int i
= 0; i
< 4; i
++)
168 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
171 if (!(colormask
& 1 << 3)) {
172 if (util_format_is_pure_integer(format
))
173 override_color
.u32
[3] = 1;
175 override_color
.f32
[3] = 1.0f
;
178 /* Handle linear to SRGB conversion */
179 if (isl_format_is_srgb(render_format
)) {
180 for (int i
= 0; i
< 3; i
++) {
181 override_color
.f32
[i
] =
182 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
186 return override_color
;
190 fast_clear_color(struct iris_context
*ice
,
191 struct iris_resource
*res
,
193 const struct pipe_box
*box
,
194 enum isl_format format
,
195 union isl_color_value color
,
196 enum blorp_batch_flags blorp_flags
)
198 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
199 struct pipe_resource
*p_res
= (void *) res
;
200 const enum isl_aux_state aux_state
=
201 iris_resource_get_aux_state(res
, level
, box
->z
);
203 color
= convert_fast_clear_color(ice
, res
, format
, color
);
205 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
209 /* We decided that we are going to fast clear, and the color is
210 * changing. But if we have a predicate bit set, the predication
211 * affects whether we should clear or not, and if we shouldn't, we
212 * also shouldn't update the clear color.
214 * However, we can't simply predicate-update the clear color (the
215 * commands don't support that). And we would lose track of the
216 * color, preventing us from doing some optimizations later.
218 * Since changing the clear color when the predication bit is enabled
219 * is not something that should happen often, we stall on the CPU here
220 * to resolve the predication, and then proceed.
222 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
223 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
226 /* If we are clearing to a new clear value, we need to resolve fast
227 * clears from other levels/layers first, since we can't have different
228 * levels/layers with different fast clear colors.
230 for (unsigned res_lvl
= 0; res_lvl
< res
->surf
.levels
; res_lvl
++) {
231 const unsigned level_layers
=
232 iris_get_num_logical_layers(res
, res_lvl
);
233 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
234 if (res_lvl
== level
&&
236 layer
< box
->z
+ box
->depth
) {
237 /* We're going to clear this layer anyway. Leave it alone. */
241 enum isl_aux_state aux_state
=
242 iris_resource_get_aux_state(res
, res_lvl
, layer
);
244 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
245 aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
&&
246 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
247 /* This slice doesn't have any fast-cleared bits. */
251 /* If we got here, then the level may have fast-clear bits that use
252 * the old clear value. We need to do a color resolve to get rid
253 * of their use of the clear color before we can change it.
254 * Fortunately, few applications ever change their clear color at
255 * different levels/layers, so this shouldn't happen often.
257 iris_resource_prepare_access(ice
, res
,
258 res_lvl
, 1, layer
, 1,
261 perf_debug(&ice
->dbg
,
262 "Resolving resource (%p) level %d, layer %d: color changing from "
263 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
264 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
266 res
->aux
.clear_color
.f32
[0],
267 res
->aux
.clear_color
.f32
[1],
268 res
->aux
.clear_color
.f32
[2],
269 res
->aux
.clear_color
.f32
[3],
270 color
.f32
[0], color
.f32
[1], color
.f32
[2], color
.f32
[3]);
275 iris_resource_set_clear_color(ice
, res
, color
);
277 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
278 * changed, the clear is redundant and can be skipped.
280 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
283 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
285 * "Any transition from any value in {Clear, Render, Resolve} to a
286 * different value in {Clear, Render, Resolve} requires end of pipe
289 * In other words, fast clear ops are not properly synchronized with
290 * other drawing. We need to use a PIPE_CONTROL to ensure that the
291 * contents of the previous draw hit the render target before we resolve
292 * and again afterwards to ensure that the resolve is complete before we
293 * do any more regular drawing.
295 iris_emit_end_of_pipe_sync(batch
,
296 "fast clear: pre-flush",
297 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
299 iris_batch_sync_region_start(batch
);
301 /* If we reach this point, we need to fast clear to change the state to
302 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
304 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
306 struct blorp_batch blorp_batch
;
307 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
309 struct blorp_surf surf
;
310 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
311 p_res
, res
->aux
.usage
, level
, true);
313 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
314 * the clear color during the fast clear, if the surface format is of sRGB
315 * type. We use the linear version of the surface format here to prevent
316 * that from happening, since we already do our own linear -> sRGB
317 * conversion in convert_fast_clear_color().
319 blorp_fast_clear(&blorp_batch
, &surf
, isl_format_srgb_to_linear(format
),
320 ISL_SWIZZLE_IDENTITY
,
321 level
, box
->z
, box
->depth
,
322 box
->x
, box
->y
, box
->x
+ box
->width
,
323 box
->y
+ box
->height
);
324 blorp_batch_finish(&blorp_batch
);
325 iris_emit_end_of_pipe_sync(batch
,
326 "fast clear: post flush",
327 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
328 iris_batch_sync_region_end(batch
);
330 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
331 box
->depth
, ISL_AUX_STATE_CLEAR
);
332 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
333 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
338 clear_color(struct iris_context
*ice
,
339 struct pipe_resource
*p_res
,
341 const struct pipe_box
*box
,
342 bool render_condition_enabled
,
343 enum isl_format format
,
344 struct isl_swizzle swizzle
,
345 union isl_color_value color
)
347 struct iris_resource
*res
= (void *) p_res
;
349 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
350 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
351 enum blorp_batch_flags blorp_flags
= 0;
353 if (render_condition_enabled
) {
354 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
357 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
358 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
361 if (p_res
->target
== PIPE_BUFFER
)
362 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
364 iris_batch_maybe_flush(batch
, 1500);
366 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
367 res
->surf
.format
, format
, color
);
368 if (can_fast_clear
) {
369 fast_clear_color(ice
, res
, level
, box
, format
, color
,
374 bool color_write_disable
[4] = { false, false, false, false };
375 enum isl_aux_usage aux_usage
=
376 iris_resource_render_aux_usage(ice
, res
, format
,
379 iris_resource_prepare_render(ice
, batch
, res
, level
,
380 box
->z
, box
->depth
, aux_usage
);
382 struct blorp_surf surf
;
383 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
384 p_res
, aux_usage
, level
, true);
386 iris_batch_sync_region_start(batch
);
388 struct blorp_batch blorp_batch
;
389 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
391 if (!isl_format_supports_rendering(devinfo
, format
) &&
392 isl_format_is_rgbx(format
))
393 format
= isl_format_rgbx_to_rgba(format
);
395 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
396 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
397 box
->x
+ box
->width
, box
->y
+ box
->height
,
398 color
, color_write_disable
);
400 blorp_batch_finish(&blorp_batch
);
401 iris_batch_sync_region_end(batch
);
403 iris_flush_and_dirty_for_history(ice
, batch
, res
,
404 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
405 "cache history: post color clear");
407 iris_resource_finish_render(ice
, res
, level
,
408 box
->z
, box
->depth
, aux_usage
);
412 can_fast_clear_depth(struct iris_context
*ice
,
413 struct iris_resource
*res
,
415 const struct pipe_box
*box
,
418 struct pipe_resource
*p_res
= (void *) res
;
419 struct pipe_context
*ctx
= (void *) ice
;
420 struct iris_screen
*screen
= (void *) ctx
->screen
;
421 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
423 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
426 /* Check for partial clears */
427 if (box
->x
> 0 || box
->y
> 0 ||
428 box
->width
< u_minify(p_res
->width0
, level
) ||
429 box
->height
< u_minify(p_res
->height0
, level
)) {
433 if (!(res
->aux
.has_hiz
& (1 << level
)))
436 return blorp_can_hiz_clear_depth(devinfo
, &res
->surf
, res
->aux
.usage
,
437 level
, box
->z
, box
->x
, box
->y
,
439 box
->y
+ box
->height
);
443 fast_clear_depth(struct iris_context
*ice
,
444 struct iris_resource
*res
,
446 const struct pipe_box
*box
,
449 struct pipe_resource
*p_res
= (void *) res
;
450 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
452 /* Quantize the clear value to what can be stored in the actual depth
453 * buffer. This makes the following check more accurate because it now
454 * checks if the actual depth bits will match. It also prevents us from
455 * getting a too-accurate depth value during depth testing or when sampling
458 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
459 const uint32_t depth_max
= (1 << nbits
) - 1;
460 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
461 (unsigned)(depth
* depth_max
) / (float)depth_max
;
463 bool update_clear_depth
= false;
465 /* If we're clearing to a new clear value, then we need to resolve any clear
466 * flags out of the HiZ buffer into the real depth buffer.
468 if (res
->aux
.clear_color
.f32
[0] != depth
) {
469 /* We decided that we are going to fast clear, and the color is
470 * changing. But if we have a predicate bit set, the predication
471 * affects whether we should clear or not, and if we shouldn't, we
472 * also shouldn't update the clear color.
474 * However, we can't simply predicate-update the clear color (the
475 * commands don't support that). And we would lose track of the
476 * color, preventing us from doing some optimizations later.
478 * For depth clears, things are even more complicated, because here we
479 * resolve the other levels/layers if they have a different color than
480 * the current one. That resolve can be predicated, but we also set those
481 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
482 * Keeping track of the aux state when predication is involved is just
483 * even more complex, so the easiest thing to do when the fast clear
484 * depth is changing is to stall on the CPU and resolve the predication.
486 batch
->screen
->vtbl
.resolve_conditional_render(ice
);
487 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
490 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
491 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
494 const unsigned level_layers
=
495 iris_get_num_logical_layers(res
, res_level
);
496 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
497 if (res_level
== level
&&
499 layer
< box
->z
+ box
->depth
) {
500 /* We're going to clear this layer anyway. Leave it alone. */
504 enum isl_aux_state aux_state
=
505 iris_resource_get_aux_state(res
, res_level
, layer
);
507 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
508 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
509 /* This slice doesn't have any fast-cleared bits. */
513 /* If we got here, then the level may have fast-clear bits that
514 * use the old clear value. We need to do a depth resolve to get
515 * rid of their use of the clear value before we can change it.
516 * Fortunately, few applications ever change their depth clear
517 * value so this shouldn't happen often.
519 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
520 ISL_AUX_OP_FULL_RESOLVE
, false);
521 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
522 ISL_AUX_STATE_RESOLVED
);
525 const union isl_color_value clear_value
= { .f32
= {depth
, } };
526 iris_resource_set_clear_color(ice
, res
, clear_value
);
527 update_clear_depth
= true;
530 for (unsigned l
= 0; l
< box
->depth
; l
++) {
531 enum isl_aux_state aux_state
=
532 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
533 if (update_clear_depth
|| aux_state
!= ISL_AUX_STATE_CLEAR
) {
534 if (aux_state
== ISL_AUX_STATE_CLEAR
) {
535 perf_debug(&ice
->dbg
, "Performing HiZ clear just to update the "
536 "depth clear value\n");
538 iris_hiz_exec(ice
, batch
, res
, level
,
539 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
544 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
545 ISL_AUX_STATE_CLEAR
);
546 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
550 clear_depth_stencil(struct iris_context
*ice
,
551 struct pipe_resource
*p_res
,
553 const struct pipe_box
*box
,
554 bool render_condition_enabled
,
560 struct iris_resource
*res
= (void *) p_res
;
562 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
563 enum blorp_batch_flags blorp_flags
= 0;
565 if (render_condition_enabled
) {
566 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
569 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
570 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
573 iris_batch_maybe_flush(batch
, 1500);
575 struct iris_resource
*z_res
;
576 struct iris_resource
*stencil_res
;
577 struct blorp_surf z_surf
;
578 struct blorp_surf stencil_surf
;
580 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
581 if (z_res
&& clear_depth
&&
582 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
583 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
584 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
585 "cache history: post fast Z clear");
590 /* At this point, we might have fast cleared the depth buffer. So if there's
591 * no stencil clear pending, return early.
593 if (!(clear_depth
|| clear_stencil
)) {
597 if (clear_depth
&& z_res
) {
598 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
599 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
600 &z_surf
, &z_res
->base
, z_res
->aux
.usage
,
604 uint8_t stencil_mask
= clear_stencil
&& stencil_res
? 0xff : 0;
606 iris_resource_prepare_access(ice
, stencil_res
, level
, 1, box
->z
,
607 box
->depth
, stencil_res
->aux
.usage
, false);
608 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
,
609 &stencil_surf
, &stencil_res
->base
,
610 stencil_res
->aux
.usage
, level
, true);
613 iris_batch_sync_region_start(batch
);
615 struct blorp_batch blorp_batch
;
616 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
618 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
619 level
, box
->z
, box
->depth
,
622 box
->y
+ box
->height
,
623 clear_depth
&& z_res
, depth
,
624 stencil_mask
, stencil
);
626 blorp_batch_finish(&blorp_batch
);
627 iris_batch_sync_region_end(batch
);
629 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
630 "cache history: post slow ZS clear");
632 if (clear_depth
&& z_res
) {
633 iris_resource_finish_depth(ice
, z_res
, level
,
634 box
->z
, box
->depth
, true);
638 iris_resource_finish_write(ice
, stencil_res
, level
, box
->z
, box
->depth
,
639 stencil_res
->aux
.usage
);
644 * The pipe->clear() driver hook.
646 * This clears buffers attached to the current draw framebuffer.
649 iris_clear(struct pipe_context
*ctx
,
651 const struct pipe_scissor_state
*scissor_state
,
652 const union pipe_color_union
*p_color
,
656 struct iris_context
*ice
= (void *) ctx
;
657 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
659 assert(buffers
!= 0);
661 struct pipe_box box
= {
662 .width
= cso_fb
->width
,
663 .height
= cso_fb
->height
,
667 box
.x
= scissor_state
->minx
;
668 box
.y
= scissor_state
->miny
;
669 box
.width
= MIN2(box
.width
, scissor_state
->maxx
- scissor_state
->minx
);
670 box
.height
= MIN2(box
.height
, scissor_state
->maxy
- scissor_state
->miny
);
673 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
674 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
676 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1;
677 box
.z
= psurf
->u
.tex
.first_layer
,
678 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
679 buffers
& PIPE_CLEAR_DEPTH
,
680 buffers
& PIPE_CLEAR_STENCIL
,
684 if (buffers
& PIPE_CLEAR_COLOR
) {
685 /* pipe_color_union and isl_color_value are interchangeable */
686 union isl_color_value
*color
= (void *) p_color
;
688 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
689 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
690 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
691 struct iris_surface
*isurf
= (void *) psurf
;
692 box
.depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
693 box
.z
= psurf
->u
.tex
.first_layer
,
695 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
696 true, isurf
->view
.format
, isurf
->view
.swizzle
,
704 * The pipe->clear_texture() driver hook.
706 * This clears the given texture resource.
709 iris_clear_texture(struct pipe_context
*ctx
,
710 struct pipe_resource
*p_res
,
712 const struct pipe_box
*box
,
715 struct iris_context
*ice
= (void *) ctx
;
716 struct iris_screen
*screen
= (void *) ctx
->screen
;
717 struct iris_resource
*res
= (void *) p_res
;
718 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
720 if (iris_resource_unfinished_aux_import(res
))
721 iris_resource_finish_aux_import(ctx
->screen
, res
);
723 if (util_format_is_depth_or_stencil(p_res
->format
)) {
724 const struct util_format_description
*fmt_desc
=
725 util_format_description(p_res
->format
);
730 if (fmt_desc
->unpack_z_float
)
731 util_format_unpack_z_float(p_res
->format
, &depth
, data
, 1);
733 if (fmt_desc
->unpack_s_8uint
)
734 util_format_unpack_s_8uint(p_res
->format
, &stencil
, data
, 1);
736 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
739 union isl_color_value color
;
740 struct iris_resource
*res
= (void *) p_res
;
741 enum isl_format format
= res
->surf
.format
;
743 if (!isl_format_supports_rendering(devinfo
, format
)) {
744 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
745 // XXX: actually just get_copy_format_for_bpb from BLORP
746 // XXX: don't cut and paste this
748 case 8: format
= ISL_FORMAT_R8_UINT
; break;
749 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
750 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
751 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
752 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
753 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
754 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
755 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
757 unreachable("Unknown format bpb");
760 /* No aux surfaces for non-renderable surfaces */
761 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
764 isl_color_value_unpack(&color
, format
, data
);
766 clear_color(ice
, p_res
, level
, box
, true, format
,
767 ISL_SWIZZLE_IDENTITY
, color
);
772 * The pipe->clear_render_target() driver hook.
774 * This clears the given render target surface.
777 iris_clear_render_target(struct pipe_context
*ctx
,
778 struct pipe_surface
*psurf
,
779 const union pipe_color_union
*p_color
,
780 unsigned dst_x
, unsigned dst_y
,
781 unsigned width
, unsigned height
,
782 bool render_condition_enabled
)
784 struct iris_context
*ice
= (void *) ctx
;
785 struct iris_surface
*isurf
= (void *) psurf
;
786 struct pipe_box box
= {
789 .z
= psurf
->u
.tex
.first_layer
,
792 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
795 /* pipe_color_union and isl_color_value are interchangeable */
796 union isl_color_value
*color
= (void *) p_color
;
798 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
799 render_condition_enabled
,
800 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
804 * The pipe->clear_depth_stencil() driver hook.
806 * This clears the given depth/stencil surface.
809 iris_clear_depth_stencil(struct pipe_context
*ctx
,
810 struct pipe_surface
*psurf
,
814 unsigned dst_x
, unsigned dst_y
,
815 unsigned width
, unsigned height
,
816 bool render_condition_enabled
)
818 struct iris_context
*ice
= (void *) ctx
;
819 struct pipe_box box
= {
822 .z
= psurf
->u
.tex
.first_layer
,
825 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
828 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
830 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
831 render_condition_enabled
,
832 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
837 iris_init_clear_functions(struct pipe_context
*ctx
)
839 ctx
->clear
= iris_clear
;
840 ctx
->clear_texture
= iris_clear_texture
;
841 ctx
->clear_render_target
= iris_clear_render_target
;
842 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;