2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
81 /* Surface state can only record one fast clear color value. Therefore
82 * unless different levels/layers agree on the color it can be used to
83 * represent only single level/layer. Here it will be reserved for the
84 * first slice (level 0, layer 0).
86 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
89 /* Check for partial clear */
90 if (box
->x
> 0 || box
->y
> 0 ||
91 box
->width
< p_res
->width0
||
92 box
->height
< p_res
->height0
) {
96 /* We store clear colors as floats or uints as needed. If there are
97 * texture views in play, the formats will not properly be respected
98 * during resolves because the resolve operations only know about the
99 * resource and not the renderbuffer.
101 if (isl_format_srgb_to_linear(render_format
) !=
102 isl_format_srgb_to_linear(format
)) {
106 /* XXX: if (irb->mt->supports_fast_clear)
107 * see intel_miptree_create_for_dri_image()
110 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
116 static union isl_color_value
117 convert_fast_clear_color(struct iris_context
*ice
,
118 struct iris_resource
*res
,
119 enum isl_format render_format
,
120 const union isl_color_value color
)
122 union isl_color_value override_color
= color
;
123 struct pipe_resource
*p_res
= (void *) res
;
125 const enum pipe_format format
= p_res
->format
;
126 const struct util_format_description
*desc
=
127 util_format_description(format
);
128 unsigned colormask
= util_format_colormask(desc
);
130 if (util_format_is_intensity(format
) ||
131 util_format_is_luminance(format
) ||
132 util_format_is_luminance_alpha(format
)) {
133 override_color
.u32
[1] = override_color
.u32
[0];
134 override_color
.u32
[2] = override_color
.u32
[0];
135 if (util_format_is_intensity(format
))
136 override_color
.u32
[3] = override_color
.u32
[0];
138 for (int chan
= 0; chan
< 3; chan
++) {
139 if (!(colormask
& (1 << chan
)))
140 override_color
.u32
[chan
] = 0;
144 if (util_format_is_unorm(format
)) {
145 for (int i
= 0; i
< 4; i
++)
146 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
147 } else if (util_format_is_snorm(format
)) {
148 for (int i
= 0; i
< 4; i
++)
149 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
150 } else if (util_format_is_pure_uint(format
)) {
151 for (int i
= 0; i
< 4; i
++) {
152 unsigned bits
= util_format_get_component_bits(
153 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
155 uint32_t max
= (1u << bits
) - 1;
156 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
159 } else if (util_format_is_pure_sint(format
)) {
160 for (int i
= 0; i
< 4; i
++) {
161 unsigned bits
= util_format_get_component_bits(
162 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
164 int32_t max
= (1 << (bits
- 1)) - 1;
165 int32_t min
= -(1 << (bits
- 1));
166 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
169 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
170 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
171 /* these packed float formats only store unsigned values */
172 for (int i
= 0; i
< 4; i
++)
173 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
176 if (!(colormask
& 1 << 3)) {
177 if (util_format_is_pure_integer(format
))
178 override_color
.u32
[3] = 1;
180 override_color
.f32
[3] = 1.0f
;
183 /* Handle linear to SRGB conversion */
184 if (isl_format_is_srgb(render_format
)) {
185 for (int i
= 0; i
< 3; i
++) {
186 override_color
.f32
[i
] =
187 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
191 return override_color
;
195 fast_clear_color(struct iris_context
*ice
,
196 struct iris_resource
*res
,
198 const struct pipe_box
*box
,
199 enum isl_format format
,
200 union isl_color_value color
,
201 enum blorp_batch_flags blorp_flags
)
203 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
204 struct pipe_resource
*p_res
= (void *) res
;
205 const enum isl_aux_state aux_state
=
206 iris_resource_get_aux_state(res
, level
, box
->z
);
208 color
= convert_fast_clear_color(ice
, res
, format
, color
);
210 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
214 /* We decided that we are going to fast clear, and the color is
215 * changing. But if we have a predicate bit set, the predication
216 * affects whether we should clear or not, and if we shouldn't, we
217 * also shouldn't update the clear color.
219 * However, we can't simply predicate-update the clear color (the
220 * commands don't support that). And we would lose track of the
221 * color, preventing us from doing some optimizations later.
223 * Since changing the clear color when the predication bit is enabled
224 * is not something that should happen often, we stall on the CPU here
225 * to resolve the predication, and then proceed.
227 iris_resolve_conditional_render(ice
);
228 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
232 iris_resource_set_clear_color(ice
, res
, color
);
234 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
235 * changed, the clear is redundant and can be skipped.
237 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
240 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
242 * "Any transition from any value in {Clear, Render, Resolve} to a
243 * different value in {Clear, Render, Resolve} requires end of pipe
246 * In other words, fast clear ops are not properly synchronized with
247 * other drawing. We need to use a PIPE_CONTROL to ensure that the
248 * contents of the previous draw hit the render target before we resolve
249 * and again afterwards to ensure that the resolve is complete before we
250 * do any more regular drawing.
252 iris_emit_end_of_pipe_sync(batch
,
253 "fast clear: pre-flush",
254 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
256 /* If we reach this point, we need to fast clear to change the state to
257 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
259 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
261 struct blorp_batch blorp_batch
;
262 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
264 struct blorp_surf surf
;
265 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
268 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
269 * the clear color during the fast clear, if the surface format is of sRGB
270 * type. We use the linear version of the surface format here to prevent
271 * that from happening, since we already do our own linear -> sRGB
272 * conversion in convert_fast_clear_color().
274 blorp_fast_clear(&blorp_batch
, &surf
, isl_format_srgb_to_linear(format
),
275 level
, box
->z
, box
->depth
,
276 box
->x
, box
->y
, box
->x
+ box
->width
,
277 box
->y
+ box
->height
);
278 blorp_batch_finish(&blorp_batch
);
279 iris_emit_end_of_pipe_sync(batch
,
280 "fast clear: post flush",
281 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
283 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
284 box
->depth
, ISL_AUX_STATE_CLEAR
);
285 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
290 clear_color(struct iris_context
*ice
,
291 struct pipe_resource
*p_res
,
293 const struct pipe_box
*box
,
294 bool render_condition_enabled
,
295 enum isl_format format
,
296 struct isl_swizzle swizzle
,
297 union isl_color_value color
)
299 struct iris_resource
*res
= (void *) p_res
;
301 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
302 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
303 enum blorp_batch_flags blorp_flags
= 0;
305 if (render_condition_enabled
) {
306 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
309 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
310 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
313 if (p_res
->target
== PIPE_BUFFER
)
314 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
316 iris_batch_maybe_flush(batch
, 1500);
318 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
319 res
->surf
.format
, format
, color
);
320 if (can_fast_clear
) {
321 fast_clear_color(ice
, res
, level
, box
, format
, color
,
326 bool color_write_disable
[4] = { false, false, false, false };
327 enum isl_aux_usage aux_usage
=
328 iris_resource_render_aux_usage(ice
, res
, format
,
331 iris_resource_prepare_render(ice
, batch
, res
, level
,
332 box
->z
, box
->depth
, aux_usage
);
334 struct blorp_surf surf
;
335 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
338 struct blorp_batch blorp_batch
;
339 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
341 if (!isl_format_supports_rendering(devinfo
, format
) &&
342 isl_format_is_rgbx(format
))
343 format
= isl_format_rgbx_to_rgba(format
);
345 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
346 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
347 box
->x
+ box
->width
, box
->y
+ box
->height
,
348 color
, color_write_disable
);
350 blorp_batch_finish(&blorp_batch
);
351 iris_flush_and_dirty_for_history(ice
, batch
, res
,
352 PIPE_CONTROL_RENDER_TARGET_FLUSH
,
353 "cache history: post color clear");
355 iris_resource_finish_render(ice
, res
, level
,
356 box
->z
, box
->depth
, aux_usage
);
360 can_fast_clear_depth(struct iris_context
*ice
,
361 struct iris_resource
*res
,
363 const struct pipe_box
*box
,
366 struct pipe_resource
*p_res
= (void *) res
;
368 /* Check for partial clears */
369 if (box
->x
> 0 || box
->y
> 0 ||
370 box
->width
< u_minify(p_res
->width0
, level
) ||
371 box
->height
< u_minify(p_res
->height0
, level
)) {
375 if (!(res
->aux
.has_hiz
& (1 << level
)))
382 fast_clear_depth(struct iris_context
*ice
,
383 struct iris_resource
*res
,
385 const struct pipe_box
*box
,
388 struct pipe_resource
*p_res
= (void *) res
;
389 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
391 /* Quantize the clear value to what can be stored in the actual depth
392 * buffer. This makes the following check more accurate because it now
393 * checks if the actual depth bits will match. It also prevents us from
394 * getting a too-accurate depth value during depth testing or when sampling
397 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
398 const uint32_t depth_max
= (1 << nbits
) - 1;
399 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
400 (unsigned)(depth
* depth_max
) / (float)depth_max
;
402 bool update_clear_depth
= false;
404 /* If we're clearing to a new clear value, then we need to resolve any clear
405 * flags out of the HiZ buffer into the real depth buffer.
407 if (res
->aux
.clear_color
.f32
[0] != depth
) {
408 /* We decided that we are going to fast clear, and the color is
409 * changing. But if we have a predicate bit set, the predication
410 * affects whether we should clear or not, and if we shouldn't, we
411 * also shouldn't update the clear color.
413 * However, we can't simply predicate-update the clear color (the
414 * commands don't support that). And we would lose track of the
415 * color, preventing us from doing some optimizations later.
417 * For depth clears, things are even more complicated, because here we
418 * resolve the other levels/layers if they have a different color than
419 * the current one. That resolve can be predicated, but we also set those
420 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
421 * Keeping track of the aux state when predication is involved is just
422 * even more complex, so the easiest thing to do when the fast clear
423 * depth is changing is to stall on the CPU and resolve the predication.
425 iris_resolve_conditional_render(ice
);
426 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
429 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
430 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
433 const unsigned level_layers
=
434 iris_get_num_logical_layers(res
, res_level
);
435 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
436 if (res_level
== level
&&
438 layer
< box
->z
+ box
->depth
) {
439 /* We're going to clear this layer anyway. Leave it alone. */
443 enum isl_aux_state aux_state
=
444 iris_resource_get_aux_state(res
, res_level
, layer
);
446 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
447 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
448 /* This slice doesn't have any fast-cleared bits. */
452 /* If we got here, then the level may have fast-clear bits that
453 * use the old clear value. We need to do a depth resolve to get
454 * rid of their use of the clear value before we can change it.
455 * Fortunately, few applications ever change their depth clear
456 * value so this shouldn't happen often.
458 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
459 ISL_AUX_OP_FULL_RESOLVE
, false);
460 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
461 ISL_AUX_STATE_RESOLVED
);
464 const union isl_color_value clear_value
= { .f32
= {depth
, } };
465 iris_resource_set_clear_color(ice
, res
, clear_value
);
466 update_clear_depth
= true;
469 for (unsigned l
= 0; l
< box
->depth
; l
++) {
470 enum isl_aux_state aux_state
=
471 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
472 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
473 iris_hiz_exec(ice
, batch
, res
, level
,
474 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
479 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
480 ISL_AUX_STATE_CLEAR
);
481 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
485 clear_depth_stencil(struct iris_context
*ice
,
486 struct pipe_resource
*p_res
,
488 const struct pipe_box
*box
,
489 bool render_condition_enabled
,
495 struct iris_resource
*res
= (void *) p_res
;
497 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
498 enum blorp_batch_flags blorp_flags
= 0;
500 if (render_condition_enabled
) {
501 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
504 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
505 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
508 iris_batch_maybe_flush(batch
, 1500);
510 struct iris_resource
*z_res
;
511 struct iris_resource
*stencil_res
;
512 struct blorp_surf z_surf
;
513 struct blorp_surf stencil_surf
;
515 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
516 if (z_res
&& clear_depth
&&
517 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
518 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
519 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
520 "cache history: post fast Z clear");
525 /* At this point, we might have fast cleared the depth buffer. So if there's
526 * no stencil clear pending, return early.
528 if (!(clear_depth
|| clear_stencil
)) {
533 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
534 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
535 z_res
->aux
.usage
, level
, true);
538 struct blorp_batch blorp_batch
;
539 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
542 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
543 &stencil_res
->base
, stencil_res
->aux
.usage
,
547 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
548 level
, box
->z
, box
->depth
,
551 box
->y
+ box
->height
,
552 clear_depth
&& z_res
, depth
,
553 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
555 blorp_batch_finish(&blorp_batch
);
556 iris_flush_and_dirty_for_history(ice
, batch
, res
, 0,
557 "cache history: post slow ZS clear");
560 iris_resource_finish_depth(ice
, z_res
, level
,
561 box
->z
, box
->depth
, true);
566 * The pipe->clear() driver hook.
568 * This clears buffers attached to the current draw framebuffer.
571 iris_clear(struct pipe_context
*ctx
,
573 const union pipe_color_union
*p_color
,
577 struct iris_context
*ice
= (void *) ctx
;
578 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
580 assert(buffers
!= 0);
582 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
583 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
584 struct pipe_box box
= {
585 .width
= cso_fb
->width
,
586 .height
= cso_fb
->height
,
587 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
588 .z
= psurf
->u
.tex
.first_layer
,
591 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
592 buffers
& PIPE_CLEAR_DEPTH
,
593 buffers
& PIPE_CLEAR_STENCIL
,
597 if (buffers
& PIPE_CLEAR_COLOR
) {
598 /* pipe_color_union and isl_color_value are interchangeable */
599 union isl_color_value
*color
= (void *) p_color
;
601 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
602 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
603 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
604 struct iris_surface
*isurf
= (void *) psurf
;
605 struct pipe_box box
= {
606 .width
= cso_fb
->width
,
607 .height
= cso_fb
->height
,
608 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
609 .z
= psurf
->u
.tex
.first_layer
,
612 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
613 true, isurf
->view
.format
, isurf
->view
.swizzle
,
621 * The pipe->clear_texture() driver hook.
623 * This clears the given texture resource.
626 iris_clear_texture(struct pipe_context
*ctx
,
627 struct pipe_resource
*p_res
,
629 const struct pipe_box
*box
,
632 struct iris_context
*ice
= (void *) ctx
;
633 struct iris_screen
*screen
= (void *) ctx
->screen
;
634 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
636 if (util_format_is_depth_or_stencil(p_res
->format
)) {
637 const struct util_format_description
*fmt_desc
=
638 util_format_description(p_res
->format
);
643 if (fmt_desc
->unpack_z_float
)
644 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
646 if (fmt_desc
->unpack_s_8uint
)
647 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
649 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
652 union isl_color_value color
;
653 struct iris_resource
*res
= (void *) p_res
;
654 enum isl_format format
= res
->surf
.format
;
656 if (!isl_format_supports_rendering(devinfo
, format
)) {
657 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
658 // XXX: actually just get_copy_format_for_bpb from BLORP
659 // XXX: don't cut and paste this
661 case 8: format
= ISL_FORMAT_R8_UINT
; break;
662 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
663 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
664 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
665 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
666 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
667 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
668 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
670 unreachable("Unknown format bpb");
673 /* No aux surfaces for non-renderable surfaces */
674 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
677 isl_color_value_unpack(&color
, format
, data
);
679 clear_color(ice
, p_res
, level
, box
, true, format
,
680 ISL_SWIZZLE_IDENTITY
, color
);
685 * The pipe->clear_render_target() driver hook.
687 * This clears the given render target surface.
690 iris_clear_render_target(struct pipe_context
*ctx
,
691 struct pipe_surface
*psurf
,
692 const union pipe_color_union
*p_color
,
693 unsigned dst_x
, unsigned dst_y
,
694 unsigned width
, unsigned height
,
695 bool render_condition_enabled
)
697 struct iris_context
*ice
= (void *) ctx
;
698 struct iris_surface
*isurf
= (void *) psurf
;
699 struct pipe_box box
= {
702 .z
= psurf
->u
.tex
.first_layer
,
705 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
708 /* pipe_color_union and isl_color_value are interchangeable */
709 union isl_color_value
*color
= (void *) p_color
;
711 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
712 render_condition_enabled
,
713 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
717 * The pipe->clear_depth_stencil() driver hook.
719 * This clears the given depth/stencil surface.
722 iris_clear_depth_stencil(struct pipe_context
*ctx
,
723 struct pipe_surface
*psurf
,
727 unsigned dst_x
, unsigned dst_y
,
728 unsigned width
, unsigned height
,
729 bool render_condition_enabled
)
731 struct iris_context
*ice
= (void *) ctx
;
732 struct pipe_box box
= {
735 .z
= psurf
->u
.tex
.first_layer
,
738 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
741 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
743 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
744 render_condition_enabled
,
745 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
750 iris_init_clear_functions(struct pipe_context
*ctx
)
752 ctx
->clear
= iris_clear
;
753 ctx
->clear_texture
= iris_clear_texture
;
754 ctx
->clear_render_target
= iris_clear_render_target
;
755 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;