src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/slab.h"
  29 #include "util/u_debug.h"
  30 #include "intel/blorp/blorp.h"
  31 #include "intel/dev/gen_debug.h"
  32 #include "intel/common/gen_l3_config.h"
  33 #include "intel/compiler/brw_compiler.h"
  34 #include "iris_batch.h"
  35 #include "iris_binder.h"
  36 #include "iris_fence.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39
  40 struct iris_bo;
  41 struct iris_context;
  42 struct blorp_batch;
  43 struct blorp_params;
  44
  45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  48 #define IRIS_MAX_ABOS 16
  49 #define IRIS_MAX_SSBOS 16
  50 #define IRIS_MAX_VIEWPORTS 16
  51 #define IRIS_MAX_CLIP_PLANES 8
  52 #define IRIS_MAX_GLOBAL_BINDINGS 32
  53
  54 enum iris_param_domain {
  55    BRW_PARAM_DOMAIN_BUILTIN = 0,
  56    BRW_PARAM_DOMAIN_IMAGE,
  57 };
  58
  59 enum {
  60    DRI_CONF_BO_REUSE_DISABLED,
  61    DRI_CONF_BO_REUSE_ALL
  62 };
  63
  64 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  65 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  66 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  67 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  68 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  69 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  70
  71 /**
  72  * Dirty flags.  When state changes, we flag some combination of these
  73  * to indicate that particular GPU commands need to be re-emitted.
  74  *
  75  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  76  * in rare cases they map to a group of related packets that need to be
  77  * emitted together.
  78  *
  79  * See iris_upload_render_state().
  80  */
  81 #define IRIS_DIRTY_COLOR_CALC_STATE               (1ull <<  0)
  82 #define IRIS_DIRTY_POLYGON_STIPPLE                (1ull <<  1)
  83 #define IRIS_DIRTY_SCISSOR_RECT                   (1ull <<  2)
  84 #define IRIS_DIRTY_WM_DEPTH_STENCIL               (1ull <<  3)
  85 #define IRIS_DIRTY_CC_VIEWPORT                    (1ull <<  4)
  86 #define IRIS_DIRTY_SF_CL_VIEWPORT                 (1ull <<  5)
  87 #define IRIS_DIRTY_PS_BLEND                       (1ull <<  6)
  88 #define IRIS_DIRTY_BLEND_STATE                    (1ull <<  7)
  89 #define IRIS_DIRTY_RASTER                         (1ull <<  8)
  90 #define IRIS_DIRTY_CLIP                           (1ull <<  9)
  91 #define IRIS_DIRTY_SBE                            (1ull << 10)
  92 #define IRIS_DIRTY_LINE_STIPPLE                   (1ull << 11)
  93 #define IRIS_DIRTY_VERTEX_ELEMENTS                (1ull << 12)
  94 #define IRIS_DIRTY_MULTISAMPLE                    (1ull << 13)
  95 #define IRIS_DIRTY_VERTEX_BUFFERS                 (1ull << 14)
  96 #define IRIS_DIRTY_SAMPLE_MASK                    (1ull << 15)
  97 #define IRIS_DIRTY_URB                            (1ull << 16)
  98 #define IRIS_DIRTY_DEPTH_BUFFER                   (1ull << 17)
  99 #define IRIS_DIRTY_WM                             (1ull << 18)
 100 #define IRIS_DIRTY_SO_BUFFERS                     (1ull << 19)
 101 #define IRIS_DIRTY_SO_DECL_LIST                   (1ull << 20)
 102 #define IRIS_DIRTY_STREAMOUT                      (1ull << 21)
 103 #define IRIS_DIRTY_VF_SGVS                        (1ull << 22)
 104 #define IRIS_DIRTY_VF                             (1ull << 23)
 105 #define IRIS_DIRTY_VF_TOPOLOGY                    (1ull << 24)
 106 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES    (1ull << 25)
 107 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES   (1ull << 26)
 108 #define IRIS_DIRTY_VF_STATISTICS                  (1ull << 27)
 109 #define IRIS_DIRTY_PMA_FIX                        (1ull << 28)
 110 #define IRIS_DIRTY_DEPTH_BOUNDS                   (1ull << 29)
 111 #define IRIS_DIRTY_RENDER_BUFFER                  (1ull << 30)
 112 #define IRIS_DIRTY_STENCIL_REF                    (1ull << 31)
 113
 114 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 115
 116 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
 117
 118 /**
 119  * Per-stage dirty flags.  When state changes, we flag some combination of
 120  * these to indicate that particular GPU commands need to be re-emitted.
 121  * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
 122  * indexed by shifting the mask by the shader stage index.
 123  *
 124  * See iris_upload_render_state().
 125  */
 126 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS        (1ull << 0)
 127 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS       (1ull << 1)
 128 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES       (1ull << 2)
 129 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS        (1ull << 3)
 130 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS        (1ull << 4)
 131 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS        (1ull << 5)
 132 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS            (1ull << 6)
 133 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS           (1ull << 7)
 134 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES           (1ull << 8)
 135 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS            (1ull << 9)
 136 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS            (1ull << 10)
 137 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS            (1ull << 11)
 138 #define IRIS_STAGE_DIRTY_VS                       (1ull << 12)
 139 #define IRIS_STAGE_DIRTY_TCS                      (1ull << 13)
 140 #define IRIS_STAGE_DIRTY_TES                      (1ull << 14)
 141 #define IRIS_STAGE_DIRTY_GS                       (1ull << 15)
 142 #define IRIS_STAGE_DIRTY_FS                       (1ull << 16)
 143 #define IRIS_STAGE_DIRTY_CS                       (1ull << 17)
 144 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS      18
 145 #define IRIS_STAGE_DIRTY_CONSTANTS_VS             (1ull << 18)
 146 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS            (1ull << 19)
 147 #define IRIS_STAGE_DIRTY_CONSTANTS_TES            (1ull << 20)
 148 #define IRIS_STAGE_DIRTY_CONSTANTS_GS             (1ull << 21)
 149 #define IRIS_STAGE_DIRTY_CONSTANTS_FS             (1ull << 22)
 150 #define IRIS_STAGE_DIRTY_CONSTANTS_CS             (1ull << 23)
 151 #define IRIS_STAGE_DIRTY_BINDINGS_VS              (1ull << 24)
 152 #define IRIS_STAGE_DIRTY_BINDINGS_TCS             (1ull << 25)
 153 #define IRIS_STAGE_DIRTY_BINDINGS_TES             (1ull << 26)
 154 #define IRIS_STAGE_DIRTY_BINDINGS_GS              (1ull << 27)
 155 #define IRIS_STAGE_DIRTY_BINDINGS_FS              (1ull << 28)
 156 #define IRIS_STAGE_DIRTY_BINDINGS_CS              (1ull << 29)
 157
 158 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
 159                                           IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
 160                                           IRIS_STAGE_DIRTY_UNCOMPILED_CS |    \
 161                                           IRIS_STAGE_DIRTY_CONSTANTS_CS |     \
 162                                           IRIS_STAGE_DIRTY_BINDINGS_CS)
 163
 164 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
 165
 166 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_STAGE_DIRTY_BINDINGS_VS  | \
 167                                        IRIS_STAGE_DIRTY_BINDINGS_TCS | \
 168                                        IRIS_STAGE_DIRTY_BINDINGS_TES | \
 169                                        IRIS_STAGE_DIRTY_BINDINGS_GS  | \
 170                                        IRIS_STAGE_DIRTY_BINDINGS_FS  | \
 171                                        IRIS_STAGE_DIRTY_BINDINGS_CS)
 172
 173 /**
 174  * Non-orthogonal state (NOS) dependency flags.
 175  *
 176  * Shader programs may depend on non-orthogonal state.  These flags are
 177  * used to indicate that a shader's key depends on the state provided by
 178  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 179  * cause the driver to re-compute the shader key, possibly triggering a
 180  * shader recompile.
 181  */
 182 enum iris_nos_dep {
 183    IRIS_NOS_FRAMEBUFFER,
 184    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 185    IRIS_NOS_RASTERIZER,
 186    IRIS_NOS_BLEND,
 187    IRIS_NOS_LAST_VUE_MAP,
 188
 189    IRIS_NOS_COUNT,
 190 };
 191
 192 /** @{
 193  *
 194  * Program cache keys for state based recompiles.
 195  */
 196
 197 struct iris_base_prog_key {
 198    unsigned program_string_id;
 199 };
 200
 201 struct iris_vue_prog_key {
 202    struct iris_base_prog_key base;
 203
 204    unsigned nr_userclip_plane_consts:4;
 205 };
 206
 207 struct iris_vs_prog_key {
 208    struct iris_vue_prog_key vue;
 209 };
 210
 211 struct iris_tcs_prog_key {
 212    struct iris_vue_prog_key vue;
 213
 214    uint16_t tes_primitive_mode;
 215
 216    uint8_t input_vertices;
 217
 218    bool quads_workaround;
 219
 220    /** A bitfield of per-patch outputs written. */
 221    uint32_t patch_outputs_written;
 222
 223    /** A bitfield of per-vertex outputs written. */
 224    uint64_t outputs_written;
 225 };
 226
 227 struct iris_tes_prog_key {
 228    struct iris_vue_prog_key vue;
 229
 230    /** A bitfield of per-patch inputs read. */
 231    uint32_t patch_inputs_read;
 232
 233    /** A bitfield of per-vertex inputs read. */
 234    uint64_t inputs_read;
 235 };
 236
 237 struct iris_gs_prog_key {
 238    struct iris_vue_prog_key vue;
 239 };
 240
 241 struct iris_fs_prog_key {
 242    struct iris_base_prog_key base;
 243
 244    unsigned nr_color_regions:5;
 245    bool flat_shade:1;
 246    bool alpha_test_replicate_alpha:1;
 247    bool alpha_to_coverage:1;
 248    bool clamp_fragment_color:1;
 249    bool persample_interp:1;
 250    bool multisample_fbo:1;
 251    bool force_dual_color_blend:1;
 252    bool coherent_fb_fetch:1;
 253
 254    uint8_t color_outputs_valid;
 255    uint64_t input_slots_valid;
 256 };
 257
 258 struct iris_cs_prog_key {
 259    struct iris_base_prog_key base;
 260 };
 261
 262 /** @} */
 263
 264 struct iris_depth_stencil_alpha_state;
 265
 266 /**
 267  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 268  */
 269 enum iris_program_cache_id {
 270    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 271    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 272    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 273    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 274    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 275    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 276    IRIS_CACHE_BLORP,
 277 };
 278
 279 /** @{
 280  *
 281  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 282  * synchronization, pipelined memory writes, and so on.
 283  *
 284  * The bits here are not the actual hardware values.  The actual fields
 285  * move between various generations, so we just have flags for each
 286  * potential operation, and use genxml to encode the actual packet.
 287  */
 288 enum pipe_control_flags
 289 {
 290    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 291    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 292    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 293    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 294    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 295    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 296    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 297    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 298    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 299    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 300    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 301    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 302    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 303    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 304    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 305    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 306    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 307    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 308    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 309    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 310    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 311    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 312    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 313    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 314    PIPE_CONTROL_TILE_CACHE_FLUSH                = (1 << 25),
 315    PIPE_CONTROL_FLUSH_HDC                       = (1 << 26),
 316 };
 317
 318 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 319    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 320     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 321     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 322
 323 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 324    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 325     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 326     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 327     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 328     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 329
 330 enum iris_predicate_state {
 331    /* The first two states are used if we can determine whether to draw
 332     * without having to look at the values in the query object buffer. This
 333     * will happen if there is no conditional render in progress, if the query
 334     * object is already completed or if something else has already added
 335     * samples to the preliminary result.
 336     */
 337    IRIS_PREDICATE_STATE_RENDER,
 338    IRIS_PREDICATE_STATE_DONT_RENDER,
 339
 340    /* In this case whether to draw or not depends on the result of an
 341     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 342     */
 343    IRIS_PREDICATE_STATE_USE_BIT,
 344 };
 345
 346 /** @} */
 347
 348 /**
 349  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 350  * It primarily contains the NIR for the shader.
 351  *
 352  * Each API-facing shader can be compiled into multiple shader variants,
 353  * based on non-orthogonal state dependencies, recorded in the shader key.
 354  *
 355  * See iris_compiled_shader, which represents a compiled shader variant.
 356  */
 357 struct iris_uncompiled_shader {
 358    struct nir_shader *nir;
 359
 360    struct pipe_stream_output_info stream_output;
 361
 362    /* A SHA1 of the serialized NIR for the disk cache. */
 363    unsigned char nir_sha1[20];
 364
 365    unsigned program_id;
 366
 367    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 368    unsigned nos;
 369
 370    /** Have any shader variants been compiled yet? */
 371    bool compiled_once;
 372
 373    /** Should we use ALT mode for math?  Useful for ARB programs. */
 374    bool use_alt_mode;
 375
 376    bool needs_edge_flag;
 377
 378    /* Whether shader uses atomic operations. */
 379    bool uses_atomic_load_store;
 380
 381    /** Size (in bytes) of the kernel input data */
 382    unsigned kernel_input_size;
 383
 384    /** Constant data scraped from the shader by nir_opt_large_constants */
 385    struct pipe_resource *const_data;
 386
 387    /** Surface state for const_data */
 388    struct iris_state_ref const_data_state;
 389 };
 390
 391 enum iris_surface_group {
 392    IRIS_SURFACE_GROUP_RENDER_TARGET,
 393    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 394    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 395    IRIS_SURFACE_GROUP_TEXTURE,
 396    IRIS_SURFACE_GROUP_IMAGE,
 397    IRIS_SURFACE_GROUP_UBO,
 398    IRIS_SURFACE_GROUP_SSBO,
 399
 400    IRIS_SURFACE_GROUP_COUNT,
 401 };
 402
 403 enum {
 404    /* Invalid value for a binding table index. */
 405    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 406 };
 407
 408 struct iris_binding_table {
 409    uint32_t size_bytes;
 410
 411    /** Number of surfaces in each group, before compacting. */
 412    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 413
 414    /** Initial offset of each group. */
 415    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 416
 417    /** Mask of surfaces used in each group. */
 418    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 419 };
 420
 421 /**
 422  * A compiled shader variant, containing a pointer to the GPU assembly,
 423  * as well as program data and other packets needed by state upload.
 424  *
 425  * There can be several iris_compiled_shader variants per API-level shader
 426  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 427  */
 428 struct iris_compiled_shader {
 429    struct list_head link;
 430
 431    /** Reference to the uploaded assembly. */
 432    struct iris_state_ref assembly;
 433
 434    /** Pointer to the assembly in the BO's map. */
 435    void *map;
 436
 437    /** The program data (owned by the program cache hash table) */
 438    struct brw_stage_prog_data *prog_data;
 439
 440    /** A list of system values to be uploaded as uniforms. */
 441    enum brw_param_builtin *system_values;
 442    unsigned num_system_values;
 443
 444    /** Size (in bytes) of the kernel input data */
 445    unsigned kernel_input_size;
 446
 447    /** Number of constbufs expected by the shader. */
 448    unsigned num_cbufs;
 449
 450    /**
 451     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 452     * (the VUE-based information for transform feedback outputs).
 453     */
 454    uint32_t *streamout;
 455
 456    struct iris_binding_table bt;
 457
 458    /**
 459     * Shader packets and other data derived from prog_data.  These must be
 460     * completely determined from prog_data.
 461     */
 462    uint8_t derived_data[0];
 463 };
 464
 465 /**
 466  * API context state that is replicated per shader stage.
 467  */
 468 struct iris_shader_state {
 469    /** Uniform Buffers */
 470    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 471    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 472
 473    bool sysvals_need_upload;
 474
 475    /** Shader Storage Buffers */
 476    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 477    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 478
 479    /** Shader Storage Images (image load store) */
 480    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 481
 482    struct iris_state_ref sampler_table;
 483    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 484    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 485
 486    /** Bitfield of which constant buffers are bound (non-null). */
 487    uint32_t bound_cbufs;
 488
 489    /** Bitfield of which image views are bound (non-null). */
 490    uint32_t bound_image_views;
 491
 492    /** Bitfield of which sampler views are bound (non-null). */
 493    uint32_t bound_sampler_views;
 494
 495    /** Bitfield of which shader storage buffers are bound (non-null). */
 496    uint32_t bound_ssbos;
 497
 498    /** Bitfield of which shader storage buffers are writable. */
 499    uint32_t writable_ssbos;
 500 };
 501
 502 /**
 503  * Gallium CSO for stream output (transform feedback) targets.
 504  */
 505 struct iris_stream_output_target {
 506    struct pipe_stream_output_target base;
 507
 508    /** Storage holding the offset where we're writing in the buffer */
 509    struct iris_state_ref offset;
 510
 511    /** Stride (bytes-per-vertex) during this transform feedback operation */
 512    uint16_t stride;
 513
 514    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 515    bool zeroed;
 516 };
 517
 518 /**
 519  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 520  *
 521  * See iris_border_color.c for more information.
 522  */
 523 struct iris_border_color_pool {
 524    struct iris_bo *bo;
 525    void *map;
 526    unsigned insert_point;
 527
 528    /** Map from border colors to offsets in the buffer. */
 529    struct hash_table *ht;
 530 };
 531
 532 /**
 533  * The API context (derived from pipe_context).
 534  *
 535  * Most driver state is tracked here.
 536  */
 537 struct iris_context {
 538    struct pipe_context ctx;
 539
 540    /** A debug callback for KHR_debug output. */
 541    struct pipe_debug_callback dbg;
 542
 543    /** A device reset status callback for notifying that the GPU is hosed. */
 544    struct pipe_device_reset_callback reset;
 545
 546    /** Slab allocator for iris_transfer_map objects. */
 547    struct slab_child_pool transfer_pool;
 548
 549    struct blorp_context blorp;
 550
 551    struct iris_batch batches[IRIS_BATCH_COUNT];
 552
 553    struct u_upload_mgr *query_buffer_uploader;
 554
 555    struct {
 556       struct {
 557          /**
 558           * Either the value of BaseVertex for indexed draw calls or the value
 559           * of the argument <first> for non-indexed draw calls.
 560           */
 561          int firstvertex;
 562          int baseinstance;
 563       } params;
 564
 565       /**
 566        * Are the above values the ones stored in the draw_params buffer?
 567        * If so, we can compare them against new values to see if anything
 568        * changed.  If not, we need to assume they changed.
 569        */
 570       bool params_valid;
 571
 572       /**
 573        * Resource and offset that stores draw_parameters from the indirect
 574        * buffer or to the buffer that stures the previous values for non
 575        * indirect draws.
 576        */
 577       struct iris_state_ref draw_params;
 578
 579       struct {
 580          /**
 581           * The value of DrawID. This always comes in from it's own vertex
 582           * buffer since it's not part of the indirect draw parameters.
 583           */
 584          int drawid;
 585
 586          /**
 587           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 588           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 589           */
 590          int is_indexed_draw;
 591       } derived_params;
 592
 593       /**
 594        * Resource and offset used for GL_ARB_shader_draw_parameters which
 595        * contains parameters that are not present in the indirect buffer as
 596        * drawid and is_indexed_draw. They will go in their own vertex element.
 597        */
 598       struct iris_state_ref derived_draw_params;
 599    } draw;
 600
 601    struct {
 602       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 603       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 604       struct brw_vue_map *last_vue_map;
 605
 606       /** List of shader variants whose deletion has been deferred for now */
 607       struct list_head deleted_variants[MESA_SHADER_STAGES];
 608
 609       struct u_upload_mgr *uploader;
 610       struct hash_table *cache;
 611
 612       /** Is a GS or TES outputting points or lines? */
 613       bool output_topology_is_points_or_lines;
 614
 615       /**
 616        * Scratch buffers for various sizes and stages.
 617        *
 618        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 619        * and shader stage.
 620        */
 621       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 622    } shaders;
 623
 624    struct {
 625       struct iris_query *query;
 626       bool condition;
 627    } condition;
 628
 629    struct gen_perf_context *perf_ctx;
 630
 631    /** Frame number for debug prints */
 632    uint32_t frame;
 633
 634    struct {
 635       uint64_t dirty;
 636       uint64_t stage_dirty;
 637       uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT];
 638
 639       unsigned num_viewports;
 640       unsigned sample_mask;
 641       struct iris_blend_state *cso_blend;
 642       struct iris_rasterizer_state *cso_rast;
 643       struct iris_depth_stencil_alpha_state *cso_zsa;
 644       struct iris_vertex_element_state *cso_vertex_elements;
 645       struct pipe_blend_color blend_color;
 646       struct pipe_poly_stipple poly_stipple;
 647       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 648       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 649       struct pipe_stencil_ref stencil_ref;
 650       struct pipe_framebuffer_state framebuffer;
 651       struct pipe_clip_state clip_planes;
 652
 653       float default_outer_level[4];
 654       float default_inner_level[2];
 655
 656       /** Bitfield of which vertex buffers are bound (non-null). */
 657       uint64_t bound_vertex_buffers;
 658
 659       bool primitive_restart;
 660       unsigned cut_index;
 661       enum pipe_prim_type prim_mode:8;
 662       bool prim_is_points_or_lines;
 663       uint8_t vertices_per_patch;
 664
 665       bool window_space_position;
 666
 667       /** The last compute group size */
 668       uint32_t last_block[3];
 669
 670       /** The last compute grid size */
 671       uint32_t last_grid[3];
 672       /** Reference to the BO containing the compute grid size */
 673       struct iris_state_ref grid_size;
 674       /** Reference to the SURFACE_STATE for the compute grid resource */
 675       struct iris_state_ref grid_surf_state;
 676
 677       /**
 678        * Array of aux usages for drawing, altered to account for any
 679        * self-dependencies from resources bound for sampling and rendering.
 680        */
 681       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 682
 683       enum gen_urb_deref_block_size urb_deref_block_size;
 684
 685       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 686       bool depth_writes_enabled;
 687
 688       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 689       bool stencil_writes_enabled;
 690
 691       /** GenX-specific current state */
 692       struct iris_genx_state *genx;
 693
 694       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 695
 696       /** Do vertex shader uses shader draw parameters ? */
 697       bool vs_uses_draw_params;
 698       bool vs_uses_derived_draw_params;
 699       bool vs_needs_sgvs_element;
 700
 701       /** Do vertex shader uses edge flag ? */
 702       bool vs_needs_edge_flag;
 703
 704       /** Do any samplers need border color?  One bit per shader stage. */
 705       uint8_t need_border_colors;
 706
 707       /** Global resource bindings */
 708       struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS];
 709
 710       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 711       bool streamout_active;
 712
 713       bool statistics_counters_enabled;
 714
 715       /** Current conditional rendering mode */
 716       enum iris_predicate_state predicate;
 717
 718       /**
 719        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 720        * render context that needs to be uploaded to the compute context.
 721        */
 722       struct iris_bo *compute_predicate;
 723
 724       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 725       bool prims_generated_query_active;
 726
 727       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 728       uint32_t *streamout;
 729
 730       /** The SURFACE_STATE for a 1x1x1 null surface. */
 731       struct iris_state_ref unbound_tex;
 732
 733       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 734       struct iris_state_ref null_fb;
 735
 736       struct u_upload_mgr *surface_uploader;
 737       struct u_upload_mgr *dynamic_uploader;
 738
 739       struct iris_binder binder;
 740
 741       struct iris_border_color_pool border_color_pool;
 742
 743       /** The high 16-bits of the last VBO/index buffer addresses */
 744       uint16_t last_vbo_high_bits[33];
 745       uint16_t last_index_bo_high_bits;
 746
 747       /**
 748        * Resources containing streamed state which our render context
 749        * currently points to.  Used to re-add these to the validation
 750        * list when we start a new batch and haven't resubmitted commands.
 751        */
 752       struct {
 753          struct pipe_resource *cc_vp;
 754          struct pipe_resource *sf_cl_vp;
 755          struct pipe_resource *color_calc;
 756          struct pipe_resource *scissor;
 757          struct pipe_resource *blend;
 758          struct pipe_resource *index_buffer;
 759          struct pipe_resource *cs_thread_ids;
 760          struct pipe_resource *cs_desc;
 761       } last_res;
 762
 763       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 764       struct hash_table_u64 *sizes;
 765
 766       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 767       unsigned current_hash_scale;
 768    } state;
 769 };
 770
 771 #define perf_debug(dbg, ...) do {                      \
 772    if (INTEL_DEBUG & DEBUG_PERF)                       \
 773       dbg_printf(__VA_ARGS__);                         \
 774    if (unlikely(dbg))                                  \
 775       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 776 } while(0)
 777
 778 double get_time(void);
 779
 780 struct pipe_context *
 781 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 782
 783 void iris_lost_context_state(struct iris_batch *batch);
 784
 785 void iris_init_blit_functions(struct pipe_context *ctx);
 786 void iris_init_clear_functions(struct pipe_context *ctx);
 787 void iris_init_program_functions(struct pipe_context *ctx);
 788 void iris_init_resource_functions(struct pipe_context *ctx);
 789 void iris_init_perfquery_functions(struct pipe_context *ctx);
 790 void iris_update_compiled_shaders(struct iris_context *ice);
 791 void iris_update_compiled_compute_shader(struct iris_context *ice);
 792 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 793                                     unsigned threads,
 794                                     uint32_t *dst);
 795
 796
 797 /* iris_blit.c */
 798 void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
 799                                   struct blorp_surf *surf,
 800                                   struct pipe_resource *p_res,
 801                                   enum isl_aux_usage aux_usage,
 802                                   unsigned level,
 803                                   bool is_render_target);
 804 void iris_copy_region(struct blorp_context *blorp,
 805                       struct iris_batch *batch,
 806                       struct pipe_resource *dst,
 807                       unsigned dst_level,
 808                       unsigned dstx, unsigned dsty, unsigned dstz,
 809                       struct pipe_resource *src,
 810                       unsigned src_level,
 811                       const struct pipe_box *src_box);
 812
 813 /* iris_draw.c */
 814
 815 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 816 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 817
 818 /* iris_pipe_control.c */
 819
 820 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 821                                   const char *reason, uint32_t flags);
 822 void iris_emit_pipe_control_write(struct iris_batch *batch,
 823                                   const char *reason, uint32_t flags,
 824                                   struct iris_bo *bo, uint32_t offset,
 825                                   uint64_t imm);
 826 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 827                                 const char *reason, uint32_t flags);
 828 void iris_emit_buffer_barrier_for(struct iris_batch *batch,
 829                                   struct iris_bo *bo,
 830                                   enum iris_domain access);
 831 void iris_flush_all_caches(struct iris_batch *batch);
 832
 833 #define iris_handle_always_flush_cache(batch) \
 834    if (unlikely(batch->screen->driconf.always_flush_cache)) \
 835       iris_flush_all_caches(batch);
 836
 837 void iris_init_flush_functions(struct pipe_context *ctx);
 838
 839 /* iris_border_color.c */
 840
 841 void iris_init_border_color_pool(struct iris_context *ice);
 842 void iris_destroy_border_color_pool(struct iris_context *ice);
 843 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 844 uint32_t iris_upload_border_color(struct iris_context *ice,
 845                                   union pipe_color_union *color);
 846
 847 /* iris_program.c */
 848 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 849                                      struct pipe_shader_buffer *buf,
 850                                      struct iris_state_ref *surf_state,
 851                                      bool ssbo);
 852 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 853                                                gl_shader_stage stage);
 854 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 855                                        unsigned per_thread_scratch,
 856                                        gl_shader_stage stage);
 857 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 858                                  enum iris_surface_group group,
 859                                  uint32_t index);
 860 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 861                                  enum iris_surface_group group,
 862                                  uint32_t bti);
 863
 864 /* iris_disk_cache.c */
 865
 866 void iris_disk_cache_store(struct disk_cache *cache,
 867                            const struct iris_uncompiled_shader *ish,
 868                            const struct iris_compiled_shader *shader,
 869                            const void *prog_key,
 870                            uint32_t prog_key_size);
 871 struct iris_compiled_shader *
 872 iris_disk_cache_retrieve(struct iris_context *ice,
 873                          const struct iris_uncompiled_shader *ish,
 874                          const void *prog_key,
 875                          uint32_t prog_key_size);
 876
 877 /* iris_program_cache.c */
 878
 879 void iris_init_program_cache(struct iris_context *ice);
 880 void iris_destroy_program_cache(struct iris_context *ice);
 881 void iris_print_program_cache(struct iris_context *ice);
 882 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 883                                                      enum iris_program_cache_id,
 884                                                      uint32_t key_size,
 885                                                      const void *key);
 886 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 887                                                 enum iris_program_cache_id,
 888                                                 uint32_t key_size,
 889                                                 const void *key,
 890                                                 const void *assembly,
 891                                                 struct brw_stage_prog_data *,
 892                                                 uint32_t *streamout,
 893                                                 enum brw_param_builtin *sysv,
 894                                                 unsigned num_system_values,
 895                                                 unsigned kernel_input_size,
 896                                                 unsigned num_cbufs,
 897                                                 const struct iris_binding_table *bt);
 898 const void *iris_find_previous_compile(const struct iris_context *ice,
 899                                        enum iris_program_cache_id cache_id,
 900                                        unsigned program_string_id);
 901 void iris_delete_shader_variants(struct iris_context *ice,
 902                                  struct iris_uncompiled_shader *ish);
 903 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 904                               const void *key,
 905                               uint32_t key_size,
 906                               uint32_t *kernel_out,
 907                               void *prog_data_out);
 908 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
 909                               const void *key, uint32_t key_size,
 910                               const void *kernel, uint32_t kernel_size,
 911                               const struct brw_stage_prog_data *prog_data,
 912                               uint32_t prog_data_size,
 913                               uint32_t *kernel_out,
 914                               void *prog_data_out);
 915
 916 /* iris_resolve.c */
 917
 918 void iris_predraw_resolve_inputs(struct iris_context *ice,
 919                                  struct iris_batch *batch,
 920                                  bool *draw_aux_buffer_disabled,
 921                                  gl_shader_stage stage,
 922                                  bool consider_framebuffer);
 923 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 924                                       struct iris_batch *batch,
 925                                       bool *draw_aux_buffer_disabled);
 926 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 927                                            struct iris_batch *batch);
 928 void iris_cache_flush_for_render(struct iris_batch *batch,
 929                                  struct iris_bo *bo,
 930                                  enum isl_format format,
 931                                  enum isl_aux_usage aux_usage);
 932 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 933                                struct pipe_driver_query_info *info);
 934 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 935                                      unsigned index,
 936                                      struct pipe_driver_query_group_info *info);
 937
 938 /* iris_state.c */
 939 void gen9_toggle_preemption(struct iris_context *ice,
 940                             struct iris_batch *batch,
 941                             const struct pipe_draw_info *draw);
 942
 943
 944
 945 #ifdef genX
 946 #  include "iris_genx_protos.h"
 947 #else
 948 #  define genX(x) gen4_##x
 949 #  include "iris_genx_protos.h"
 950 #  undef genX
 951 #  define genX(x) gen5_##x
 952 #  include "iris_genx_protos.h"
 953 #  undef genX
 954 #  define genX(x) gen6_##x
 955 #  include "iris_genx_protos.h"
 956 #  undef genX
 957 #  define genX(x) gen7_##x
 958 #  include "iris_genx_protos.h"
 959 #  undef genX
 960 #  define genX(x) gen75_##x
 961 #  include "iris_genx_protos.h"
 962 #  undef genX
 963 #  define genX(x) gen8_##x
 964 #  include "iris_genx_protos.h"
 965 #  undef genX
 966 #  define genX(x) gen9_##x
 967 #  include "iris_genx_protos.h"
 968 #  undef genX
 969 #  define genX(x) gen10_##x
 970 #  include "iris_genx_protos.h"
 971 #  undef genX
 972 #  define genX(x) gen11_##x
 973 #  include "iris_genx_protos.h"
 974 #  undef genX
 975 #  define genX(x) gen12_##x
 976 #  include "iris_genx_protos.h"
 977 #  undef genX
 978 #endif
 979
 980 #endif