2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/slab.h"
29 #include "util/u_debug.h"
30 #include "intel/blorp/blorp.h"
31 #include "intel/dev/gen_debug.h"
32 #include "intel/common/gen_l3_config.h"
33 #include "intel/compiler/brw_compiler.h"
34 #include "iris_batch.h"
35 #include "iris_binder.h"
36 #include "iris_fence.h"
37 #include "iris_resource.h"
38 #include "iris_screen.h"
45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
48 #define IRIS_MAX_ABOS 16
49 #define IRIS_MAX_SSBOS 16
50 #define IRIS_MAX_VIEWPORTS 16
51 #define IRIS_MAX_CLIP_PLANES 8
52 #define IRIS_MAX_GLOBAL_BINDINGS 32
54 enum iris_param_domain
{
55 BRW_PARAM_DOMAIN_BUILTIN
= 0,
56 BRW_PARAM_DOMAIN_IMAGE
,
60 DRI_CONF_BO_REUSE_DISABLED
,
64 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
65 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
66 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
67 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
68 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
69 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
72 * Dirty flags. When state changes, we flag some combination of these
73 * to indicate that particular GPU commands need to be re-emitted.
75 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
76 * in rare cases they map to a group of related packets that need to be
79 * See iris_upload_render_state().
81 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
82 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
83 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
84 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
85 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
86 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
87 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
88 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
89 #define IRIS_DIRTY_RASTER (1ull << 8)
90 #define IRIS_DIRTY_CLIP (1ull << 9)
91 #define IRIS_DIRTY_SBE (1ull << 10)
92 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
93 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
94 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
95 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
96 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
97 #define IRIS_DIRTY_URB (1ull << 16)
98 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17)
99 #define IRIS_DIRTY_WM (1ull << 18)
100 #define IRIS_DIRTY_SO_BUFFERS (1ull << 19)
101 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 20)
102 #define IRIS_DIRTY_STREAMOUT (1ull << 21)
103 #define IRIS_DIRTY_VF_SGVS (1ull << 22)
104 #define IRIS_DIRTY_VF (1ull << 23)
105 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24)
106 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25)
107 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26)
108 #define IRIS_DIRTY_VF_STATISTICS (1ull << 27)
109 #define IRIS_DIRTY_PMA_FIX (1ull << 28)
110 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29)
111 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 30)
112 #define IRIS_DIRTY_STENCIL_REF (1ull << 31)
114 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
116 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
119 * Per-stage dirty flags. When state changes, we flag some combination of
120 * these to indicate that particular GPU commands need to be re-emitted.
121 * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
122 * indexed by shifting the mask by the shader stage index.
124 * See iris_upload_render_state().
126 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0)
127 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1)
128 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2)
129 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3)
130 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4)
131 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5)
132 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6)
133 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7)
134 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8)
135 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9)
136 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10)
137 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11)
138 #define IRIS_STAGE_DIRTY_VS (1ull << 12)
139 #define IRIS_STAGE_DIRTY_TCS (1ull << 13)
140 #define IRIS_STAGE_DIRTY_TES (1ull << 14)
141 #define IRIS_STAGE_DIRTY_GS (1ull << 15)
142 #define IRIS_STAGE_DIRTY_FS (1ull << 16)
143 #define IRIS_STAGE_DIRTY_CS (1ull << 17)
144 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18
145 #define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18)
146 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19)
147 #define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20)
148 #define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21)
149 #define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22)
150 #define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23)
151 #define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24)
152 #define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25)
153 #define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26)
154 #define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27)
155 #define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28)
156 #define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29)
158 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
159 IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
160 IRIS_STAGE_DIRTY_UNCOMPILED_CS | \
161 IRIS_STAGE_DIRTY_CONSTANTS_CS | \
162 IRIS_STAGE_DIRTY_BINDINGS_CS)
164 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
166 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_STAGE_DIRTY_BINDINGS_VS | \
167 IRIS_STAGE_DIRTY_BINDINGS_TCS | \
168 IRIS_STAGE_DIRTY_BINDINGS_TES | \
169 IRIS_STAGE_DIRTY_BINDINGS_GS | \
170 IRIS_STAGE_DIRTY_BINDINGS_FS | \
171 IRIS_STAGE_DIRTY_BINDINGS_CS)
174 * Non-orthogonal state (NOS) dependency flags.
176 * Shader programs may depend on non-orthogonal state. These flags are
177 * used to indicate that a shader's key depends on the state provided by
178 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
179 * cause the driver to re-compute the shader key, possibly triggering a
183 IRIS_NOS_FRAMEBUFFER
,
184 IRIS_NOS_DEPTH_STENCIL_ALPHA
,
187 IRIS_NOS_LAST_VUE_MAP
,
194 * Program cache keys for state based recompiles.
197 struct iris_base_prog_key
{
198 unsigned program_string_id
;
201 struct iris_vue_prog_key
{
202 struct iris_base_prog_key base
;
204 unsigned nr_userclip_plane_consts
:4;
207 struct iris_vs_prog_key
{
208 struct iris_vue_prog_key vue
;
211 struct iris_tcs_prog_key
{
212 struct iris_vue_prog_key vue
;
214 uint16_t tes_primitive_mode
;
216 uint8_t input_vertices
;
218 bool quads_workaround
;
220 /** A bitfield of per-patch outputs written. */
221 uint32_t patch_outputs_written
;
223 /** A bitfield of per-vertex outputs written. */
224 uint64_t outputs_written
;
227 struct iris_tes_prog_key
{
228 struct iris_vue_prog_key vue
;
230 /** A bitfield of per-patch inputs read. */
231 uint32_t patch_inputs_read
;
233 /** A bitfield of per-vertex inputs read. */
234 uint64_t inputs_read
;
237 struct iris_gs_prog_key
{
238 struct iris_vue_prog_key vue
;
241 struct iris_fs_prog_key
{
242 struct iris_base_prog_key base
;
244 unsigned nr_color_regions
:5;
246 bool alpha_test_replicate_alpha
:1;
247 bool alpha_to_coverage
:1;
248 bool clamp_fragment_color
:1;
249 bool persample_interp
:1;
250 bool multisample_fbo
:1;
251 bool force_dual_color_blend
:1;
252 bool coherent_fb_fetch
:1;
254 uint8_t color_outputs_valid
;
255 uint64_t input_slots_valid
;
258 struct iris_cs_prog_key
{
259 struct iris_base_prog_key base
;
264 struct iris_depth_stencil_alpha_state
;
267 * Cache IDs for the in-memory program cache (ice->shaders.cache).
269 enum iris_program_cache_id
{
270 IRIS_CACHE_VS
= MESA_SHADER_VERTEX
,
271 IRIS_CACHE_TCS
= MESA_SHADER_TESS_CTRL
,
272 IRIS_CACHE_TES
= MESA_SHADER_TESS_EVAL
,
273 IRIS_CACHE_GS
= MESA_SHADER_GEOMETRY
,
274 IRIS_CACHE_FS
= MESA_SHADER_FRAGMENT
,
275 IRIS_CACHE_CS
= MESA_SHADER_COMPUTE
,
281 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
282 * synchronization, pipelined memory writes, and so on.
284 * The bits here are not the actual hardware values. The actual fields
285 * move between various generations, so we just have flags for each
286 * potential operation, and use genxml to encode the actual packet.
288 enum pipe_control_flags
290 PIPE_CONTROL_FLUSH_LLC
= (1 << 1),
291 PIPE_CONTROL_LRI_POST_SYNC_OP
= (1 << 2),
292 PIPE_CONTROL_STORE_DATA_INDEX
= (1 << 3),
293 PIPE_CONTROL_CS_STALL
= (1 << 4),
294 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
= (1 << 5),
295 PIPE_CONTROL_SYNC_GFDT
= (1 << 6),
296 PIPE_CONTROL_TLB_INVALIDATE
= (1 << 7),
297 PIPE_CONTROL_MEDIA_STATE_CLEAR
= (1 << 8),
298 PIPE_CONTROL_WRITE_IMMEDIATE
= (1 << 9),
299 PIPE_CONTROL_WRITE_DEPTH_COUNT
= (1 << 10),
300 PIPE_CONTROL_WRITE_TIMESTAMP
= (1 << 11),
301 PIPE_CONTROL_DEPTH_STALL
= (1 << 12),
302 PIPE_CONTROL_RENDER_TARGET_FLUSH
= (1 << 13),
303 PIPE_CONTROL_INSTRUCTION_INVALIDATE
= (1 << 14),
304 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
= (1 << 15),
305 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
= (1 << 16),
306 PIPE_CONTROL_NOTIFY_ENABLE
= (1 << 17),
307 PIPE_CONTROL_FLUSH_ENABLE
= (1 << 18),
308 PIPE_CONTROL_DATA_CACHE_FLUSH
= (1 << 19),
309 PIPE_CONTROL_VF_CACHE_INVALIDATE
= (1 << 20),
310 PIPE_CONTROL_CONST_CACHE_INVALIDATE
= (1 << 21),
311 PIPE_CONTROL_STATE_CACHE_INVALIDATE
= (1 << 22),
312 PIPE_CONTROL_STALL_AT_SCOREBOARD
= (1 << 23),
313 PIPE_CONTROL_DEPTH_CACHE_FLUSH
= (1 << 24),
314 PIPE_CONTROL_TILE_CACHE_FLUSH
= (1 << 25),
315 PIPE_CONTROL_FLUSH_HDC
= (1 << 26),
318 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
319 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
320 PIPE_CONTROL_DATA_CACHE_FLUSH | \
321 PIPE_CONTROL_RENDER_TARGET_FLUSH)
323 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
324 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
325 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
326 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
327 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
328 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
330 enum iris_predicate_state
{
331 /* The first two states are used if we can determine whether to draw
332 * without having to look at the values in the query object buffer. This
333 * will happen if there is no conditional render in progress, if the query
334 * object is already completed or if something else has already added
335 * samples to the preliminary result.
337 IRIS_PREDICATE_STATE_RENDER
,
338 IRIS_PREDICATE_STATE_DONT_RENDER
,
340 /* In this case whether to draw or not depends on the result of an
341 * MI_PREDICATE command so the predicate enable bit needs to be checked.
343 IRIS_PREDICATE_STATE_USE_BIT
,
349 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
350 * It primarily contains the NIR for the shader.
352 * Each API-facing shader can be compiled into multiple shader variants,
353 * based on non-orthogonal state dependencies, recorded in the shader key.
355 * See iris_compiled_shader, which represents a compiled shader variant.
357 struct iris_uncompiled_shader
{
358 struct nir_shader
*nir
;
360 struct pipe_stream_output_info stream_output
;
362 /* A SHA1 of the serialized NIR for the disk cache. */
363 unsigned char nir_sha1
[20];
367 /** Bitfield of (1 << IRIS_NOS_*) flags. */
370 /** Have any shader variants been compiled yet? */
373 /** Should we use ALT mode for math? Useful for ARB programs. */
376 bool needs_edge_flag
;
378 /* Whether shader uses atomic operations. */
379 bool uses_atomic_load_store
;
381 /** Constant data scraped from the shader by nir_opt_large_constants */
382 struct pipe_resource
*const_data
;
384 /** Surface state for const_data */
385 struct iris_state_ref const_data_state
;
388 enum iris_surface_group
{
389 IRIS_SURFACE_GROUP_RENDER_TARGET
,
390 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
,
391 IRIS_SURFACE_GROUP_CS_WORK_GROUPS
,
392 IRIS_SURFACE_GROUP_TEXTURE
,
393 IRIS_SURFACE_GROUP_IMAGE
,
394 IRIS_SURFACE_GROUP_UBO
,
395 IRIS_SURFACE_GROUP_SSBO
,
397 IRIS_SURFACE_GROUP_COUNT
,
401 /* Invalid value for a binding table index. */
402 IRIS_SURFACE_NOT_USED
= 0xa0a0a0a0,
405 struct iris_binding_table
{
408 /** Number of surfaces in each group, before compacting. */
409 uint32_t sizes
[IRIS_SURFACE_GROUP_COUNT
];
411 /** Initial offset of each group. */
412 uint32_t offsets
[IRIS_SURFACE_GROUP_COUNT
];
414 /** Mask of surfaces used in each group. */
415 uint64_t used_mask
[IRIS_SURFACE_GROUP_COUNT
];
419 * A compiled shader variant, containing a pointer to the GPU assembly,
420 * as well as program data and other packets needed by state upload.
422 * There can be several iris_compiled_shader variants per API-level shader
423 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
425 struct iris_compiled_shader
{
426 struct list_head link
;
428 /** Reference to the uploaded assembly. */
429 struct iris_state_ref assembly
;
431 /** Pointer to the assembly in the BO's map. */
434 /** The program data (owned by the program cache hash table) */
435 struct brw_stage_prog_data
*prog_data
;
437 /** A list of system values to be uploaded as uniforms. */
438 enum brw_param_builtin
*system_values
;
439 unsigned num_system_values
;
441 /** Number of constbufs expected by the shader. */
445 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
446 * (the VUE-based information for transform feedback outputs).
450 struct iris_binding_table bt
;
453 * Shader packets and other data derived from prog_data. These must be
454 * completely determined from prog_data.
456 uint8_t derived_data
[0];
460 * API context state that is replicated per shader stage.
462 struct iris_shader_state
{
463 /** Uniform Buffers */
464 struct pipe_shader_buffer constbuf
[PIPE_MAX_CONSTANT_BUFFERS
];
465 struct iris_state_ref constbuf_surf_state
[PIPE_MAX_CONSTANT_BUFFERS
];
467 bool sysvals_need_upload
;
469 /** Shader Storage Buffers */
470 struct pipe_shader_buffer ssbo
[PIPE_MAX_SHADER_BUFFERS
];
471 struct iris_state_ref ssbo_surf_state
[PIPE_MAX_SHADER_BUFFERS
];
473 /** Shader Storage Images (image load store) */
474 struct iris_image_view image
[PIPE_MAX_SHADER_IMAGES
];
476 struct iris_state_ref sampler_table
;
477 struct iris_sampler_state
*samplers
[IRIS_MAX_TEXTURE_SAMPLERS
];
478 struct iris_sampler_view
*textures
[IRIS_MAX_TEXTURE_SAMPLERS
];
480 /** Bitfield of which constant buffers are bound (non-null). */
481 uint32_t bound_cbufs
;
483 /** Bitfield of which image views are bound (non-null). */
484 uint32_t bound_image_views
;
486 /** Bitfield of which sampler views are bound (non-null). */
487 uint32_t bound_sampler_views
;
489 /** Bitfield of which shader storage buffers are bound (non-null). */
490 uint32_t bound_ssbos
;
492 /** Bitfield of which shader storage buffers are writable. */
493 uint32_t writable_ssbos
;
497 * Gallium CSO for stream output (transform feedback) targets.
499 struct iris_stream_output_target
{
500 struct pipe_stream_output_target base
;
502 /** Storage holding the offset where we're writing in the buffer */
503 struct iris_state_ref offset
;
505 /** Stride (bytes-per-vertex) during this transform feedback operation */
508 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
513 * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
515 * See iris_border_color.c for more information.
517 struct iris_border_color_pool
{
520 unsigned insert_point
;
522 /** Map from border colors to offsets in the buffer. */
523 struct hash_table
*ht
;
527 * The API context (derived from pipe_context).
529 * Most driver state is tracked here.
531 struct iris_context
{
532 struct pipe_context ctx
;
534 /** A debug callback for KHR_debug output. */
535 struct pipe_debug_callback dbg
;
537 /** A device reset status callback for notifying that the GPU is hosed. */
538 struct pipe_device_reset_callback reset
;
540 /** Slab allocator for iris_transfer_map objects. */
541 struct slab_child_pool transfer_pool
;
543 struct blorp_context blorp
;
545 struct iris_batch batches
[IRIS_BATCH_COUNT
];
547 struct u_upload_mgr
*query_buffer_uploader
;
552 * Either the value of BaseVertex for indexed draw calls or the value
553 * of the argument <first> for non-indexed draw calls.
560 * Are the above values the ones stored in the draw_params buffer?
561 * If so, we can compare them against new values to see if anything
562 * changed. If not, we need to assume they changed.
567 * Resource and offset that stores draw_parameters from the indirect
568 * buffer or to the buffer that stures the previous values for non
571 struct iris_state_ref draw_params
;
575 * The value of DrawID. This always comes in from it's own vertex
576 * buffer since it's not part of the indirect draw parameters.
581 * Stores if an indexed or non-indexed draw (~0/0). Useful to
582 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
588 * Resource and offset used for GL_ARB_shader_draw_parameters which
589 * contains parameters that are not present in the indirect buffer as
590 * drawid and is_indexed_draw. They will go in their own vertex element.
592 struct iris_state_ref derived_draw_params
;
596 struct iris_uncompiled_shader
*uncompiled
[MESA_SHADER_STAGES
];
597 struct iris_compiled_shader
*prog
[MESA_SHADER_STAGES
];
598 struct brw_vue_map
*last_vue_map
;
600 /** List of shader variants whose deletion has been deferred for now */
601 struct list_head deleted_variants
[MESA_SHADER_STAGES
];
603 struct u_upload_mgr
*uploader
;
604 struct hash_table
*cache
;
606 /** Is a GS or TES outputting points or lines? */
607 bool output_topology_is_points_or_lines
;
610 * Scratch buffers for various sizes and stages.
612 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
615 struct iris_bo
*scratch_bos
[1 << 4][MESA_SHADER_STAGES
];
619 struct iris_query
*query
;
623 struct gen_perf_context
*perf_ctx
;
625 /** Frame number for debug prints */
630 uint64_t stage_dirty
;
631 uint64_t stage_dirty_for_nos
[IRIS_NOS_COUNT
];
633 unsigned num_viewports
;
634 unsigned sample_mask
;
635 struct iris_blend_state
*cso_blend
;
636 struct iris_rasterizer_state
*cso_rast
;
637 struct iris_depth_stencil_alpha_state
*cso_zsa
;
638 struct iris_vertex_element_state
*cso_vertex_elements
;
639 struct pipe_blend_color blend_color
;
640 struct pipe_poly_stipple poly_stipple
;
641 struct pipe_viewport_state viewports
[IRIS_MAX_VIEWPORTS
];
642 struct pipe_scissor_state scissors
[IRIS_MAX_VIEWPORTS
];
643 struct pipe_stencil_ref stencil_ref
;
644 struct pipe_framebuffer_state framebuffer
;
645 struct pipe_clip_state clip_planes
;
647 float default_outer_level
[4];
648 float default_inner_level
[2];
650 /** Bitfield of which vertex buffers are bound (non-null). */
651 uint64_t bound_vertex_buffers
;
653 bool primitive_restart
;
655 enum pipe_prim_type prim_mode
:8;
656 bool prim_is_points_or_lines
;
657 uint8_t vertices_per_patch
;
659 bool window_space_position
;
661 /** The last compute group size */
662 uint32_t last_block
[3];
664 /** The last compute grid size */
665 uint32_t last_grid
[3];
666 /** Reference to the BO containing the compute grid size */
667 struct iris_state_ref grid_size
;
668 /** Reference to the SURFACE_STATE for the compute grid resource */
669 struct iris_state_ref grid_surf_state
;
672 * Array of aux usages for drawing, altered to account for any
673 * self-dependencies from resources bound for sampling and rendering.
675 enum isl_aux_usage draw_aux_usage
[BRW_MAX_DRAW_BUFFERS
];
677 enum gen_urb_deref_block_size urb_deref_block_size
;
679 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
680 bool depth_writes_enabled
;
682 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
683 bool stencil_writes_enabled
;
685 /** GenX-specific current state */
686 struct iris_genx_state
*genx
;
688 struct iris_shader_state shaders
[MESA_SHADER_STAGES
];
690 /** Do vertex shader uses shader draw parameters ? */
691 bool vs_uses_draw_params
;
692 bool vs_uses_derived_draw_params
;
693 bool vs_needs_sgvs_element
;
695 /** Do vertex shader uses edge flag ? */
696 bool vs_needs_edge_flag
;
698 /** Do any samplers need border color? One bit per shader stage. */
699 uint8_t need_border_colors
;
701 /** Global resource bindings */
702 struct pipe_resource
*global_bindings
[IRIS_MAX_GLOBAL_BINDINGS
];
704 struct pipe_stream_output_target
*so_target
[PIPE_MAX_SO_BUFFERS
];
705 bool streamout_active
;
707 bool statistics_counters_enabled
;
709 /** Current conditional rendering mode */
710 enum iris_predicate_state predicate
;
713 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
714 * render context that needs to be uploaded to the compute context.
716 struct iris_bo
*compute_predicate
;
718 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
719 bool prims_generated_query_active
;
721 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
724 /** The SURFACE_STATE for a 1x1x1 null surface. */
725 struct iris_state_ref unbound_tex
;
727 /** The SURFACE_STATE for a framebuffer-sized null surface. */
728 struct iris_state_ref null_fb
;
730 struct u_upload_mgr
*surface_uploader
;
731 struct u_upload_mgr
*dynamic_uploader
;
733 struct iris_binder binder
;
735 struct iris_border_color_pool border_color_pool
;
737 /** The high 16-bits of the last VBO/index buffer addresses */
738 uint16_t last_vbo_high_bits
[33];
739 uint16_t last_index_bo_high_bits
;
742 * Resources containing streamed state which our render context
743 * currently points to. Used to re-add these to the validation
744 * list when we start a new batch and haven't resubmitted commands.
747 struct pipe_resource
*cc_vp
;
748 struct pipe_resource
*sf_cl_vp
;
749 struct pipe_resource
*color_calc
;
750 struct pipe_resource
*scissor
;
751 struct pipe_resource
*blend
;
752 struct pipe_resource
*index_buffer
;
753 struct pipe_resource
*cs_thread_ids
;
754 struct pipe_resource
*cs_desc
;
757 /** Records the size of variable-length state for INTEL_DEBUG=bat */
758 struct hash_table_u64
*sizes
;
760 /** Last rendering scale argument provided to genX(emit_hashing_mode). */
761 unsigned current_hash_scale
;
765 #define perf_debug(dbg, ...) do { \
766 if (INTEL_DEBUG & DEBUG_PERF) \
767 dbg_printf(__VA_ARGS__); \
769 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
772 double get_time(void);
774 struct pipe_context
*
775 iris_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
);
777 void iris_lost_context_state(struct iris_batch
*batch
);
779 void iris_init_blit_functions(struct pipe_context
*ctx
);
780 void iris_init_clear_functions(struct pipe_context
*ctx
);
781 void iris_init_program_functions(struct pipe_context
*ctx
);
782 void iris_init_resource_functions(struct pipe_context
*ctx
);
783 void iris_init_perfquery_functions(struct pipe_context
*ctx
);
784 void iris_update_compiled_shaders(struct iris_context
*ice
);
785 void iris_update_compiled_compute_shader(struct iris_context
*ice
);
786 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
792 void iris_blorp_surf_for_resource(struct isl_device
*isl_dev
,
793 struct blorp_surf
*surf
,
794 struct pipe_resource
*p_res
,
795 enum isl_aux_usage aux_usage
,
797 bool is_render_target
);
798 void iris_copy_region(struct blorp_context
*blorp
,
799 struct iris_batch
*batch
,
800 struct pipe_resource
*dst
,
802 unsigned dstx
, unsigned dsty
, unsigned dstz
,
803 struct pipe_resource
*src
,
805 const struct pipe_box
*src_box
);
809 void iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
810 void iris_launch_grid(struct pipe_context
*, const struct pipe_grid_info
*);
812 /* iris_pipe_control.c */
814 void iris_emit_pipe_control_flush(struct iris_batch
*batch
,
815 const char *reason
, uint32_t flags
);
816 void iris_emit_pipe_control_write(struct iris_batch
*batch
,
817 const char *reason
, uint32_t flags
,
818 struct iris_bo
*bo
, uint32_t offset
,
820 void iris_emit_end_of_pipe_sync(struct iris_batch
*batch
,
821 const char *reason
, uint32_t flags
);
822 void iris_emit_buffer_barrier_for(struct iris_batch
*batch
,
824 enum iris_domain access
);
825 void iris_flush_all_caches(struct iris_batch
*batch
);
827 #define iris_handle_always_flush_cache(batch) \
828 if (unlikely(batch->screen->driconf.always_flush_cache)) \
829 iris_flush_all_caches(batch);
831 void iris_init_flush_functions(struct pipe_context
*ctx
);
833 /* iris_border_color.c */
835 void iris_init_border_color_pool(struct iris_context
*ice
);
836 void iris_destroy_border_color_pool(struct iris_context
*ice
);
837 void iris_border_color_pool_reserve(struct iris_context
*ice
, unsigned count
);
838 uint32_t iris_upload_border_color(struct iris_context
*ice
,
839 union pipe_color_union
*color
);
842 void iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
843 struct pipe_shader_buffer
*buf
,
844 struct iris_state_ref
*surf_state
,
846 const struct shader_info
*iris_get_shader_info(const struct iris_context
*ice
,
847 gl_shader_stage stage
);
848 struct iris_bo
*iris_get_scratch_space(struct iris_context
*ice
,
849 unsigned per_thread_scratch
,
850 gl_shader_stage stage
);
851 uint32_t iris_group_index_to_bti(const struct iris_binding_table
*bt
,
852 enum iris_surface_group group
,
854 uint32_t iris_bti_to_group_index(const struct iris_binding_table
*bt
,
855 enum iris_surface_group group
,
858 /* iris_disk_cache.c */
860 void iris_disk_cache_store(struct disk_cache
*cache
,
861 const struct iris_uncompiled_shader
*ish
,
862 const struct iris_compiled_shader
*shader
,
863 const void *prog_key
,
864 uint32_t prog_key_size
);
865 struct iris_compiled_shader
*
866 iris_disk_cache_retrieve(struct iris_context
*ice
,
867 const struct iris_uncompiled_shader
*ish
,
868 const void *prog_key
,
869 uint32_t prog_key_size
);
871 /* iris_program_cache.c */
873 void iris_init_program_cache(struct iris_context
*ice
);
874 void iris_destroy_program_cache(struct iris_context
*ice
);
875 void iris_print_program_cache(struct iris_context
*ice
);
876 struct iris_compiled_shader
*iris_find_cached_shader(struct iris_context
*ice
,
877 enum iris_program_cache_id
,
880 struct iris_compiled_shader
*iris_upload_shader(struct iris_context
*ice
,
881 enum iris_program_cache_id
,
884 const void *assembly
,
885 struct brw_stage_prog_data
*,
887 enum brw_param_builtin
*sysv
,
888 unsigned num_system_values
,
890 const struct iris_binding_table
*bt
);
891 const void *iris_find_previous_compile(const struct iris_context
*ice
,
892 enum iris_program_cache_id cache_id
,
893 unsigned program_string_id
);
894 void iris_delete_shader_variants(struct iris_context
*ice
,
895 struct iris_uncompiled_shader
*ish
);
896 bool iris_blorp_lookup_shader(struct blorp_batch
*blorp_batch
,
899 uint32_t *kernel_out
,
900 void *prog_data_out
);
901 bool iris_blorp_upload_shader(struct blorp_batch
*blorp_batch
, uint32_t stage
,
902 const void *key
, uint32_t key_size
,
903 const void *kernel
, uint32_t kernel_size
,
904 const struct brw_stage_prog_data
*prog_data
,
905 uint32_t prog_data_size
,
906 uint32_t *kernel_out
,
907 void *prog_data_out
);
911 void iris_predraw_resolve_inputs(struct iris_context
*ice
,
912 struct iris_batch
*batch
,
913 bool *draw_aux_buffer_disabled
,
914 gl_shader_stage stage
,
915 bool consider_framebuffer
);
916 void iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
917 struct iris_batch
*batch
,
918 bool *draw_aux_buffer_disabled
);
919 void iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
920 struct iris_batch
*batch
);
921 void iris_cache_flush_for_render(struct iris_batch
*batch
,
923 enum isl_format format
,
924 enum isl_aux_usage aux_usage
);
925 int iris_get_driver_query_info(struct pipe_screen
*pscreen
, unsigned index
,
926 struct pipe_driver_query_info
*info
);
927 int iris_get_driver_query_group_info(struct pipe_screen
*pscreen
,
929 struct pipe_driver_query_group_info
*info
);
932 void gen9_toggle_preemption(struct iris_context
*ice
,
933 struct iris_batch
*batch
,
934 const struct pipe_draw_info
*draw
);
939 # include "iris_genx_protos.h"
941 # define genX(x) gen4_##x
942 # include "iris_genx_protos.h"
944 # define genX(x) gen5_##x
945 # include "iris_genx_protos.h"
947 # define genX(x) gen6_##x
948 # include "iris_genx_protos.h"
950 # define genX(x) gen7_##x
951 # include "iris_genx_protos.h"
953 # define genX(x) gen75_##x
954 # include "iris_genx_protos.h"
956 # define genX(x) gen8_##x
957 # include "iris_genx_protos.h"
959 # define genX(x) gen9_##x
960 # include "iris_genx_protos.h"
962 # define genX(x) gen10_##x
963 # include "iris_genx_protos.h"
965 # define genX(x) gen11_##x
966 # include "iris_genx_protos.h"
968 # define genX(x) gen12_##x
969 # include "iris_genx_protos.h"