2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
51 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
52 .base.tex.compressed_multisample_layout_mask = ~0, \
53 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
54 #define KEY_INIT(gen) .base.program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
57 get_new_program_id(struct iris_screen
*screen
)
59 return p_atomic_inc_return(&screen
->program_id
);
63 upload_state(struct u_upload_mgr
*uploader
,
64 struct iris_state_ref
*ref
,
69 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
74 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
75 struct pipe_shader_buffer
*buf
,
76 struct iris_state_ref
*surf_state
,
79 struct pipe_context
*ctx
= &ice
->ctx
;
80 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
83 upload_state(ice
->state
.surface_uploader
, surf_state
,
84 screen
->isl_dev
.ss
.size
, 64);
86 surf_state
->res
= NULL
;
90 struct iris_resource
*res
= (void *) buf
->buffer
;
91 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
92 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
94 isl_buffer_fill_state(&screen
->isl_dev
, map
,
95 .address
= res
->bo
->gtt_offset
+ res
->offset
+
97 .size_B
= buf
->buffer_size
- res
->offset
,
98 .format
= ssbo
? ISL_FORMAT_RAW
99 : ISL_FORMAT_R32G32B32A32_FLOAT
,
100 .swizzle
= ISL_SWIZZLE_IDENTITY
,
102 .mocs
= ice
->vtbl
.mocs(res
->bo
));
106 get_aoa_deref_offset(nir_builder
*b
,
107 nir_deref_instr
*deref
,
110 unsigned array_size
= elem_size
;
111 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
113 while (deref
->deref_type
!= nir_deref_type_var
) {
114 assert(deref
->deref_type
== nir_deref_type_array
);
116 /* This level's element size is the previous level's array size */
117 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
118 assert(deref
->arr
.index
.ssa
);
119 offset
= nir_iadd(b
, offset
,
120 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
122 deref
= nir_deref_instr_parent(deref
);
123 assert(glsl_type_is_array(deref
->type
));
124 array_size
*= glsl_get_length(deref
->type
);
127 /* Accessing an invalid surface index with the dataport can result in a
128 * hang. According to the spec "if the index used to select an individual
129 * element is negative or greater than or equal to the size of the array,
130 * the results of the operation are undefined but may not lead to
131 * termination" -- which is one of the possible outcomes of the hang.
132 * Clamp the index to prevent access outside of the array bounds.
134 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
138 iris_lower_storage_image_derefs(nir_shader
*nir
)
140 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
143 nir_builder_init(&b
, impl
);
145 nir_foreach_block(block
, impl
) {
146 nir_foreach_instr_safe(instr
, block
) {
147 if (instr
->type
!= nir_instr_type_intrinsic
)
150 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
151 switch (intrin
->intrinsic
) {
152 case nir_intrinsic_image_deref_load
:
153 case nir_intrinsic_image_deref_store
:
154 case nir_intrinsic_image_deref_atomic_add
:
155 case nir_intrinsic_image_deref_atomic_imin
:
156 case nir_intrinsic_image_deref_atomic_umin
:
157 case nir_intrinsic_image_deref_atomic_imax
:
158 case nir_intrinsic_image_deref_atomic_umax
:
159 case nir_intrinsic_image_deref_atomic_and
:
160 case nir_intrinsic_image_deref_atomic_or
:
161 case nir_intrinsic_image_deref_atomic_xor
:
162 case nir_intrinsic_image_deref_atomic_exchange
:
163 case nir_intrinsic_image_deref_atomic_comp_swap
:
164 case nir_intrinsic_image_deref_size
:
165 case nir_intrinsic_image_deref_samples
:
166 case nir_intrinsic_image_deref_load_raw_intel
:
167 case nir_intrinsic_image_deref_store_raw_intel
: {
168 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
169 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
171 b
.cursor
= nir_before_instr(&intrin
->instr
);
173 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
174 get_aoa_deref_offset(&b
, deref
, 1));
175 nir_rewrite_image_intrinsic(intrin
, index
, false);
186 // XXX: need unify_interfaces() at link time...
189 * Fix an uncompiled shader's stream output info.
191 * Core Gallium stores output->register_index as a "slot" number, where
192 * slots are assigned consecutively to all outputs in info->outputs_written.
193 * This naive packing of outputs doesn't work for us - we too have slots,
194 * but the layout is defined by the VUE map, which we won't have until we
195 * compile a specific shader variant. So, we remap these and simply store
196 * VARYING_SLOT_* in our copy's output->register_index fields.
198 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
199 * components of our VUE header. See brw_vue_map.c for the layout.
202 update_so_info(struct pipe_stream_output_info
*so_info
,
203 uint64_t outputs_written
)
205 uint8_t reverse_map
[64] = {};
207 while (outputs_written
) {
208 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
211 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
212 struct pipe_stream_output
*output
= &so_info
->output
[i
];
214 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
215 output
->register_index
= reverse_map
[output
->register_index
];
217 /* The VUE header contains three scalar fields packed together:
218 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
219 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
220 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
222 switch (output
->register_index
) {
223 case VARYING_SLOT_LAYER
:
224 assert(output
->num_components
== 1);
225 output
->register_index
= VARYING_SLOT_PSIZ
;
226 output
->start_component
= 1;
228 case VARYING_SLOT_VIEWPORT
:
229 assert(output
->num_components
== 1);
230 output
->register_index
= VARYING_SLOT_PSIZ
;
231 output
->start_component
= 2;
233 case VARYING_SLOT_PSIZ
:
234 assert(output
->num_components
== 1);
235 output
->start_component
= 3;
239 //info->outputs_written |= 1ull << output->register_index;
244 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
245 unsigned offset
, unsigned n
)
247 assert(offset
% sizeof(uint32_t) == 0);
249 for (unsigned i
= 0; i
< n
; ++i
)
250 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
252 for (unsigned i
= n
; i
< 4; ++i
)
253 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
257 * Associate NIR uniform variables with the prog_data->param[] mechanism
258 * used by the backend. Also, decide which UBOs we'd like to push in an
259 * ideal situation (though the backend can reduce this).
262 iris_setup_uniforms(const struct brw_compiler
*compiler
,
265 struct brw_stage_prog_data
*prog_data
,
266 enum brw_param_builtin
**out_system_values
,
267 unsigned *out_num_system_values
,
268 unsigned *out_num_cbufs
)
270 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
272 /* The intel compiler assumes that num_uniforms is in bytes. For
273 * scalar that means 4 bytes per uniform slot.
275 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
277 nir
->num_uniforms
*= 4;
279 const unsigned IRIS_MAX_SYSTEM_VALUES
=
280 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
281 enum brw_param_builtin
*system_values
=
282 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
283 unsigned num_system_values
= 0;
285 unsigned patch_vert_idx
= -1;
286 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
287 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
288 memset(ucp_idx
, -1, sizeof(ucp_idx
));
289 memset(img_idx
, -1, sizeof(img_idx
));
291 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
294 nir_builder_init(&b
, impl
);
296 b
.cursor
= nir_before_block(nir_start_block(impl
));
297 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
298 nir_ssa_def
*temp_const_ubo_name
= NULL
;
300 /* Turn system value intrinsics into uniforms */
301 nir_foreach_block(block
, impl
) {
302 nir_foreach_instr_safe(instr
, block
) {
303 if (instr
->type
!= nir_instr_type_intrinsic
)
306 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
309 switch (intrin
->intrinsic
) {
310 case nir_intrinsic_load_constant
: {
311 /* This one is special because it reads from the shader constant
312 * data and not cbuf0 which gallium uploads for us.
314 b
.cursor
= nir_before_instr(instr
);
315 nir_ssa_def
*offset
=
316 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
317 nir_intrinsic_base(intrin
));
319 if (temp_const_ubo_name
== NULL
)
320 temp_const_ubo_name
= nir_imm_int(&b
, 0);
322 nir_intrinsic_instr
*load_ubo
=
323 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
324 load_ubo
->num_components
= intrin
->num_components
;
325 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
326 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
327 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
328 intrin
->dest
.ssa
.num_components
,
329 intrin
->dest
.ssa
.bit_size
,
330 intrin
->dest
.ssa
.name
);
331 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
333 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
334 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
335 nir_instr_remove(&intrin
->instr
);
338 case nir_intrinsic_load_user_clip_plane
: {
339 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
341 if (ucp_idx
[ucp
] == -1) {
342 ucp_idx
[ucp
] = num_system_values
;
343 num_system_values
+= 4;
346 for (int i
= 0; i
< 4; i
++) {
347 system_values
[ucp_idx
[ucp
] + i
] =
348 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
351 b
.cursor
= nir_before_instr(instr
);
352 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
355 case nir_intrinsic_load_patch_vertices_in
:
356 if (patch_vert_idx
== -1)
357 patch_vert_idx
= num_system_values
++;
359 system_values
[patch_vert_idx
] =
360 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
362 b
.cursor
= nir_before_instr(instr
);
363 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
365 case nir_intrinsic_image_deref_load_param_intel
: {
366 assert(devinfo
->gen
< 9);
367 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
368 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
370 if (img_idx
[var
->data
.binding
] == -1) {
371 /* GL only allows arrays of arrays of images. */
372 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
373 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
375 for (int i
= 0; i
< num_images
; i
++) {
376 const unsigned img
= var
->data
.binding
+ i
;
378 img_idx
[img
] = num_system_values
;
379 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
381 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
383 setup_vec4_image_sysval(
384 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
385 offsetof(struct brw_image_param
, offset
), 2);
386 setup_vec4_image_sysval(
387 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
388 offsetof(struct brw_image_param
, size
), 3);
389 setup_vec4_image_sysval(
390 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
391 offsetof(struct brw_image_param
, stride
), 4);
392 setup_vec4_image_sysval(
393 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
394 offsetof(struct brw_image_param
, tiling
), 3);
395 setup_vec4_image_sysval(
396 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
397 offsetof(struct brw_image_param
, swizzling
), 2);
401 b
.cursor
= nir_before_instr(instr
);
402 offset
= nir_iadd(&b
,
403 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
404 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
405 nir_intrinsic_base(intrin
) * 16));
412 unsigned comps
= nir_intrinsic_dest_components(intrin
);
414 nir_intrinsic_instr
*load
=
415 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
416 load
->num_components
= comps
;
417 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
418 load
->src
[1] = nir_src_for_ssa(offset
);
419 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
420 nir_builder_instr_insert(&b
, &load
->instr
);
421 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
422 nir_src_for_ssa(&load
->dest
.ssa
));
423 nir_instr_remove(instr
);
427 nir_validate_shader(nir
, "before remapping");
429 /* Uniforms are stored in constant buffer 0, the
430 * user-facing UBOs are indexed by one. So if any constant buffer is
431 * needed, the constant buffer 0 will be needed, so account for it.
433 unsigned num_cbufs
= nir
->info
.num_ubos
;
434 if (num_cbufs
|| nir
->num_uniforms
)
437 /* Place the new params in a new cbuf. */
438 if (num_system_values
> 0) {
439 unsigned sysval_cbuf_index
= num_cbufs
;
442 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
445 nir_foreach_block(block
, impl
) {
446 nir_foreach_instr_safe(instr
, block
) {
447 if (instr
->type
!= nir_instr_type_intrinsic
)
450 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
452 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
455 b
.cursor
= nir_before_instr(instr
);
457 assert(load
->src
[0].is_ssa
);
459 if (load
->src
[0].ssa
== temp_ubo_name
) {
460 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
461 nir_instr_rewrite_src(instr
, &load
->src
[0],
462 nir_src_for_ssa(imm
));
467 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
468 nir_opt_constant_folding(nir
);
470 ralloc_free(system_values
);
471 system_values
= NULL
;
474 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
475 nir_validate_shader(nir
, "after remap");
477 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
478 * about it for compute shaders, so go ahead and make some fake ones
479 * which the backend will dead code eliminate.
481 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
482 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
484 /* Constant loads (if any) need to go at the end of the constant buffers so
485 * we need to know num_cbufs before we can lower to them.
487 if (temp_const_ubo_name
!= NULL
) {
488 nir_load_const_instr
*const_ubo_index
=
489 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
490 assert(const_ubo_index
->def
.bit_size
== 32);
491 const_ubo_index
->value
[0].u32
= num_cbufs
;
494 *out_system_values
= system_values
;
495 *out_num_system_values
= num_system_values
;
496 *out_num_cbufs
= num_cbufs
;
499 static const char *surface_group_names
[] = {
500 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
501 [IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = "non-coherent render target read",
502 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
503 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
504 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
505 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
506 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
510 iris_print_binding_table(FILE *fp
, const char *name
,
511 const struct iris_binding_table
*bt
)
513 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
516 uint32_t compacted
= 0;
518 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
519 uint32_t size
= bt
->sizes
[i
];
522 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
526 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
530 if (total
!= compacted
) {
531 fprintf(fp
, "Binding table for %s "
532 "(compacted to %u entries from %u entries)\n",
533 name
, compacted
, total
);
535 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
539 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
540 uint64_t mask
= bt
->used_mask
[i
];
542 int index
= u_bit_scan64(&mask
);
543 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
550 /* Max elements in a surface group. */
551 SURFACE_GROUP_MAX_ELEMENTS
= 64,
555 * Map a <group, index> pair to a binding table index.
557 * For example: <UBO, 5> => binding table index 12
560 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
561 enum iris_surface_group group
, uint32_t index
)
563 assert(index
< bt
->sizes
[group
]);
564 uint64_t mask
= bt
->used_mask
[group
];
565 uint64_t bit
= 1ull << index
;
567 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
569 return IRIS_SURFACE_NOT_USED
;
574 * Map a binding table index back to a <group, index> pair.
576 * For example: binding table index 12 => <UBO, 5>
579 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
580 enum iris_surface_group group
, uint32_t bti
)
582 uint64_t used_mask
= bt
->used_mask
[group
];
583 assert(bti
>= bt
->offsets
[group
]);
585 uint32_t c
= bti
- bt
->offsets
[group
];
587 int i
= u_bit_scan64(&used_mask
);
593 return IRIS_SURFACE_NOT_USED
;
597 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
598 nir_instr
*instr
, nir_src
*src
,
599 enum iris_surface_group group
)
601 assert(bt
->sizes
[group
] > 0);
603 b
->cursor
= nir_before_instr(instr
);
605 if (nir_src_is_const(*src
)) {
606 uint32_t index
= nir_src_as_uint(*src
);
607 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
610 /* Indirect usage makes all the surfaces of the group to be available,
611 * so we can just add the base.
613 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
614 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
616 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
620 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
621 enum iris_surface_group group
)
623 assert(bt
->sizes
[group
] > 0);
625 if (nir_src_is_const(*src
)) {
626 uint64_t index
= nir_src_as_uint(*src
);
627 assert(index
< bt
->sizes
[group
]);
628 bt
->used_mask
[group
] |= 1ull << index
;
630 /* There's an indirect usage, we need all the surfaces. */
631 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
636 skip_compacting_binding_tables(void)
638 static int skip
= -1;
640 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
645 * Set up the binding table indices and apply to the shader.
648 iris_setup_binding_table(const struct gen_device_info
*devinfo
,
649 struct nir_shader
*nir
,
650 struct iris_binding_table
*bt
,
651 unsigned num_render_targets
,
652 unsigned num_system_values
,
655 const struct shader_info
*info
= &nir
->info
;
657 memset(bt
, 0, sizeof(*bt
));
659 /* Set the sizes for each surface group. For some groups, we already know
660 * upfront how many will be used, so mark them.
662 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
663 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
664 /* All render targets used. */
665 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
666 BITFIELD64_MASK(num_render_targets
);
668 /* Setup render target read surface group inorder to support non-coherent
669 * framebuffer fetch on Gen8
671 if (devinfo
->gen
== 8 && info
->outputs_read
) {
672 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = num_render_targets
;
673 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] =
674 BITFIELD64_MASK(num_render_targets
);
676 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
677 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
680 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
681 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
683 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
685 /* Allocate an extra slot in the UBO section for NIR constants.
686 * Binding table compaction will remove it if unnecessary.
688 * We don't include them in iris_compiled_shader::num_cbufs because
689 * they are uploaded separately from shs->constbuf[], but from a shader
690 * point of view, they're another UBO (at the end of the section).
692 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
694 /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
695 * SSBOs start after that. Compaction will remove unused ABOs.
697 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = IRIS_MAX_ABOS
+ info
->num_ssbos
;
699 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
700 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
702 /* Mark surfaces used for the cases we don't have the information available
705 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
706 nir_foreach_block (block
, impl
) {
707 nir_foreach_instr (instr
, block
) {
708 if (instr
->type
!= nir_instr_type_intrinsic
)
711 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
712 switch (intrin
->intrinsic
) {
713 case nir_intrinsic_load_num_work_groups
:
714 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
717 case nir_intrinsic_load_output
:
718 if (devinfo
->gen
== 8) {
719 mark_used_with_src(bt
, &intrin
->src
[0],
720 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
724 case nir_intrinsic_image_size
:
725 case nir_intrinsic_image_load
:
726 case nir_intrinsic_image_store
:
727 case nir_intrinsic_image_atomic_add
:
728 case nir_intrinsic_image_atomic_imin
:
729 case nir_intrinsic_image_atomic_umin
:
730 case nir_intrinsic_image_atomic_imax
:
731 case nir_intrinsic_image_atomic_umax
:
732 case nir_intrinsic_image_atomic_and
:
733 case nir_intrinsic_image_atomic_or
:
734 case nir_intrinsic_image_atomic_xor
:
735 case nir_intrinsic_image_atomic_exchange
:
736 case nir_intrinsic_image_atomic_comp_swap
:
737 case nir_intrinsic_image_load_raw_intel
:
738 case nir_intrinsic_image_store_raw_intel
:
739 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
742 case nir_intrinsic_load_ubo
:
743 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
746 case nir_intrinsic_store_ssbo
:
747 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
750 case nir_intrinsic_get_buffer_size
:
751 case nir_intrinsic_ssbo_atomic_add
:
752 case nir_intrinsic_ssbo_atomic_imin
:
753 case nir_intrinsic_ssbo_atomic_umin
:
754 case nir_intrinsic_ssbo_atomic_imax
:
755 case nir_intrinsic_ssbo_atomic_umax
:
756 case nir_intrinsic_ssbo_atomic_and
:
757 case nir_intrinsic_ssbo_atomic_or
:
758 case nir_intrinsic_ssbo_atomic_xor
:
759 case nir_intrinsic_ssbo_atomic_exchange
:
760 case nir_intrinsic_ssbo_atomic_comp_swap
:
761 case nir_intrinsic_ssbo_atomic_fmin
:
762 case nir_intrinsic_ssbo_atomic_fmax
:
763 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
764 case nir_intrinsic_load_ssbo
:
765 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
774 /* When disable we just mark everything as used. */
775 if (unlikely(skip_compacting_binding_tables())) {
776 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
777 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
780 /* Calculate the offsets and the binding table size based on the used
781 * surfaces. After this point, the functions to go between "group indices"
782 * and binding table indices can be used.
785 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
786 if (bt
->used_mask
[i
] != 0) {
787 bt
->offsets
[i
] = next
;
788 next
+= util_bitcount64(bt
->used_mask
[i
]);
791 bt
->size_bytes
= next
* 4;
793 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
794 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
797 /* Apply the binding table indices. The backend compiler is not expected
798 * to change those, as we haven't set any of the *_start entries in brw
802 nir_builder_init(&b
, impl
);
804 nir_foreach_block (block
, impl
) {
805 nir_foreach_instr (instr
, block
) {
806 if (instr
->type
== nir_instr_type_tex
) {
807 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
809 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
814 if (instr
->type
!= nir_instr_type_intrinsic
)
817 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
818 switch (intrin
->intrinsic
) {
819 case nir_intrinsic_image_size
:
820 case nir_intrinsic_image_load
:
821 case nir_intrinsic_image_store
:
822 case nir_intrinsic_image_atomic_add
:
823 case nir_intrinsic_image_atomic_imin
:
824 case nir_intrinsic_image_atomic_umin
:
825 case nir_intrinsic_image_atomic_imax
:
826 case nir_intrinsic_image_atomic_umax
:
827 case nir_intrinsic_image_atomic_and
:
828 case nir_intrinsic_image_atomic_or
:
829 case nir_intrinsic_image_atomic_xor
:
830 case nir_intrinsic_image_atomic_exchange
:
831 case nir_intrinsic_image_atomic_comp_swap
:
832 case nir_intrinsic_image_load_raw_intel
:
833 case nir_intrinsic_image_store_raw_intel
:
834 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
835 IRIS_SURFACE_GROUP_IMAGE
);
838 case nir_intrinsic_load_ubo
:
839 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
840 IRIS_SURFACE_GROUP_UBO
);
843 case nir_intrinsic_store_ssbo
:
844 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
845 IRIS_SURFACE_GROUP_SSBO
);
848 case nir_intrinsic_load_output
:
849 if (devinfo
->gen
== 8) {
850 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
851 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
855 case nir_intrinsic_get_buffer_size
:
856 case nir_intrinsic_ssbo_atomic_add
:
857 case nir_intrinsic_ssbo_atomic_imin
:
858 case nir_intrinsic_ssbo_atomic_umin
:
859 case nir_intrinsic_ssbo_atomic_imax
:
860 case nir_intrinsic_ssbo_atomic_umax
:
861 case nir_intrinsic_ssbo_atomic_and
:
862 case nir_intrinsic_ssbo_atomic_or
:
863 case nir_intrinsic_ssbo_atomic_xor
:
864 case nir_intrinsic_ssbo_atomic_exchange
:
865 case nir_intrinsic_ssbo_atomic_comp_swap
:
866 case nir_intrinsic_ssbo_atomic_fmin
:
867 case nir_intrinsic_ssbo_atomic_fmax
:
868 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
869 case nir_intrinsic_load_ssbo
:
870 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
871 IRIS_SURFACE_GROUP_SSBO
);
882 iris_debug_recompile(struct iris_context
*ice
,
883 struct shader_info
*info
,
884 const struct brw_base_prog_key
*key
)
886 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
887 const struct brw_compiler
*c
= screen
->compiler
;
892 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
893 _mesa_shader_stage_to_string(info
->stage
),
894 info
->name
? info
->name
: "(no identifier)",
895 info
->label
? info
->label
: "");
897 const void *old_key
=
898 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
900 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
904 * Get the shader for the last enabled geometry stage.
906 * This stage is the one which will feed stream output and the rasterizer.
908 static gl_shader_stage
909 last_vue_stage(struct iris_context
*ice
)
911 if (ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
912 return MESA_SHADER_GEOMETRY
;
914 if (ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
915 return MESA_SHADER_TESS_EVAL
;
917 return MESA_SHADER_VERTEX
;
921 * Compile a vertex shader, and upload the assembly.
923 static struct iris_compiled_shader
*
924 iris_compile_vs(struct iris_context
*ice
,
925 struct iris_uncompiled_shader
*ish
,
926 const struct brw_vs_prog_key
*key
)
928 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
929 const struct brw_compiler
*compiler
= screen
->compiler
;
930 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
931 void *mem_ctx
= ralloc_context(NULL
);
932 struct brw_vs_prog_data
*vs_prog_data
=
933 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
934 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
935 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
936 enum brw_param_builtin
*system_values
;
937 unsigned num_system_values
;
940 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
942 if (key
->nr_userclip_plane_consts
) {
943 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
944 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
945 nir_lower_io_to_temporaries(nir
, impl
, true, false);
946 nir_lower_global_vars_to_local(nir
);
947 nir_lower_vars_to_ssa(nir
);
948 nir_shader_gather_info(nir
, impl
);
951 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
953 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
954 &num_system_values
, &num_cbufs
);
956 struct iris_binding_table bt
;
957 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
958 num_system_values
, num_cbufs
);
960 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
962 brw_compute_vue_map(devinfo
,
963 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
964 nir
->info
.separate_shader
);
966 /* Don't tell the backend about our clip plane constants, we've already
967 * lowered them in NIR and we don't want it doing it again.
969 struct brw_vs_prog_key key_no_ucp
= *key
;
970 key_no_ucp
.nr_userclip_plane_consts
= 0;
972 char *error_str
= NULL
;
973 const unsigned *program
=
974 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
975 nir
, -1, NULL
, &error_str
);
976 if (program
== NULL
) {
977 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
978 ralloc_free(mem_ctx
);
982 if (ish
->compiled_once
) {
983 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
985 ish
->compiled_once
= true;
989 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
990 &vue_prog_data
->vue_map
);
992 struct iris_compiled_shader
*shader
=
993 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
994 prog_data
, so_decls
, system_values
, num_system_values
,
997 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
999 ralloc_free(mem_ctx
);
1004 * Update the current vertex shader variant.
1006 * Fill out the key, look in the cache, compile and bind if needed.
1009 iris_update_compiled_vs(struct iris_context
*ice
)
1011 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1012 struct iris_uncompiled_shader
*ish
=
1013 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
1014 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1015 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1017 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1018 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1020 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
1021 struct iris_compiled_shader
*shader
=
1022 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
1025 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1028 shader
= iris_compile_vs(ice
, ish
, &key
);
1030 if (old
!= shader
) {
1031 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
1032 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
1033 IRIS_DIRTY_BINDINGS_VS
|
1034 IRIS_DIRTY_CONSTANTS_VS
|
1036 shs
->sysvals_need_upload
= true;
1038 const struct brw_vs_prog_data
*vs_prog_data
=
1039 (void *) shader
->prog_data
;
1040 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
1041 vs_prog_data
->uses_baseinstance
;
1042 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
1043 vs_prog_data
->uses_is_indexed_draw
;
1044 const bool needs_sgvs_element
= uses_draw_params
||
1045 vs_prog_data
->uses_instanceid
||
1046 vs_prog_data
->uses_vertexid
;
1047 bool needs_edge_flag
= false;
1048 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1049 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1050 needs_edge_flag
= true;
1053 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1054 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1055 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1056 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1057 IRIS_DIRTY_VERTEX_ELEMENTS
;
1059 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1060 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1061 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1062 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1067 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1069 const struct shader_info
*
1070 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1072 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1077 const nir_shader
*nir
= ish
->nir
;
1082 * Get the union of TCS output and TES input slots.
1084 * TCS and TES need to agree on a common URB entry layout. In particular,
1085 * the data for all patch vertices is stored in a single URB entry (unlike
1086 * GS which has one entry per input vertex). This means that per-vertex
1087 * array indexing needs a stride.
1089 * SSO requires locations to match, but doesn't require the number of
1090 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1091 * So, we need to take the extra step of unifying these on the fly.
1094 get_unified_tess_slots(const struct iris_context
*ice
,
1095 uint64_t *per_vertex_slots
,
1096 uint32_t *per_patch_slots
)
1098 const struct shader_info
*tcs
=
1099 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1100 const struct shader_info
*tes
=
1101 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1103 *per_vertex_slots
= tes
->inputs_read
;
1104 *per_patch_slots
= tes
->patch_inputs_read
;
1107 *per_vertex_slots
|= tcs
->outputs_written
;
1108 *per_patch_slots
|= tcs
->patch_outputs_written
;
1113 * Compile a tessellation control shader, and upload the assembly.
1115 static struct iris_compiled_shader
*
1116 iris_compile_tcs(struct iris_context
*ice
,
1117 struct iris_uncompiled_shader
*ish
,
1118 const struct brw_tcs_prog_key
*key
)
1120 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1121 const struct brw_compiler
*compiler
= screen
->compiler
;
1122 const struct nir_shader_compiler_options
*options
=
1123 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1124 void *mem_ctx
= ralloc_context(NULL
);
1125 struct brw_tcs_prog_data
*tcs_prog_data
=
1126 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1127 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1128 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1129 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1130 enum brw_param_builtin
*system_values
= NULL
;
1131 unsigned num_system_values
= 0;
1132 unsigned num_cbufs
= 0;
1136 struct iris_binding_table bt
;
1139 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1141 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1142 &num_system_values
, &num_cbufs
);
1143 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1144 num_system_values
, num_cbufs
);
1145 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1147 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1149 /* Reserve space for passing the default tess levels as constants. */
1151 num_system_values
= 8;
1153 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1154 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1155 prog_data
->nr_params
= num_system_values
;
1157 if (key
->tes_primitive_mode
== GL_QUADS
) {
1158 for (int i
= 0; i
< 4; i
++)
1159 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1161 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1162 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1163 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1164 for (int i
= 0; i
< 3; i
++)
1165 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1167 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1169 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1170 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1171 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1174 /* Manually setup the TCS binding table. */
1175 memset(&bt
, 0, sizeof(bt
));
1176 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1177 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1180 prog_data
->ubo_ranges
[0].length
= 1;
1183 char *error_str
= NULL
;
1184 const unsigned *program
=
1185 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1186 -1, NULL
, &error_str
);
1187 if (program
== NULL
) {
1188 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1189 ralloc_free(mem_ctx
);
1194 if (ish
->compiled_once
) {
1195 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1197 ish
->compiled_once
= true;
1201 struct iris_compiled_shader
*shader
=
1202 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1203 prog_data
, NULL
, system_values
, num_system_values
,
1207 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1209 ralloc_free(mem_ctx
);
1214 * Update the current tessellation control shader variant.
1216 * Fill out the key, look in the cache, compile and bind if needed.
1219 iris_update_compiled_tcs(struct iris_context
*ice
)
1221 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1222 struct iris_uncompiled_shader
*tcs
=
1223 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1224 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1225 const struct brw_compiler
*compiler
= screen
->compiler
;
1226 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1228 const struct shader_info
*tes_info
=
1229 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1230 struct brw_tcs_prog_key key
= {
1231 KEY_INIT_NO_ID(devinfo
->gen
),
1232 .base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1233 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1235 !tcs
|| compiler
->use_tcs_8_patch
? ice
->state
.vertices_per_patch
: 0,
1237 get_unified_tess_slots(ice
, &key
.outputs_written
,
1238 &key
.patch_outputs_written
);
1239 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1241 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1242 struct iris_compiled_shader
*shader
=
1243 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1246 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1249 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1251 if (old
!= shader
) {
1252 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1253 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1254 IRIS_DIRTY_BINDINGS_TCS
|
1255 IRIS_DIRTY_CONSTANTS_TCS
;
1256 shs
->sysvals_need_upload
= true;
1261 * Compile a tessellation evaluation shader, and upload the assembly.
1263 static struct iris_compiled_shader
*
1264 iris_compile_tes(struct iris_context
*ice
,
1265 struct iris_uncompiled_shader
*ish
,
1266 const struct brw_tes_prog_key
*key
)
1268 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1269 const struct brw_compiler
*compiler
= screen
->compiler
;
1270 void *mem_ctx
= ralloc_context(NULL
);
1271 struct brw_tes_prog_data
*tes_prog_data
=
1272 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1273 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1274 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1275 enum brw_param_builtin
*system_values
;
1276 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1277 unsigned num_system_values
;
1280 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1282 if (key
->nr_userclip_plane_consts
) {
1283 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1284 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
1285 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1286 nir_lower_global_vars_to_local(nir
);
1287 nir_lower_vars_to_ssa(nir
);
1288 nir_shader_gather_info(nir
, impl
);
1291 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1292 &num_system_values
, &num_cbufs
);
1294 struct iris_binding_table bt
;
1295 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1296 num_system_values
, num_cbufs
);
1298 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1300 struct brw_vue_map input_vue_map
;
1301 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1302 key
->patch_inputs_read
);
1304 char *error_str
= NULL
;
1305 const unsigned *program
=
1306 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1307 tes_prog_data
, nir
, NULL
, -1, NULL
, &error_str
);
1308 if (program
== NULL
) {
1309 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1310 ralloc_free(mem_ctx
);
1314 if (ish
->compiled_once
) {
1315 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1317 ish
->compiled_once
= true;
1320 uint32_t *so_decls
=
1321 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1322 &vue_prog_data
->vue_map
);
1325 struct iris_compiled_shader
*shader
=
1326 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1327 prog_data
, so_decls
, system_values
, num_system_values
,
1330 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1332 ralloc_free(mem_ctx
);
1337 * Update the current tessellation evaluation shader variant.
1339 * Fill out the key, look in the cache, compile and bind if needed.
1342 iris_update_compiled_tes(struct iris_context
*ice
)
1344 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1345 struct iris_uncompiled_shader
*ish
=
1346 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1347 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1348 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1350 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1351 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1352 ice
->vtbl
.populate_tes_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1354 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1355 struct iris_compiled_shader
*shader
=
1356 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1359 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1362 shader
= iris_compile_tes(ice
, ish
, &key
);
1364 if (old
!= shader
) {
1365 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1366 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1367 IRIS_DIRTY_BINDINGS_TES
|
1368 IRIS_DIRTY_CONSTANTS_TES
;
1369 shs
->sysvals_need_upload
= true;
1372 /* TODO: Could compare and avoid flagging this. */
1373 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1374 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1375 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1376 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1381 * Compile a geometry shader, and upload the assembly.
1383 static struct iris_compiled_shader
*
1384 iris_compile_gs(struct iris_context
*ice
,
1385 struct iris_uncompiled_shader
*ish
,
1386 const struct brw_gs_prog_key
*key
)
1388 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1389 const struct brw_compiler
*compiler
= screen
->compiler
;
1390 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1391 void *mem_ctx
= ralloc_context(NULL
);
1392 struct brw_gs_prog_data
*gs_prog_data
=
1393 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1394 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1395 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1396 enum brw_param_builtin
*system_values
;
1397 unsigned num_system_values
;
1400 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1402 if (key
->nr_userclip_plane_consts
) {
1403 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1404 nir_lower_clip_gs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1);
1405 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1406 nir_lower_global_vars_to_local(nir
);
1407 nir_lower_vars_to_ssa(nir
);
1408 nir_shader_gather_info(nir
, impl
);
1411 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1412 &num_system_values
, &num_cbufs
);
1414 struct iris_binding_table bt
;
1415 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1416 num_system_values
, num_cbufs
);
1418 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1420 brw_compute_vue_map(devinfo
,
1421 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1422 nir
->info
.separate_shader
);
1424 char *error_str
= NULL
;
1425 const unsigned *program
=
1426 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1427 NULL
, -1, NULL
, &error_str
);
1428 if (program
== NULL
) {
1429 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1430 ralloc_free(mem_ctx
);
1434 if (ish
->compiled_once
) {
1435 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1437 ish
->compiled_once
= true;
1440 uint32_t *so_decls
=
1441 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1442 &vue_prog_data
->vue_map
);
1444 struct iris_compiled_shader
*shader
=
1445 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1446 prog_data
, so_decls
, system_values
, num_system_values
,
1449 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1451 ralloc_free(mem_ctx
);
1456 * Update the current geometry shader variant.
1458 * Fill out the key, look in the cache, compile and bind if needed.
1461 iris_update_compiled_gs(struct iris_context
*ice
)
1463 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1464 struct iris_uncompiled_shader
*ish
=
1465 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1466 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1467 struct iris_compiled_shader
*shader
= NULL
;
1470 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1471 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1472 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1473 ice
->vtbl
.populate_gs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1476 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1479 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1482 shader
= iris_compile_gs(ice
, ish
, &key
);
1485 if (old
!= shader
) {
1486 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1487 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1488 IRIS_DIRTY_BINDINGS_GS
|
1489 IRIS_DIRTY_CONSTANTS_GS
;
1490 shs
->sysvals_need_upload
= true;
1495 * Compile a fragment (pixel) shader, and upload the assembly.
1497 static struct iris_compiled_shader
*
1498 iris_compile_fs(struct iris_context
*ice
,
1499 struct iris_uncompiled_shader
*ish
,
1500 const struct brw_wm_prog_key
*key
,
1501 struct brw_vue_map
*vue_map
)
1503 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1504 const struct brw_compiler
*compiler
= screen
->compiler
;
1505 void *mem_ctx
= ralloc_context(NULL
);
1506 struct brw_wm_prog_data
*fs_prog_data
=
1507 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1508 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1509 enum brw_param_builtin
*system_values
;
1510 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1511 unsigned num_system_values
;
1514 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1516 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1518 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1519 &num_system_values
, &num_cbufs
);
1521 /* Lower output variables to load_output intrinsics before setting up
1522 * binding tables, so iris_setup_binding_table can map any load_output
1523 * intrinsics to IRIS_SURFACE_GROUP_RENDER_TARGET_READ on Gen8 for
1524 * non-coherent framebuffer fetches.
1526 brw_nir_lower_fs_outputs(nir
);
1528 struct iris_binding_table bt
;
1529 iris_setup_binding_table(devinfo
, nir
, &bt
, MAX2(key
->nr_color_regions
, 1),
1530 num_system_values
, num_cbufs
);
1532 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1534 char *error_str
= NULL
;
1535 const unsigned *program
=
1536 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1537 nir
, NULL
, -1, -1, -1, true, false, vue_map
,
1539 if (program
== NULL
) {
1540 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1541 ralloc_free(mem_ctx
);
1545 if (ish
->compiled_once
) {
1546 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1548 ish
->compiled_once
= true;
1551 struct iris_compiled_shader
*shader
=
1552 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1553 prog_data
, NULL
, system_values
, num_system_values
,
1556 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1558 ralloc_free(mem_ctx
);
1563 * Update the current fragment shader variant.
1565 * Fill out the key, look in the cache, compile and bind if needed.
1568 iris_update_compiled_fs(struct iris_context
*ice
)
1570 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1571 struct iris_uncompiled_shader
*ish
=
1572 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1573 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1574 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1575 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1576 ice
->vtbl
.populate_fs_key(ice
, &ish
->nir
->info
, &key
);
1578 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1579 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1581 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1582 struct iris_compiled_shader
*shader
=
1583 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1586 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1589 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1591 if (old
!= shader
) {
1592 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1593 // toggles. might be able to avoid flagging SBE too.
1594 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1595 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1596 IRIS_DIRTY_BINDINGS_FS
|
1597 IRIS_DIRTY_CONSTANTS_FS
|
1601 shs
->sysvals_need_upload
= true;
1606 * Update the last enabled stage's VUE map.
1608 * When the shader feeding the rasterizer's output interface changes, we
1609 * need to re-emit various packets.
1612 update_last_vue_map(struct iris_context
*ice
,
1613 struct brw_stage_prog_data
*prog_data
)
1615 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1616 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1617 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1618 const uint64_t changed_slots
=
1619 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1621 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1622 ice
->state
.num_viewports
=
1623 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1624 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1625 IRIS_DIRTY_SF_CL_VIEWPORT
|
1626 IRIS_DIRTY_CC_VIEWPORT
|
1627 IRIS_DIRTY_SCISSOR_RECT
|
1628 IRIS_DIRTY_UNCOMPILED_FS
|
1629 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1632 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1633 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1636 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1640 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1642 static struct brw_vue_prog_data
*
1643 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1645 if (!ice
->shaders
.prog
[stage
])
1648 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1651 // XXX: iris_compiled_shaders are space-leaking :(
1652 // XXX: do remember to unbind them if deleting them.
1655 * Update the current shader variants for the given state.
1657 * This should be called on every draw call to ensure that the correct
1658 * shaders are bound. It will also flag any dirty state triggered by
1659 * swapping out those shaders.
1662 iris_update_compiled_shaders(struct iris_context
*ice
)
1664 const uint64_t dirty
= ice
->state
.dirty
;
1666 struct brw_vue_prog_data
*old_prog_datas
[4];
1667 if (!(dirty
& IRIS_DIRTY_URB
)) {
1668 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1669 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1672 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1673 struct iris_uncompiled_shader
*tes
=
1674 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1676 iris_update_compiled_tcs(ice
);
1677 iris_update_compiled_tes(ice
);
1679 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1680 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1682 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1683 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1684 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1688 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1689 iris_update_compiled_vs(ice
);
1690 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1691 iris_update_compiled_gs(ice
);
1693 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1694 const struct iris_compiled_shader
*gs
=
1695 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1696 const struct iris_compiled_shader
*tes
=
1697 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1699 bool points_or_lines
= false;
1702 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1704 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1705 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1707 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1709 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1710 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1713 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1714 /* Outbound to XY Clip enables */
1715 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1716 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1720 gl_shader_stage last_stage
= last_vue_stage(ice
);
1721 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1722 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1723 update_last_vue_map(ice
, shader
->prog_data
);
1724 if (ice
->state
.streamout
!= shader
->streamout
) {
1725 ice
->state
.streamout
= shader
->streamout
;
1726 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1729 if (ice
->state
.streamout_active
) {
1730 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1731 struct iris_stream_output_target
*so
=
1732 (void *) ice
->state
.so_target
[i
];
1734 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1738 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1739 iris_update_compiled_fs(ice
);
1741 /* Changing shader interfaces may require a URB configuration. */
1742 if (!(dirty
& IRIS_DIRTY_URB
)) {
1743 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1744 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1745 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1746 if (!!old
!= !!new ||
1747 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1748 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1755 static struct iris_compiled_shader
*
1756 iris_compile_cs(struct iris_context
*ice
,
1757 struct iris_uncompiled_shader
*ish
,
1758 const struct brw_cs_prog_key
*key
)
1760 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1761 const struct brw_compiler
*compiler
= screen
->compiler
;
1762 void *mem_ctx
= ralloc_context(NULL
);
1763 struct brw_cs_prog_data
*cs_prog_data
=
1764 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1765 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1766 enum brw_param_builtin
*system_values
;
1767 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1768 unsigned num_system_values
;
1771 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1773 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1774 &num_system_values
, &num_cbufs
);
1776 struct iris_binding_table bt
;
1777 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1778 num_system_values
, num_cbufs
);
1780 char *error_str
= NULL
;
1781 const unsigned *program
=
1782 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1783 nir
, -1, NULL
, &error_str
);
1784 if (program
== NULL
) {
1785 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1786 ralloc_free(mem_ctx
);
1790 if (ish
->compiled_once
) {
1791 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1793 ish
->compiled_once
= true;
1796 struct iris_compiled_shader
*shader
=
1797 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1798 prog_data
, NULL
, system_values
, num_system_values
,
1801 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1803 ralloc_free(mem_ctx
);
1808 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1810 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1811 struct iris_uncompiled_shader
*ish
=
1812 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1814 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1815 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1816 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1817 ice
->vtbl
.populate_cs_key(ice
, &key
);
1819 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1820 struct iris_compiled_shader
*shader
=
1821 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1824 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1827 shader
= iris_compile_cs(ice
, ish
, &key
);
1829 if (old
!= shader
) {
1830 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1831 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1832 IRIS_DIRTY_BINDINGS_CS
|
1833 IRIS_DIRTY_CONSTANTS_CS
;
1834 shs
->sysvals_need_upload
= true;
1839 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1842 assert(cs_prog_data
->push
.total
.size
> 0);
1843 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1844 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1845 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1846 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1851 * Allocate scratch BOs as needed for the given per-thread size and stage.
1854 iris_get_scratch_space(struct iris_context
*ice
,
1855 unsigned per_thread_scratch
,
1856 gl_shader_stage stage
)
1858 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1859 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1860 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1862 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1863 assert(encoded_size
< (1 << 16));
1865 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1867 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1869 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1870 * must allocate scratch space enough so that each slice has 4
1873 * According to the other driver team, this applies to compute shaders
1874 * as well. This is not currently documented at all.
1876 * This hack is no longer necessary on Gen11+.
1878 unsigned subslice_total
= screen
->subslice_total
;
1879 if (devinfo
->gen
< 11)
1880 subslice_total
= 4 * devinfo
->num_slices
;
1881 assert(subslice_total
>= screen
->subslice_total
);
1884 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1885 uint32_t max_threads
[] = {
1886 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1887 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1888 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1889 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1890 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1891 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1894 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1896 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1902 /* ------------------------------------------------------------------- */
1905 * The pipe->create_[stage]_state() driver hooks.
1907 * Performs basic NIR preprocessing, records any state dependencies, and
1908 * returns an iris_uncompiled_shader as the Gallium CSO.
1910 * Actual shader compilation to assembly happens later, at first use.
1913 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1915 const struct pipe_stream_output_info
*so_info
)
1917 struct iris_context
*ice
= (void *)ctx
;
1918 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1919 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1921 struct iris_uncompiled_shader
*ish
=
1922 calloc(1, sizeof(struct iris_uncompiled_shader
));
1926 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1928 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1929 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1933 if (nir
->constant_data_size
> 0) {
1934 unsigned data_offset
;
1935 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1936 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1938 struct pipe_shader_buffer psb
= {
1939 .buffer
= ish
->const_data
,
1940 .buffer_offset
= data_offset
,
1941 .buffer_size
= nir
->constant_data_size
,
1943 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1946 ish
->program_id
= get_new_program_id(screen
);
1949 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1950 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1953 /* Save this now before potentially dropping nir->info.name */
1954 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1955 ish
->use_alt_mode
= true;
1957 if (screen
->disk_cache
) {
1958 /* Serialize the NIR to a binary blob that we can hash for the disk
1959 * cache. First, drop unnecessary information (like variable names)
1960 * so the serialized NIR is smaller, and also to let us detect more
1961 * isomorphic shaders when hashing, increasing cache hits. We clone
1962 * the NIR before stripping away this info because it can be useful
1963 * when inspecting and debugging shaders.
1965 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1970 nir_serialize(&blob
, clone
);
1971 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1980 static struct iris_uncompiled_shader
*
1981 iris_create_shader_state(struct pipe_context
*ctx
,
1982 const struct pipe_shader_state
*state
)
1984 struct nir_shader
*nir
;
1986 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1987 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1989 nir
= state
->ir
.nir
;
1991 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1995 iris_create_vs_state(struct pipe_context
*ctx
,
1996 const struct pipe_shader_state
*state
)
1998 struct iris_context
*ice
= (void *) ctx
;
1999 struct iris_screen
*screen
= (void *) ctx
->screen
;
2000 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2002 /* User clip planes */
2003 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2004 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2006 if (screen
->precompile
) {
2007 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2008 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2010 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2011 iris_compile_vs(ice
, ish
, &key
);
2018 iris_create_tcs_state(struct pipe_context
*ctx
,
2019 const struct pipe_shader_state
*state
)
2021 struct iris_context
*ice
= (void *) ctx
;
2022 struct iris_screen
*screen
= (void *) ctx
->screen
;
2023 const struct brw_compiler
*compiler
= screen
->compiler
;
2024 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2025 struct shader_info
*info
= &ish
->nir
->info
;
2027 if (screen
->precompile
) {
2028 const unsigned _GL_TRIANGLES
= 0x0004;
2029 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2030 struct brw_tcs_prog_key key
= {
2031 KEY_INIT(devinfo
->gen
),
2032 // XXX: make sure the linker fills this out from the TES...
2033 .tes_primitive_mode
=
2034 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
2036 .outputs_written
= info
->outputs_written
,
2037 .patch_outputs_written
= info
->patch_outputs_written
,
2040 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
2041 * We don't have that information, so we randomly guess that the input
2042 * and output patches are the same size. This is a bad guess, but we
2043 * can't do much better.
2045 if (compiler
->use_tcs_8_patch
)
2046 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2048 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2049 iris_compile_tcs(ice
, ish
, &key
);
2056 iris_create_tes_state(struct pipe_context
*ctx
,
2057 const struct pipe_shader_state
*state
)
2059 struct iris_context
*ice
= (void *) ctx
;
2060 struct iris_screen
*screen
= (void *) ctx
->screen
;
2061 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2062 struct shader_info
*info
= &ish
->nir
->info
;
2064 /* User clip planes */
2065 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2066 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2068 if (screen
->precompile
) {
2069 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2070 struct brw_tes_prog_key key
= {
2071 KEY_INIT(devinfo
->gen
),
2072 // XXX: not ideal, need TCS output/TES input unification
2073 .inputs_read
= info
->inputs_read
,
2074 .patch_inputs_read
= info
->patch_inputs_read
,
2077 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2078 iris_compile_tes(ice
, ish
, &key
);
2085 iris_create_gs_state(struct pipe_context
*ctx
,
2086 const struct pipe_shader_state
*state
)
2088 struct iris_context
*ice
= (void *) ctx
;
2089 struct iris_screen
*screen
= (void *) ctx
->screen
;
2090 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2092 /* User clip planes */
2093 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2094 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2096 if (screen
->precompile
) {
2097 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2098 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2100 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2101 iris_compile_gs(ice
, ish
, &key
);
2108 iris_create_fs_state(struct pipe_context
*ctx
,
2109 const struct pipe_shader_state
*state
)
2111 struct iris_context
*ice
= (void *) ctx
;
2112 struct iris_screen
*screen
= (void *) ctx
->screen
;
2113 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2114 struct shader_info
*info
= &ish
->nir
->info
;
2116 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2117 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2118 (1ull << IRIS_NOS_RASTERIZER
) |
2119 (1ull << IRIS_NOS_BLEND
);
2121 /* The program key needs the VUE map if there are > 16 inputs */
2122 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2123 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2124 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2127 if (screen
->precompile
) {
2128 const uint64_t color_outputs
= info
->outputs_written
&
2129 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2130 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2131 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2133 bool can_rearrange_varyings
=
2134 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2136 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2137 struct brw_wm_prog_key key
= {
2138 KEY_INIT(devinfo
->gen
),
2139 .nr_color_regions
= util_bitcount(color_outputs
),
2140 .coherent_fb_fetch
= devinfo
->gen
>= 9,
2141 .input_slots_valid
=
2142 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2145 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2146 iris_compile_fs(ice
, ish
, &key
, NULL
);
2153 iris_create_compute_state(struct pipe_context
*ctx
,
2154 const struct pipe_compute_state
*state
)
2156 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2158 struct iris_context
*ice
= (void *) ctx
;
2159 struct iris_screen
*screen
= (void *) ctx
->screen
;
2160 struct iris_uncompiled_shader
*ish
=
2161 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2163 // XXX: disallow more than 64KB of shared variables
2165 if (screen
->precompile
) {
2166 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2167 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2169 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2170 iris_compile_cs(ice
, ish
, &key
);
2177 * The pipe->delete_[stage]_state() driver hooks.
2179 * Frees the iris_uncompiled_shader.
2182 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2184 struct iris_uncompiled_shader
*ish
= state
;
2185 struct iris_context
*ice
= (void *) ctx
;
2187 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2188 ice
->shaders
.uncompiled
[stage
] = NULL
;
2189 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2192 if (ish
->const_data
) {
2193 pipe_resource_reference(&ish
->const_data
, NULL
);
2194 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2197 ralloc_free(ish
->nir
);
2202 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2204 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2208 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2210 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2214 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2216 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2220 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2222 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2226 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2228 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2232 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2234 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2238 * The pipe->bind_[stage]_state() driver hook.
2240 * Binds an uncompiled shader as the current one for a particular stage.
2241 * Updates dirty tracking to account for the shader's NOS.
2244 bind_shader_state(struct iris_context
*ice
,
2245 struct iris_uncompiled_shader
*ish
,
2246 gl_shader_stage stage
)
2248 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2249 const uint64_t nos
= ish
? ish
->nos
: 0;
2251 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2252 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2254 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2255 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2256 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2259 ice
->shaders
.uncompiled
[stage
] = ish
;
2260 ice
->state
.dirty
|= dirty_bit
;
2262 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2263 * (or that they no longer need to do so).
2265 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2267 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2269 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2274 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2276 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2277 struct iris_uncompiled_shader
*new_ish
= state
;
2280 ice
->state
.window_space_position
!=
2281 new_ish
->nir
->info
.vs
.window_space_position
) {
2282 ice
->state
.window_space_position
=
2283 new_ish
->nir
->info
.vs
.window_space_position
;
2285 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
2287 IRIS_DIRTY_CC_VIEWPORT
;
2290 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2294 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2296 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2300 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2302 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2304 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2305 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2306 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2308 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2312 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2314 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2316 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2317 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2318 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2320 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2324 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2326 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2327 struct iris_uncompiled_shader
*old_ish
=
2328 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2329 struct iris_uncompiled_shader
*new_ish
= state
;
2331 const unsigned color_bits
=
2332 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2333 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2335 /* Fragment shader outputs influence HasWriteableRT */
2336 if (!old_ish
|| !new_ish
||
2337 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2338 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2339 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2341 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2345 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2347 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2351 iris_init_program_functions(struct pipe_context
*ctx
)
2353 ctx
->create_vs_state
= iris_create_vs_state
;
2354 ctx
->create_tcs_state
= iris_create_tcs_state
;
2355 ctx
->create_tes_state
= iris_create_tes_state
;
2356 ctx
->create_gs_state
= iris_create_gs_state
;
2357 ctx
->create_fs_state
= iris_create_fs_state
;
2358 ctx
->create_compute_state
= iris_create_compute_state
;
2360 ctx
->delete_vs_state
= iris_delete_vs_state
;
2361 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2362 ctx
->delete_tes_state
= iris_delete_tes_state
;
2363 ctx
->delete_gs_state
= iris_delete_gs_state
;
2364 ctx
->delete_fs_state
= iris_delete_fs_state
;
2365 ctx
->delete_compute_state
= iris_delete_cs_state
;
2367 ctx
->bind_vs_state
= iris_bind_vs_state
;
2368 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2369 ctx
->bind_tes_state
= iris_bind_tes_state
;
2370 ctx
->bind_gs_state
= iris_bind_gs_state
;
2371 ctx
->bind_fs_state
= iris_bind_fs_state
;
2372 ctx
->bind_compute_state
= iris_bind_cs_state
;