2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS
,
65 static const uint64_t priority_to_modifier
[] = {
66 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
67 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
68 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
69 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
70 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS
] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
75 modifier_is_supported(const struct gen_device_info
*devinfo
,
76 enum pipe_format pfmt
, uint64_t modifier
)
78 /* Check for basic device support. */
80 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_X_TILED
:
82 case I915_FORMAT_MOD_Y_TILED
:
84 case I915_FORMAT_MOD_Y_TILED_CCS
:
85 if (devinfo
->gen
<= 8 || devinfo
->gen
>= 12)
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
89 if (devinfo
->gen
!= 12)
92 case DRM_FORMAT_MOD_INVALID
:
97 /* Check remaining requirements. */
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
100 case I915_FORMAT_MOD_Y_TILED_CCS
: {
101 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
104 enum isl_format rt_format
=
105 iris_format_for_usage(devinfo
, pfmt
,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
108 if (rt_format
== ISL_FORMAT_UNSUPPORTED
||
109 !isl_format_supports_ccs_e(devinfo
, rt_format
))
121 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
122 const uint64_t *modifiers
,
125 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
127 for (int i
= 0; i
< count
; i
++) {
128 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
131 switch (modifiers
[i
]) {
132 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
133 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_GEN12_RC_CCS
);
135 case I915_FORMAT_MOD_Y_TILED_CCS
:
136 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
138 case I915_FORMAT_MOD_Y_TILED
:
139 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
141 case I915_FORMAT_MOD_X_TILED
:
142 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
144 case DRM_FORMAT_MOD_LINEAR
:
145 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
147 case DRM_FORMAT_MOD_INVALID
:
153 return priority_to_modifier
[prio
];
157 target_to_isl_surf_dim(enum pipe_texture_target target
)
161 case PIPE_TEXTURE_1D
:
162 case PIPE_TEXTURE_1D_ARRAY
:
163 return ISL_SURF_DIM_1D
;
164 case PIPE_TEXTURE_2D
:
165 case PIPE_TEXTURE_CUBE
:
166 case PIPE_TEXTURE_RECT
:
167 case PIPE_TEXTURE_2D_ARRAY
:
168 case PIPE_TEXTURE_CUBE_ARRAY
:
169 return ISL_SURF_DIM_2D
;
170 case PIPE_TEXTURE_3D
:
171 return ISL_SURF_DIM_3D
;
172 case PIPE_MAX_TEXTURE_TYPES
:
175 unreachable("invalid texture type");
179 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
180 enum pipe_format pfmt
,
183 unsigned int *external_only
,
186 struct iris_screen
*screen
= (void *) pscreen
;
187 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
189 uint64_t all_modifiers
[] = {
190 DRM_FORMAT_MOD_LINEAR
,
191 I915_FORMAT_MOD_X_TILED
,
192 I915_FORMAT_MOD_Y_TILED
,
193 I915_FORMAT_MOD_Y_TILED_CCS
,
194 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
197 int supported_mods
= 0;
199 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
200 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
203 if (supported_mods
< max
) {
205 modifiers
[supported_mods
] = all_modifiers
[i
];
208 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
214 *count
= supported_mods
;
217 static isl_surf_usage_flags_t
218 pipe_bind_to_isl_usage(unsigned bindings
)
220 isl_surf_usage_flags_t usage
= 0;
222 if (bindings
& PIPE_BIND_RENDER_TARGET
)
223 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
225 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
226 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
228 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
229 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
231 if (bindings
& PIPE_BIND_SCANOUT
)
232 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
238 iris_image_view_get_format(struct iris_context
*ice
,
239 const struct pipe_image_view
*img
)
241 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
242 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
244 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
245 enum isl_format isl_fmt
=
246 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
248 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
249 /* On Gen8, try to use typed surfaces reads (which support a
250 * limited number of formats), and if not possible, fall back
253 if (devinfo
->gen
== 8 &&
254 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
255 return ISL_FORMAT_RAW
;
257 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
263 struct pipe_resource
*
264 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
266 /* For packed depth-stencil, we treat depth as the primary resource
267 * and store S8 as the "second plane" resource.
269 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
277 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
278 struct pipe_resource
*stencil
)
280 assert(util_format_has_depth(util_format_description(p_res
->format
)));
281 pipe_resource_reference(&p_res
->next
, stencil
);
285 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
286 struct iris_resource
**out_z
,
287 struct iris_resource
**out_s
)
295 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
296 *out_z
= (void *) res
;
297 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
300 *out_s
= (void *) res
;
305 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
306 enum isl_tiling tiling
,
307 enum pipe_texture_target target
)
310 case PIPE_TEXTURE_1D
:
311 case PIPE_TEXTURE_1D_ARRAY
:
312 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
313 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
315 case PIPE_TEXTURE_2D
:
316 case PIPE_TEXTURE_2D_ARRAY
:
317 case PIPE_TEXTURE_RECT
:
318 case PIPE_TEXTURE_CUBE
:
319 case PIPE_TEXTURE_CUBE_ARRAY
:
320 return ISL_DIM_LAYOUT_GEN4_2D
;
322 case PIPE_TEXTURE_3D
:
323 return (devinfo
->gen
>= 9 ?
324 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
326 case PIPE_MAX_TEXTURE_TYPES
:
330 unreachable("invalid texture type");
334 iris_resource_disable_aux(struct iris_resource
*res
)
336 iris_bo_unreference(res
->aux
.bo
);
337 iris_bo_unreference(res
->aux
.clear_color_bo
);
338 free(res
->aux
.state
);
340 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
341 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
342 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
343 res
->aux
.has_hiz
= 0;
344 res
->aux
.surf
.size_B
= 0;
346 res
->aux
.extra_aux
.surf
.size_B
= 0;
347 res
->aux
.clear_color_bo
= NULL
;
348 res
->aux
.state
= NULL
;
352 iris_resource_destroy(struct pipe_screen
*screen
,
353 struct pipe_resource
*resource
)
355 struct iris_resource
*res
= (struct iris_resource
*)resource
;
357 if (resource
->target
== PIPE_BUFFER
)
358 util_range_destroy(&res
->valid_buffer_range
);
360 iris_resource_disable_aux(res
);
362 iris_bo_unreference(res
->bo
);
363 iris_pscreen_unref(res
->base
.screen
);
368 static struct iris_resource
*
369 iris_alloc_resource(struct pipe_screen
*pscreen
,
370 const struct pipe_resource
*templ
)
372 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
377 res
->base
.screen
= iris_pscreen_ref(pscreen
);
378 pipe_reference_init(&res
->base
.reference
, 1);
380 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
381 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
383 if (templ
->target
== PIPE_BUFFER
)
384 util_range_init(&res
->valid_buffer_range
);
390 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
392 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
393 return minify(res
->surf
.logical_level0_px
.depth
, level
);
395 return res
->surf
.logical_level0_px
.array_len
;
398 static enum isl_aux_state
**
399 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
401 assert(res
->aux
.state
== NULL
);
403 uint32_t total_slices
= 0;
404 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
405 total_slices
+= iris_get_num_logical_layers(res
, level
);
407 const size_t per_level_array_size
=
408 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
410 /* We're going to allocate a single chunk of data for both the per-level
411 * reference array and the arrays of aux_state. This makes cleanup
412 * significantly easier.
414 const size_t total_size
=
415 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
417 void *data
= malloc(total_size
);
421 enum isl_aux_state
**per_level_arr
= data
;
422 enum isl_aux_state
*s
= data
+ per_level_array_size
;
423 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
424 per_level_arr
[level
] = s
;
425 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
426 for (uint32_t a
= 0; a
< level_layers
; a
++)
429 assert((void *)s
== data
+ total_size
);
431 return per_level_arr
;
435 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
437 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
438 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
442 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
444 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
445 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
446 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
448 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
449 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
450 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
451 res
->aux
.bo
->gtt_offset
+ aux_offset
);
452 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
457 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
458 enum isl_format format
)
460 if (!isl_format_supports_ccs_e(devinfo
, format
))
463 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
465 /* CCS_E seems to significantly hurt performance with 32-bit floating
466 * point formats. For example, Paraview's "Wavelet Volume" case uses
467 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
468 * formats causes a 62% FPS drop.
470 * However, many benchmarks seem to use 16-bit float with no issues.
472 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
479 * Configure aux for the resource, but don't allocate it. For images which
480 * might be shared with modifiers, we must allocate the image and aux data in
483 * Returns false on unexpected error (e.g. allocation failed, or invalid
484 * configuration result).
487 iris_resource_configure_aux(struct iris_screen
*screen
,
488 struct iris_resource
*res
, bool imported
,
489 uint64_t *aux_size_B
)
491 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
493 /* Try to create the auxiliary surfaces allowed by the modifier or by
494 * the user if no modifier is specified.
496 assert(!res
->mod_info
||
497 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
498 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
499 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
);
501 const bool has_mcs
= !res
->mod_info
&&
502 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
504 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
505 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
508 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
509 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
510 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
511 &res
->aux
.extra_aux
.surf
, 0);
513 /* Having both HIZ and MCS is impossible. */
514 assert(!has_mcs
|| !has_hiz
);
516 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
517 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
518 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
519 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
520 assert(res
->aux
.surf
.size_B
> 0 &&
521 res
->aux
.surf
.usage
&
522 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
525 if (res
->mod_info
&& has_ccs
) {
526 /* Only allow a CCS modifier if the aux was created successfully. */
527 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
528 } else if (has_mcs
) {
529 res
->aux
.possible_usages
|=
530 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
531 } else if (has_hiz
) {
533 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
534 } else if (res
->surf
.samples
== 1 &&
535 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
536 /* If this resource is single-sampled and will be used as a texture,
537 * put the HiZ surface in write-through mode so that we can sample
540 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
542 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
544 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
545 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
546 } else if (has_ccs
) {
547 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
)) {
548 res
->aux
.possible_usages
|= devinfo
->gen
< 12 ?
549 1 << ISL_AUX_USAGE_CCS_E
: 1 << ISL_AUX_USAGE_GEN12_CCS_E
;
550 } else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
)) {
551 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
555 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
557 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
559 /* We don't always support sampling with hiz. But when we do, it must be
562 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
563 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
565 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
566 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
568 enum isl_aux_state initial_state
;
570 assert(!res
->aux
.bo
);
572 switch (res
->aux
.usage
) {
573 case ISL_AUX_USAGE_NONE
:
574 /* Having no aux buffer is only okay if there's no modifier with aux. */
575 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
576 case ISL_AUX_USAGE_HIZ
:
577 case ISL_AUX_USAGE_HIZ_CCS
:
578 case ISL_AUX_USAGE_HIZ_CCS_WT
:
579 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
581 case ISL_AUX_USAGE_MCS
:
582 case ISL_AUX_USAGE_MCS_CCS
:
583 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
585 * "When MCS buffer is enabled and bound to MSRT, it is required
586 * that it is cleared prior to any rendering."
588 * Since we only use the MCS buffer for rendering, we just clear it
589 * immediately on allocation. The clear value for MCS buffers is all
590 * 1's, so we simply memset it to 0xff.
592 initial_state
= ISL_AUX_STATE_CLEAR
;
594 case ISL_AUX_USAGE_CCS_D
:
595 case ISL_AUX_USAGE_CCS_E
:
596 case ISL_AUX_USAGE_GEN12_CCS_E
:
597 case ISL_AUX_USAGE_STC_CCS
:
598 /* When CCS_E is used, we need to ensure that the CCS starts off in
599 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
602 * "If Software wants to enable Color Compression without Fast
603 * clear, Software needs to initialize MCS with zeros."
605 * A CCS value of 0 indicates that the corresponding block is in the
606 * pass-through state which is what we want.
608 * For CCS_D, do the same thing. On Gen9+, this avoids having any
609 * undefined bits in the aux buffer.
612 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
614 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
616 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
619 case ISL_AUX_USAGE_MC
:
621 unreachable("Unsupported aux mode");
624 /* Create the aux_state for the auxiliary buffer. */
625 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
629 /* Allocate space in the buffer for storing the aux surface. */
631 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
632 uint64_t size
= res
->aux
.surf
.size_B
;
634 /* Allocate space in the buffer for storing the CCS. */
635 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
636 const uint64_t padded_aux_size
=
637 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
638 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
639 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
642 /* Allocate space in the buffer for storing the clear color. On modern
643 * platforms (gen > 9), we can read it directly from such buffer.
645 * On gen <= 9, we are going to store the clear color on the buffer
646 * anyways, and copy it back to the surface state during state emission.
648 * Also add some padding to make sure the fast clear color state buffer
649 * starts at a 4K alignment. We believe that 256B might be enough, but due
650 * to lack of testing we will leave this as 4K for now.
652 size
= ALIGN(size
, 4096);
653 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
654 size
+= iris_get_aux_clear_color_state_size(screen
);
657 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
658 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
659 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
660 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
662 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
663 * For LOD == 0, we can grow the dimensions to make it work.
665 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
666 res
->aux
.has_hiz
|= 1 << level
;
674 * Initialize the aux buffer contents.
676 * Returns false on unexpected error (e.g. mapping a BO failed).
679 iris_resource_init_aux_buf(struct iris_resource
*res
,
680 unsigned clear_color_state_size
)
682 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
687 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
688 /* See iris_resource_configure_aux for the memset_value rationale. */
689 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
690 memset((char*)map
+ res
->aux
.offset
, memset_value
,
691 res
->aux
.surf
.size_B
);
694 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
695 0, res
->aux
.extra_aux
.surf
.size_B
);
697 /* Zero the indirect clear color to match ::fast_clear_color. */
698 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
699 clear_color_state_size
);
701 iris_bo_unmap(res
->aux
.bo
);
703 if (clear_color_state_size
> 0) {
704 res
->aux
.clear_color_bo
= res
->aux
.bo
;
705 iris_bo_reference(res
->aux
.clear_color_bo
);
712 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
713 struct iris_resource
*res
)
715 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
716 assert(iris_resource_unfinished_aux_import(res
));
717 assert(!res
->mod_info
->supports_clear_color
);
719 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
720 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
723 assert(res
->bo
== aux_res
->aux
.bo
);
724 iris_bo_reference(aux_res
->aux
.bo
);
725 res
->aux
.bo
= aux_res
->aux
.bo
;
727 res
->aux
.offset
= aux_res
->aux
.offset
;
729 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
730 assert(res
->aux
.clear_color_bo
== NULL
);
731 res
->aux
.clear_color_offset
= 0;
733 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
735 unsigned clear_color_state_size
=
736 iris_get_aux_clear_color_state_size(screen
);
738 if (clear_color_state_size
> 0) {
739 res
->aux
.clear_color_bo
=
740 iris_bo_alloc_tiled(screen
->bufmgr
, "clear color_buffer",
741 clear_color_state_size
, 1, IRIS_MEMZONE_OTHER
,
742 I915_TILING_NONE
, 0, BO_ALLOC_ZEROED
);
743 res
->aux
.clear_color_offset
= 0;
746 iris_resource_destroy(&screen
->base
, res
->base
.next
);
747 res
->base
.next
= NULL
;
749 map_aux_addresses(screen
, res
);
752 static struct pipe_resource
*
753 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
754 const struct pipe_resource
*templ
)
756 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
757 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
759 assert(templ
->target
== PIPE_BUFFER
);
760 assert(templ
->height0
<= 1);
761 assert(templ
->depth0
<= 1);
762 assert(templ
->format
== PIPE_FORMAT_NONE
||
763 util_format_get_blocksize(templ
->format
) == 1);
765 res
->internal_format
= templ
->format
;
766 res
->surf
.tiling
= ISL_TILING_LINEAR
;
768 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
769 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
770 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
771 memzone
= IRIS_MEMZONE_SHADER
;
772 name
= "shader kernels";
773 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
774 memzone
= IRIS_MEMZONE_SURFACE
;
775 name
= "surface state";
776 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
777 memzone
= IRIS_MEMZONE_DYNAMIC
;
778 name
= "dynamic state";
781 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
783 iris_resource_destroy(pscreen
, &res
->base
);
787 if (templ
->bind
& PIPE_BIND_SHARED
)
788 iris_bo_make_external(res
->bo
);
793 static struct pipe_resource
*
794 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
795 const struct pipe_resource
*templ
,
796 const uint64_t *modifiers
,
799 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
800 struct gen_device_info
*devinfo
= &screen
->devinfo
;
801 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
806 const struct util_format_description
*format_desc
=
807 util_format_description(templ
->format
);
808 const bool has_depth
= util_format_has_depth(format_desc
);
810 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
812 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
814 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
815 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
817 tiling_flags
= 1 << res
->mod_info
->tiling
;
819 if (modifiers_count
> 0) {
820 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
824 /* Use linear for staging buffers */
825 if (templ
->usage
== PIPE_USAGE_STAGING
||
826 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) ) {
827 tiling_flags
= ISL_TILING_LINEAR_BIT
;
828 } else if (templ
->bind
& PIPE_BIND_SCANOUT
) {
829 if (devinfo
->has_tiling_uapi
)
830 tiling_flags
= ISL_TILING_X_BIT
;
832 tiling_flags
= ISL_TILING_LINEAR_BIT
;
836 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
838 if (templ
->target
== PIPE_TEXTURE_CUBE
||
839 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
840 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
842 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
843 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
844 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
846 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
849 enum pipe_format pfmt
= templ
->format
;
850 res
->internal_format
= pfmt
;
852 /* Should be handled by u_transfer_helper */
853 assert(!util_format_is_depth_and_stencil(pfmt
));
855 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
856 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
858 UNUSED
const bool isl_surf_created_successfully
=
859 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
860 .dim
= target_to_isl_surf_dim(templ
->target
),
862 .width
= templ
->width0
,
863 .height
= templ
->height0
,
864 .depth
= templ
->depth0
,
865 .levels
= templ
->last_level
+ 1,
866 .array_len
= templ
->array_size
,
867 .samples
= MAX2(templ
->nr_samples
, 1),
868 .min_alignment_B
= 0,
871 .tiling_flags
= tiling_flags
);
872 assert(isl_surf_created_successfully
);
874 const char *name
= "miptree";
875 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
877 unsigned int flags
= 0;
878 if (templ
->usage
== PIPE_USAGE_STAGING
)
879 flags
|= BO_ALLOC_COHERENT
;
881 /* These are for u_upload_mgr buffers only */
882 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
883 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
884 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
886 uint64_t aux_size
= 0;
887 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
))
890 /* Modifiers require the aux data to be in the same buffer as the main
891 * surface, but we combine them even when a modifiers is not being used.
893 const uint64_t bo_size
=
894 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
895 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
896 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
898 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
899 res
->surf
.row_pitch_B
, flags
);
905 res
->aux
.bo
= res
->bo
;
906 iris_bo_reference(res
->aux
.bo
);
907 unsigned clear_color_state_size
=
908 iris_get_aux_clear_color_state_size(screen
);
909 if (!iris_resource_init_aux_buf(res
, clear_color_state_size
))
911 map_aux_addresses(screen
, res
);
914 if (templ
->bind
& PIPE_BIND_SHARED
)
915 iris_bo_make_external(res
->bo
);
920 fprintf(stderr
, "XXX: resource creation failed\n");
921 iris_resource_destroy(pscreen
, &res
->base
);
926 static struct pipe_resource
*
927 iris_resource_create(struct pipe_screen
*pscreen
,
928 const struct pipe_resource
*templ
)
930 if (templ
->target
== PIPE_BUFFER
)
931 return iris_resource_create_for_buffer(pscreen
, templ
);
933 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
937 tiling_to_modifier(uint32_t tiling
)
939 static const uint64_t map
[] = {
940 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
941 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
942 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
945 assert(tiling
< ARRAY_SIZE(map
));
950 static struct pipe_resource
*
951 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
952 const struct pipe_resource
*templ
,
955 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
956 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
957 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
961 assert(templ
->target
== PIPE_BUFFER
);
963 res
->internal_format
= templ
->format
;
964 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
965 user_memory
, templ
->width0
,
968 iris_resource_destroy(pscreen
, &res
->base
);
972 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
977 static struct pipe_resource
*
978 iris_resource_from_handle(struct pipe_screen
*pscreen
,
979 const struct pipe_resource
*templ
,
980 struct winsys_handle
*whandle
,
983 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
984 struct gen_device_info
*devinfo
= &screen
->devinfo
;
985 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
986 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
987 const struct isl_drm_modifier_info
*mod_inf
=
988 isl_drm_modifier_get_info(whandle
->modifier
);
993 switch (whandle
->type
) {
994 case WINSYS_HANDLE_TYPE_FD
:
995 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
998 case WINSYS_HANDLE_TYPE_SHARED
:
999 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1003 unreachable("invalid winsys handle type");
1008 res
->offset
= whandle
->offset
;
1010 if (mod_inf
== NULL
) {
1012 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1016 res
->external_format
= whandle
->format
;
1017 res
->mod_info
= mod_inf
;
1019 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1021 const struct iris_format_info fmt
=
1022 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1023 res
->internal_format
= templ
->format
;
1025 if (templ
->target
== PIPE_BUFFER
) {
1026 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1028 /* Create a surface for each plane specified by the external format. */
1029 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1030 UNUSED
const bool isl_surf_created_successfully
=
1031 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1032 .dim
= target_to_isl_surf_dim(templ
->target
),
1034 .width
= templ
->width0
,
1035 .height
= templ
->height0
,
1036 .depth
= templ
->depth0
,
1037 .levels
= templ
->last_level
+ 1,
1038 .array_len
= templ
->array_size
,
1039 .samples
= MAX2(templ
->nr_samples
, 1),
1040 .min_alignment_B
= 0,
1041 .row_pitch_B
= whandle
->stride
,
1043 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1044 assert(isl_surf_created_successfully
);
1045 assert(res
->bo
->tiling_mode
==
1046 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1049 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
);
1051 /* The gallium dri layer will create a separate plane resource
1052 * for the aux image. iris_resource_finish_aux_import will
1053 * merge the separate aux parameters back into a single
1057 /* Save modifier import information to reconstruct later. After
1058 * import, this will be available under a second image accessible
1059 * from the main image with res->base.next. See
1060 * iris_resource_finish_aux_import.
1062 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1063 res
->aux
.offset
= whandle
->offset
;
1064 res
->aux
.bo
= res
->bo
;
1072 iris_resource_destroy(pscreen
, &res
->base
);
1077 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1079 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1080 struct iris_resource
*res
= (void *) resource
;
1081 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1083 iris_resource_prepare_access(ice
, res
,
1084 0, INTEL_REMAINING_LEVELS
,
1085 0, INTEL_REMAINING_LAYERS
,
1086 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1087 mod
? mod
->supports_clear_color
: false);
1091 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1094 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1096 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1098 /* Disable aux usage if explicit flush not set and this is the first time
1099 * we are dealing with this resource and the resource was not created with
1100 * a modifier with aux.
1102 if (!mod_with_aux
&&
1103 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1104 p_atomic_read(&resource
->reference
.count
) == 1) {
1105 iris_resource_disable_aux(res
);
1110 iris_resource_get_param(struct pipe_screen
*pscreen
,
1111 struct pipe_context
*context
,
1112 struct pipe_resource
*resource
,
1115 enum pipe_resource_param param
,
1116 unsigned handle_usage
,
1119 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1120 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1122 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1123 bool wants_aux
= mod_with_aux
&& plane
> 0;
1127 if (iris_resource_unfinished_aux_import(res
))
1128 iris_resource_finish_aux_import(pscreen
, res
);
1130 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1132 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1135 case PIPE_RESOURCE_PARAM_NPLANES
:
1140 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1145 case PIPE_RESOURCE_PARAM_STRIDE
:
1146 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1148 case PIPE_RESOURCE_PARAM_OFFSET
:
1149 *value
= wants_aux
? res
->aux
.offset
: 0;
1151 case PIPE_RESOURCE_PARAM_MODIFIER
:
1152 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1153 tiling_to_modifier(res
->bo
->tiling_mode
);
1155 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1156 result
= iris_bo_flink(bo
, &handle
) == 0;
1160 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1161 /* Because we share the same drm file across multiple iris_screen, when
1162 * we export a GEM handle we must make sure it is valid in the DRM file
1163 * descriptor the caller is using (this is the FD given at screen
1167 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1173 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1174 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1184 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1185 struct pipe_context
*ctx
,
1186 struct pipe_resource
*resource
,
1187 struct winsys_handle
*whandle
,
1190 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1191 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1193 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1195 iris_resource_disable_aux_on_first_query(resource
, usage
);
1198 if (mod_with_aux
&& whandle
->plane
> 0) {
1199 assert(res
->aux
.bo
);
1201 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1202 whandle
->offset
= res
->aux
.offset
;
1204 /* If this is a buffer, stride should be 0 - no need to special case */
1205 whandle
->stride
= res
->surf
.row_pitch_B
;
1209 whandle
->format
= res
->external_format
;
1211 res
->mod_info
? res
->mod_info
->modifier
1212 : tiling_to_modifier(res
->bo
->tiling_mode
);
1215 enum isl_aux_usage allowed_usage
=
1216 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1218 if (res
->aux
.usage
!= allowed_usage
) {
1219 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1220 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1221 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1225 switch (whandle
->type
) {
1226 case WINSYS_HANDLE_TYPE_SHARED
:
1227 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1228 case WINSYS_HANDLE_TYPE_KMS
: {
1229 /* Because we share the same drm file across multiple iris_screen, when
1230 * we export a GEM handle we must make sure it is valid in the DRM file
1231 * descriptor the caller is using (this is the FD given at screen
1235 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1237 whandle
->handle
= handle
;
1240 case WINSYS_HANDLE_TYPE_FD
:
1241 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1248 resource_is_busy(struct iris_context
*ice
,
1249 struct iris_resource
*res
)
1251 bool busy
= iris_bo_busy(res
->bo
);
1253 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1254 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1260 iris_invalidate_resource(struct pipe_context
*ctx
,
1261 struct pipe_resource
*resource
)
1263 struct iris_screen
*screen
= (void *) ctx
->screen
;
1264 struct iris_context
*ice
= (void *) ctx
;
1265 struct iris_resource
*res
= (void *) resource
;
1267 if (resource
->target
!= PIPE_BUFFER
)
1270 /* If it's already invalidated, don't bother doing anything. */
1271 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1274 if (!resource_is_busy(ice
, res
)) {
1275 /* The resource is idle, so just mark that it contains no data and
1276 * keep using the same underlying buffer object.
1278 util_range_set_empty(&res
->valid_buffer_range
);
1282 /* Otherwise, try and replace the backing storage with a new BO. */
1284 /* We can't reallocate memory we didn't allocate in the first place. */
1285 if (res
->bo
->userptr
)
1288 // XXX: We should support this.
1289 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1292 struct iris_bo
*old_bo
= res
->bo
;
1293 struct iris_bo
*new_bo
=
1294 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1295 iris_memzone_for_address(old_bo
->gtt_offset
));
1299 /* Swap out the backing storage */
1302 /* Rebind the buffer, replacing any state referring to the old BO's
1303 * address, and marking state dirty so it's reemitted.
1305 screen
->vtbl
.rebind_buffer(ice
, res
);
1307 util_range_set_empty(&res
->valid_buffer_range
);
1309 iris_bo_unreference(old_bo
);
1313 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1314 const struct pipe_box
*flush_box
)
1316 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1319 struct iris_transfer
*map
= (void *) xfer
;
1321 struct pipe_box src_box
= *flush_box
;
1323 /* Account for extra alignment padding in staging buffer */
1324 if (xfer
->resource
->target
== PIPE_BUFFER
)
1325 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1327 struct pipe_box dst_box
= (struct pipe_box
) {
1328 .x
= xfer
->box
.x
+ flush_box
->x
,
1329 .y
= xfer
->box
.y
+ flush_box
->y
,
1330 .z
= xfer
->box
.z
+ flush_box
->z
,
1331 .width
= flush_box
->width
,
1332 .height
= flush_box
->height
,
1333 .depth
= flush_box
->depth
,
1336 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1337 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1342 iris_unmap_copy_region(struct iris_transfer
*map
)
1344 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1350 iris_map_copy_region(struct iris_transfer
*map
)
1352 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1353 struct pipe_transfer
*xfer
= &map
->base
;
1354 struct pipe_box
*box
= &xfer
->box
;
1355 struct iris_resource
*res
= (void *) xfer
->resource
;
1357 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1358 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1360 struct pipe_resource templ
= (struct pipe_resource
) {
1361 .usage
= PIPE_USAGE_STAGING
,
1362 .width0
= box
->width
+ extra
,
1363 .height0
= box
->height
,
1365 .nr_samples
= xfer
->resource
->nr_samples
,
1366 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1367 .array_size
= box
->depth
,
1368 .format
= res
->internal_format
,
1371 if (xfer
->resource
->target
== PIPE_BUFFER
)
1372 templ
.target
= PIPE_BUFFER
;
1373 else if (templ
.array_size
> 1)
1374 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1376 templ
.target
= PIPE_TEXTURE_2D
;
1378 map
->staging
= iris_resource_create(pscreen
, &templ
);
1379 assert(map
->staging
);
1381 if (templ
.target
!= PIPE_BUFFER
) {
1382 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1383 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1384 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1387 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1388 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1389 xfer
->resource
, xfer
->level
, box
);
1390 /* Ensure writes to the staging BO land before we map it below. */
1391 iris_emit_pipe_control_flush(map
->batch
,
1392 "transfer read: flush before mapping",
1393 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1394 PIPE_CONTROL_CS_STALL
);
1397 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1399 if (iris_batch_references(map
->batch
, staging_bo
))
1400 iris_batch_flush(map
->batch
);
1403 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1405 map
->unmap
= iris_unmap_copy_region
;
1409 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1410 unsigned *out_x0_el
, unsigned *out_y0_el
)
1412 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1413 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1415 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1420 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1421 * different tiling patterns.
1424 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1425 uint32_t *tile_w
, uint32_t *tile_h
)
1436 case ISL_TILING_LINEAR
:
1441 unreachable("not reached");
1447 * This function computes masks that may be used to select the bits of the X
1448 * and Y coordinates that indicate the offset within a tile. If the BO is
1449 * untiled, the masks are set to 0.
1452 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1453 uint32_t *mask_x
, uint32_t *mask_y
)
1455 uint32_t tile_w_bytes
, tile_h
;
1457 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1459 *mask_x
= tile_w_bytes
/ cpp
- 1;
1460 *mask_y
= tile_h
- 1;
1464 * Compute the offset (in bytes) from the start of the BO to the given x
1465 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1466 * multiples of the tile size.
1469 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1470 uint32_t x
, uint32_t y
)
1472 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1473 unsigned cpp
= fmtl
->bpb
/ 8;
1474 uint32_t pitch
= res
->surf
.row_pitch_B
;
1476 switch (res
->surf
.tiling
) {
1478 unreachable("not reached");
1479 case ISL_TILING_LINEAR
:
1480 return y
* pitch
+ x
* cpp
;
1482 assert((x
% (512 / cpp
)) == 0);
1483 assert((y
% 8) == 0);
1484 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1486 assert((x
% (128 / cpp
)) == 0);
1487 assert((y
% 32) == 0);
1488 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1493 * Rendering with tiled buffers requires that the base address of the buffer
1494 * be aligned to a page boundary. For renderbuffers, and sometimes with
1495 * textures, we may want the surface to point at a texture image level that
1496 * isn't at a page boundary.
1498 * This function returns an appropriately-aligned base offset
1499 * according to the tiling restrictions, plus any required x/y offset
1503 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1504 uint32_t level
, uint32_t z
,
1505 uint32_t *tile_x
, uint32_t *tile_y
)
1508 uint32_t mask_x
, mask_y
;
1510 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1511 const unsigned cpp
= fmtl
->bpb
/ 8;
1513 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1514 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1516 *tile_x
= x
& mask_x
;
1517 *tile_y
= y
& mask_y
;
1519 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1523 * Get pointer offset into stencil buffer.
1525 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1526 * must decode the tile's layout in software.
1529 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1531 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1533 * Even though the returned offset is always positive, the return type is
1535 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1536 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1539 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1541 uint32_t tile_size
= 4096;
1542 uint32_t tile_width
= 64;
1543 uint32_t tile_height
= 64;
1544 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1546 uint32_t tile_x
= x
/ tile_width
;
1547 uint32_t tile_y
= y
/ tile_height
;
1549 /* The byte's address relative to the tile's base addres. */
1550 uint32_t byte_x
= x
% tile_width
;
1551 uint32_t byte_y
= y
% tile_height
;
1553 uintptr_t u
= tile_y
* row_size
1554 + tile_x
* tile_size
1555 + 512 * (byte_x
/ 8)
1557 + 32 * ((byte_y
/ 4) % 2)
1558 + 16 * ((byte_x
/ 4) % 2)
1559 + 8 * ((byte_y
/ 2) % 2)
1560 + 4 * ((byte_x
/ 2) % 2)
1568 iris_unmap_s8(struct iris_transfer
*map
)
1570 struct pipe_transfer
*xfer
= &map
->base
;
1571 const struct pipe_box
*box
= &xfer
->box
;
1572 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1573 struct isl_surf
*surf
= &res
->surf
;
1575 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1576 uint8_t *untiled_s8_map
= map
->ptr
;
1577 uint8_t *tiled_s8_map
=
1578 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1580 for (int s
= 0; s
< box
->depth
; s
++) {
1581 unsigned x0_el
, y0_el
;
1582 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1584 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1585 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1586 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1588 y0_el
+ box
->y
+ y
);
1589 tiled_s8_map
[offset
] =
1590 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1600 iris_map_s8(struct iris_transfer
*map
)
1602 struct pipe_transfer
*xfer
= &map
->base
;
1603 const struct pipe_box
*box
= &xfer
->box
;
1604 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1605 struct isl_surf
*surf
= &res
->surf
;
1607 xfer
->stride
= surf
->row_pitch_B
;
1608 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1610 /* The tiling and detiling functions require that the linear buffer has
1611 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1612 * over-allocate the linear buffer to get the proper alignment.
1614 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1615 assert(map
->buffer
);
1617 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1618 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1619 * invalidate is set, since we'll be writing the whole rectangle from our
1620 * temporary buffer back out.
1622 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1623 uint8_t *untiled_s8_map
= map
->ptr
;
1624 uint8_t *tiled_s8_map
=
1625 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1627 for (int s
= 0; s
< box
->depth
; s
++) {
1628 unsigned x0_el
, y0_el
;
1629 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1631 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1632 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1633 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1635 y0_el
+ box
->y
+ y
);
1636 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1637 tiled_s8_map
[offset
];
1643 map
->unmap
= iris_unmap_s8
;
1646 /* Compute extent parameters for use with tiled_memcpy functions.
1647 * xs are in units of bytes and ys are in units of strides.
1650 tile_extents(const struct isl_surf
*surf
,
1651 const struct pipe_box
*box
,
1652 unsigned level
, int z
,
1653 unsigned *x1_B
, unsigned *x2_B
,
1654 unsigned *y1_el
, unsigned *y2_el
)
1656 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1657 const unsigned cpp
= fmtl
->bpb
/ 8;
1659 assert(box
->x
% fmtl
->bw
== 0);
1660 assert(box
->y
% fmtl
->bh
== 0);
1662 unsigned x0_el
, y0_el
;
1663 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1665 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1666 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1667 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1668 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1672 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1674 struct pipe_transfer
*xfer
= &map
->base
;
1675 const struct pipe_box
*box
= &xfer
->box
;
1676 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1677 struct isl_surf
*surf
= &res
->surf
;
1679 const bool has_swizzling
= false;
1681 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1683 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1685 for (int s
= 0; s
< box
->depth
; s
++) {
1686 unsigned x1
, x2
, y1
, y2
;
1687 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1689 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1691 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1692 surf
->row_pitch_B
, xfer
->stride
,
1693 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1696 os_free_aligned(map
->buffer
);
1697 map
->buffer
= map
->ptr
= NULL
;
1701 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1703 struct pipe_transfer
*xfer
= &map
->base
;
1704 const struct pipe_box
*box
= &xfer
->box
;
1705 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1706 struct isl_surf
*surf
= &res
->surf
;
1708 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1709 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1711 unsigned x1
, x2
, y1
, y2
;
1712 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1714 /* The tiling and detiling functions require that the linear buffer has
1715 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1716 * over-allocate the linear buffer to get the proper alignment.
1719 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1720 assert(map
->buffer
);
1721 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1723 const bool has_swizzling
= false;
1725 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1727 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1729 for (int s
= 0; s
< box
->depth
; s
++) {
1730 unsigned x1
, x2
, y1
, y2
;
1731 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1733 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1734 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1736 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1737 surf
->row_pitch_B
, has_swizzling
,
1738 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1742 map
->unmap
= iris_unmap_tiled_memcpy
;
1746 iris_map_direct(struct iris_transfer
*map
)
1748 struct pipe_transfer
*xfer
= &map
->base
;
1749 struct pipe_box
*box
= &xfer
->box
;
1750 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1752 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1754 if (res
->base
.target
== PIPE_BUFFER
) {
1756 xfer
->layer_stride
= 0;
1758 map
->ptr
= ptr
+ box
->x
;
1760 struct isl_surf
*surf
= &res
->surf
;
1761 const struct isl_format_layout
*fmtl
=
1762 isl_format_get_layout(surf
->format
);
1763 const unsigned cpp
= fmtl
->bpb
/ 8;
1764 unsigned x0_el
, y0_el
;
1766 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1768 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1769 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1771 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1776 can_promote_to_async(const struct iris_resource
*res
,
1777 const struct pipe_box
*box
,
1778 enum pipe_transfer_usage usage
)
1780 /* If we're writing to a section of the buffer that hasn't even been
1781 * initialized with useful data, then we can safely promote this write
1782 * to be unsynchronized. This helps the common pattern of appending data.
1784 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1785 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1786 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1787 box
->x
+ box
->width
);
1791 iris_transfer_map(struct pipe_context
*ctx
,
1792 struct pipe_resource
*resource
,
1794 enum pipe_transfer_usage usage
,
1795 const struct pipe_box
*box
,
1796 struct pipe_transfer
**ptransfer
)
1798 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1799 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1800 struct isl_surf
*surf
= &res
->surf
;
1802 if (iris_resource_unfinished_aux_import(res
))
1803 iris_resource_finish_aux_import(ctx
->screen
, res
);
1805 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1806 /* Replace the backing storage with a fresh buffer for non-async maps */
1807 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1808 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1809 iris_invalidate_resource(ctx
, resource
);
1811 /* If we can discard the whole resource, we can discard the range. */
1812 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1815 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1816 can_promote_to_async(res
, box
, usage
)) {
1817 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1820 bool need_resolve
= false;
1821 bool need_color_resolve
= false;
1823 if (resource
->target
!= PIPE_BUFFER
) {
1824 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1825 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1827 need_color_resolve
=
1828 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1829 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1830 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) &&
1831 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1833 need_resolve
= need_color_resolve
||
1835 need_stencil_resolve
;
1838 bool map_would_stall
= false;
1840 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1841 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1843 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1844 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1848 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1849 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1852 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1853 struct pipe_transfer
*xfer
= &map
->base
;
1858 memset(map
, 0, sizeof(*map
));
1859 map
->dbg
= &ice
->dbg
;
1861 pipe_resource_reference(&xfer
->resource
, resource
);
1862 xfer
->level
= level
;
1863 xfer
->usage
= usage
;
1867 map
->dest_had_defined_contents
=
1868 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1869 box
->x
+ box
->width
);
1871 if (usage
& PIPE_TRANSFER_WRITE
)
1872 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1874 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1875 * there is to access them simultaneously on the CPU & GPU. This also
1876 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1877 * contain state we're constructing for a GPU draw call, which would
1878 * kill us with infinite stack recursion.
1880 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1881 PIPE_TRANSFER_COHERENT
|
1882 PIPE_TRANSFER_MAP_DIRECTLY
);
1884 /* GPU copies are not useful for buffer reads. Instead of stalling to
1885 * read from the original buffer, we'd simply copy it to a temporary...
1886 * then stall (a bit longer) to read from that buffer.
1888 * Images are less clear-cut. Color resolves are destructive, removing
1889 * the underlying compression, so we'd rather blit the data to a linear
1890 * temporary and map that, to avoid the resolve. (It might be better to
1891 * a tiled temporary and use the tiled_memcpy paths...)
1893 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1896 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1897 if (fmtl
->txc
== ISL_TXC_ASTC
)
1900 if ((map_would_stall
||
1901 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1902 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) && !no_gpu
) {
1903 /* If we need a synchronous mapping and the resource is busy, or needs
1904 * resolving, we copy to/from a linear temporary buffer using the GPU.
1906 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1907 map
->blorp
= &ice
->blorp
;
1908 iris_map_copy_region(map
);
1910 /* Otherwise we're free to map on the CPU. */
1913 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1914 usage
& PIPE_TRANSFER_WRITE
);
1917 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1918 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1919 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1920 iris_batch_flush(&ice
->batches
[i
]);
1924 if (surf
->tiling
== ISL_TILING_W
) {
1925 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1927 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1928 iris_map_tiled_memcpy(map
);
1930 iris_map_direct(map
);
1938 iris_transfer_flush_region(struct pipe_context
*ctx
,
1939 struct pipe_transfer
*xfer
,
1940 const struct pipe_box
*box
)
1942 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1943 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1944 struct iris_transfer
*map
= (void *) xfer
;
1947 iris_flush_staging_region(xfer
, box
);
1949 uint32_t history_flush
= 0;
1951 if (res
->base
.target
== PIPE_BUFFER
) {
1953 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1955 if (map
->dest_had_defined_contents
)
1956 history_flush
|= iris_flush_bits_for_history(res
);
1958 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1961 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1962 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1963 struct iris_batch
*batch
= &ice
->batches
[i
];
1964 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1965 iris_batch_maybe_flush(batch
, 24);
1966 iris_emit_pipe_control_flush(batch
,
1967 "cache history: transfer flush",
1973 /* Make sure we flag constants dirty even if there's no need to emit
1974 * any PIPE_CONTROLs to a batch.
1976 iris_dirty_for_history(ice
, res
);
1980 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1982 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1983 struct iris_transfer
*map
= (void *) xfer
;
1985 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1986 PIPE_TRANSFER_COHERENT
))) {
1987 struct pipe_box flush_box
= {
1988 .x
= 0, .y
= 0, .z
= 0,
1989 .width
= xfer
->box
.width
,
1990 .height
= xfer
->box
.height
,
1991 .depth
= xfer
->box
.depth
,
1993 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1999 pipe_resource_reference(&xfer
->resource
, NULL
);
2000 slab_free(&ice
->transfer_pool
, map
);
2004 * The pipe->texture_subdata() driver hook.
2006 * Mesa's state tracker takes this path whenever possible, even with
2007 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2010 iris_texture_subdata(struct pipe_context
*ctx
,
2011 struct pipe_resource
*resource
,
2014 const struct pipe_box
*box
,
2017 unsigned layer_stride
)
2019 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2020 struct iris_resource
*res
= (struct iris_resource
*)resource
;
2021 const struct isl_surf
*surf
= &res
->surf
;
2023 assert(resource
->target
!= PIPE_BUFFER
);
2025 if (iris_resource_unfinished_aux_import(res
))
2026 iris_resource_finish_aux_import(ctx
->screen
, res
);
2028 /* Just use the transfer-based path for linear buffers - it will already
2029 * do a direct mapping, or a simple linear staging buffer.
2031 * Linear staging buffers appear to be better than tiled ones, too, so
2032 * take that path if we need the GPU to perform color compression, or
2033 * stall-avoidance blits.
2035 if (surf
->tiling
== ISL_TILING_LINEAR
||
2036 (isl_aux_usage_has_ccs(res
->aux
.usage
) &&
2037 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) ||
2038 resource_is_busy(ice
, res
)) {
2039 return u_default_texture_subdata(ctx
, resource
, level
, usage
, box
,
2040 data
, stride
, layer_stride
);
2043 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2045 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
, true);
2047 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2048 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
2049 iris_batch_flush(&ice
->batches
[i
]);
2052 uint8_t *dst
= iris_bo_map(&ice
->dbg
, res
->bo
, MAP_WRITE
| MAP_RAW
);
2054 for (int s
= 0; s
< box
->depth
; s
++) {
2055 const uint8_t *src
= data
+ s
* layer_stride
;
2057 if (surf
->tiling
== ISL_TILING_W
) {
2058 unsigned x0_el
, y0_el
;
2059 get_image_offset_el(surf
, level
, box
->z
+ s
, &x0_el
, &y0_el
);
2061 for (unsigned y
= 0; y
< box
->height
; y
++) {
2062 for (unsigned x
= 0; x
< box
->width
; x
++) {
2063 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
2065 y0_el
+ box
->y
+ y
);
2066 dst
[offset
] = src
[y
* stride
+ x
];
2070 unsigned x1
, x2
, y1
, y2
;
2072 tile_extents(surf
, box
, level
, s
, &x1
, &x2
, &y1
, &y2
);
2074 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
,
2075 (void *)dst
, (void *)src
,
2076 surf
->row_pitch_B
, stride
,
2077 false, surf
->tiling
, ISL_MEMCPY
);
2083 * Mark state dirty that needs to be re-emitted when a resource is written.
2086 iris_dirty_for_history(struct iris_context
*ice
,
2087 struct iris_resource
*res
)
2089 uint64_t stage_dirty
= 0ull;
2091 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2092 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2093 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2096 ice
->state
.stage_dirty
|= stage_dirty
;
2100 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2101 * resource becomes visible, and any stale read cache data is invalidated.
2104 iris_flush_bits_for_history(struct iris_resource
*res
)
2106 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2108 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2109 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2110 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2113 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2114 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2116 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2117 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2119 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2120 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2126 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2127 struct iris_batch
*batch
,
2128 struct iris_resource
*res
,
2129 uint32_t extra_flags
,
2132 if (res
->base
.target
!= PIPE_BUFFER
)
2135 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2137 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2139 iris_dirty_for_history(ice
, res
);
2143 iris_resource_set_clear_color(struct iris_context
*ice
,
2144 struct iris_resource
*res
,
2145 union isl_color_value color
)
2147 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2148 res
->aux
.clear_color
= color
;
2155 union isl_color_value
2156 iris_resource_get_clear_color(const struct iris_resource
*res
,
2157 struct iris_bo
**clear_color_bo
,
2158 uint64_t *clear_color_offset
)
2160 assert(res
->aux
.bo
);
2163 *clear_color_bo
= res
->aux
.clear_color_bo
;
2164 if (clear_color_offset
)
2165 *clear_color_offset
= res
->aux
.clear_color_offset
;
2166 return res
->aux
.clear_color
;
2169 static enum pipe_format
2170 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2172 struct iris_resource
*res
= (void *) p_res
;
2173 return res
->internal_format
;
2176 static const struct u_transfer_vtbl transfer_vtbl
= {
2177 .resource_create
= iris_resource_create
,
2178 .resource_destroy
= iris_resource_destroy
,
2179 .transfer_map
= iris_transfer_map
,
2180 .transfer_unmap
= iris_transfer_unmap
,
2181 .transfer_flush_region
= iris_transfer_flush_region
,
2182 .get_internal_format
= iris_resource_get_internal_format
,
2183 .set_stencil
= iris_resource_set_separate_stencil
,
2184 .get_stencil
= iris_resource_get_separate_stencil
,
2188 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2190 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2191 pscreen
->resource_create_with_modifiers
=
2192 iris_resource_create_with_modifiers
;
2193 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2194 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2195 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2196 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2197 pscreen
->resource_get_param
= iris_resource_get_param
;
2198 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2199 pscreen
->transfer_helper
=
2200 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2204 iris_init_resource_functions(struct pipe_context
*ctx
)
2206 ctx
->flush_resource
= iris_flush_resource
;
2207 ctx
->invalidate_resource
= iris_invalidate_resource
;
2208 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2209 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2210 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2211 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2212 ctx
->texture_subdata
= iris_texture_subdata
;