a32328b31a022c2ab7c895b39f4ec786eda10035
[mesa.git] / src / gallium / drivers / iris / iris_resource.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_resource.c
25 *
26 * Resources are images, buffers, and other objects used by the GPU.
27 *
28 * XXX: explain resources
29 */
30
31 #include <stdio.h>
32 #include <errno.h>
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
52 #include "isl/isl.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
55
56 enum modifier_priority {
57 MODIFIER_PRIORITY_INVALID = 0,
58 MODIFIER_PRIORITY_LINEAR,
59 MODIFIER_PRIORITY_X,
60 MODIFIER_PRIORITY_Y,
61 MODIFIER_PRIORITY_Y_CCS,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS,
63 };
64
65 static const uint64_t priority_to_modifier[] = {
66 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
67 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
68 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
69 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
70 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
72 };
73
74 static bool
75 modifier_is_supported(const struct gen_device_info *devinfo,
76 enum pipe_format pfmt, uint64_t modifier)
77 {
78 /* Check for basic device support. */
79 switch (modifier) {
80 case DRM_FORMAT_MOD_LINEAR:
81 case I915_FORMAT_MOD_X_TILED:
82 case I915_FORMAT_MOD_Y_TILED:
83 break;
84 case I915_FORMAT_MOD_Y_TILED_CCS:
85 if (devinfo->gen <= 8 || devinfo->gen >= 12)
86 return false;
87 break;
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
89 if (devinfo->gen != 12)
90 return false;
91 break;
92 case DRM_FORMAT_MOD_INVALID:
93 default:
94 return false;
95 }
96
97 /* Check remaining requirements. */
98 switch (modifier) {
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
100 case I915_FORMAT_MOD_Y_TILED_CCS: {
101 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
102 return false;
103
104 enum isl_format rt_format =
105 iris_format_for_usage(devinfo, pfmt,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;
107
108 if (rt_format == ISL_FORMAT_UNSUPPORTED ||
109 !isl_format_supports_ccs_e(devinfo, rt_format))
110 return false;
111 break;
112 }
113 default:
114 break;
115 }
116
117 return true;
118 }
119
120 static uint64_t
121 select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
122 const uint64_t *modifiers,
123 int count)
124 {
125 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
126
127 for (int i = 0; i < count; i++) {
128 if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
129 continue;
130
131 switch (modifiers[i]) {
132 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
133 prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS);
134 break;
135 case I915_FORMAT_MOD_Y_TILED_CCS:
136 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
137 break;
138 case I915_FORMAT_MOD_Y_TILED:
139 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
140 break;
141 case I915_FORMAT_MOD_X_TILED:
142 prio = MAX2(prio, MODIFIER_PRIORITY_X);
143 break;
144 case DRM_FORMAT_MOD_LINEAR:
145 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
146 break;
147 case DRM_FORMAT_MOD_INVALID:
148 default:
149 break;
150 }
151 }
152
153 return priority_to_modifier[prio];
154 }
155
156 enum isl_surf_dim
157 target_to_isl_surf_dim(enum pipe_texture_target target)
158 {
159 switch (target) {
160 case PIPE_BUFFER:
161 case PIPE_TEXTURE_1D:
162 case PIPE_TEXTURE_1D_ARRAY:
163 return ISL_SURF_DIM_1D;
164 case PIPE_TEXTURE_2D:
165 case PIPE_TEXTURE_CUBE:
166 case PIPE_TEXTURE_RECT:
167 case PIPE_TEXTURE_2D_ARRAY:
168 case PIPE_TEXTURE_CUBE_ARRAY:
169 return ISL_SURF_DIM_2D;
170 case PIPE_TEXTURE_3D:
171 return ISL_SURF_DIM_3D;
172 case PIPE_MAX_TEXTURE_TYPES:
173 break;
174 }
175 unreachable("invalid texture type");
176 }
177
178 static void
179 iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
180 enum pipe_format pfmt,
181 int max,
182 uint64_t *modifiers,
183 unsigned int *external_only,
184 int *count)
185 {
186 struct iris_screen *screen = (void *) pscreen;
187 const struct gen_device_info *devinfo = &screen->devinfo;
188
189 uint64_t all_modifiers[] = {
190 DRM_FORMAT_MOD_LINEAR,
191 I915_FORMAT_MOD_X_TILED,
192 I915_FORMAT_MOD_Y_TILED,
193 I915_FORMAT_MOD_Y_TILED_CCS,
194 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
195 };
196
197 int supported_mods = 0;
198
199 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
200 if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
201 continue;
202
203 if (supported_mods < max) {
204 if (modifiers)
205 modifiers[supported_mods] = all_modifiers[i];
206
207 if (external_only)
208 external_only[supported_mods] = util_format_is_yuv(pfmt);
209 }
210
211 supported_mods++;
212 }
213
214 *count = supported_mods;
215 }
216
217 enum isl_format
218 iris_image_view_get_format(struct iris_context *ice,
219 const struct pipe_image_view *img)
220 {
221 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
222 const struct gen_device_info *devinfo = &screen->devinfo;
223
224 isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
225 enum isl_format isl_fmt =
226 iris_format_for_usage(devinfo, img->format, usage).fmt;
227
228 if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
229 /* On Gen8, try to use typed surfaces reads (which support a
230 * limited number of formats), and if not possible, fall back
231 * to untyped reads.
232 */
233 if (devinfo->gen == 8 &&
234 !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
235 return ISL_FORMAT_RAW;
236 else
237 return isl_lower_storage_image_format(devinfo, isl_fmt);
238 }
239
240 return isl_fmt;
241 }
242
243 struct pipe_resource *
244 iris_resource_get_separate_stencil(struct pipe_resource *p_res)
245 {
246 /* For packed depth-stencil, we treat depth as the primary resource
247 * and store S8 as the "second plane" resource.
248 */
249 if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT)
250 return p_res->next;
251
252 return NULL;
253
254 }
255
256 static void
257 iris_resource_set_separate_stencil(struct pipe_resource *p_res,
258 struct pipe_resource *stencil)
259 {
260 assert(util_format_has_depth(util_format_description(p_res->format)));
261 pipe_resource_reference(&p_res->next, stencil);
262 }
263
264 void
265 iris_get_depth_stencil_resources(struct pipe_resource *res,
266 struct iris_resource **out_z,
267 struct iris_resource **out_s)
268 {
269 if (!res) {
270 *out_z = NULL;
271 *out_s = NULL;
272 return;
273 }
274
275 if (res->format != PIPE_FORMAT_S8_UINT) {
276 *out_z = (void *) res;
277 *out_s = (void *) iris_resource_get_separate_stencil(res);
278 } else {
279 *out_z = NULL;
280 *out_s = (void *) res;
281 }
282 }
283
284 enum isl_dim_layout
285 iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
286 enum isl_tiling tiling,
287 enum pipe_texture_target target)
288 {
289 switch (target) {
290 case PIPE_TEXTURE_1D:
291 case PIPE_TEXTURE_1D_ARRAY:
292 return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
293 ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
294
295 case PIPE_TEXTURE_2D:
296 case PIPE_TEXTURE_2D_ARRAY:
297 case PIPE_TEXTURE_RECT:
298 case PIPE_TEXTURE_CUBE:
299 case PIPE_TEXTURE_CUBE_ARRAY:
300 return ISL_DIM_LAYOUT_GEN4_2D;
301
302 case PIPE_TEXTURE_3D:
303 return (devinfo->gen >= 9 ?
304 ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
305
306 case PIPE_MAX_TEXTURE_TYPES:
307 case PIPE_BUFFER:
308 break;
309 }
310 unreachable("invalid texture type");
311 }
312
313 void
314 iris_resource_disable_aux(struct iris_resource *res)
315 {
316 iris_bo_unreference(res->aux.bo);
317 iris_bo_unreference(res->aux.clear_color_bo);
318 free(res->aux.state);
319
320 res->aux.usage = ISL_AUX_USAGE_NONE;
321 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
322 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
323 res->aux.has_hiz = 0;
324 res->aux.surf.size_B = 0;
325 res->aux.bo = NULL;
326 res->aux.extra_aux.surf.size_B = 0;
327 res->aux.clear_color_bo = NULL;
328 res->aux.state = NULL;
329 }
330
331 static void
332 iris_resource_destroy(struct pipe_screen *screen,
333 struct pipe_resource *resource)
334 {
335 struct iris_resource *res = (struct iris_resource *)resource;
336
337 if (resource->target == PIPE_BUFFER)
338 util_range_destroy(&res->valid_buffer_range);
339
340 iris_resource_disable_aux(res);
341
342 iris_bo_unreference(res->bo);
343 iris_pscreen_unref(res->base.screen);
344
345 free(res);
346 }
347
348 static struct iris_resource *
349 iris_alloc_resource(struct pipe_screen *pscreen,
350 const struct pipe_resource *templ)
351 {
352 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
353 if (!res)
354 return NULL;
355
356 res->base = *templ;
357 res->base.screen = iris_pscreen_ref(pscreen);
358 pipe_reference_init(&res->base.reference, 1);
359
360 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
361 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
362
363 if (templ->target == PIPE_BUFFER)
364 util_range_init(&res->valid_buffer_range);
365
366 return res;
367 }
368
369 unsigned
370 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
371 {
372 if (res->surf.dim == ISL_SURF_DIM_3D)
373 return minify(res->surf.logical_level0_px.depth, level);
374 else
375 return res->surf.logical_level0_px.array_len;
376 }
377
378 static enum isl_aux_state **
379 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
380 {
381 assert(res->aux.state == NULL);
382
383 uint32_t total_slices = 0;
384 for (uint32_t level = 0; level < res->surf.levels; level++)
385 total_slices += iris_get_num_logical_layers(res, level);
386
387 const size_t per_level_array_size =
388 res->surf.levels * sizeof(enum isl_aux_state *);
389
390 /* We're going to allocate a single chunk of data for both the per-level
391 * reference array and the arrays of aux_state. This makes cleanup
392 * significantly easier.
393 */
394 const size_t total_size =
395 per_level_array_size + total_slices * sizeof(enum isl_aux_state);
396
397 void *data = malloc(total_size);
398 if (!data)
399 return NULL;
400
401 enum isl_aux_state **per_level_arr = data;
402 enum isl_aux_state *s = data + per_level_array_size;
403 for (uint32_t level = 0; level < res->surf.levels; level++) {
404 per_level_arr[level] = s;
405 const unsigned level_layers = iris_get_num_logical_layers(res, level);
406 for (uint32_t a = 0; a < level_layers; a++)
407 *(s++) = initial;
408 }
409 assert((void *)s == data + total_size);
410
411 return per_level_arr;
412 }
413
414 static unsigned
415 iris_get_aux_clear_color_state_size(struct iris_screen *screen)
416 {
417 const struct gen_device_info *devinfo = &screen->devinfo;
418 return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
419 }
420
421 static void
422 map_aux_addresses(struct iris_screen *screen, struct iris_resource *res)
423 {
424 const struct gen_device_info *devinfo = &screen->devinfo;
425 if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
426 void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
427 assert(aux_map_ctx);
428 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
429 res->aux.extra_aux.offset : res->aux.offset;
430 gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset,
431 res->aux.bo->gtt_offset + aux_offset);
432 res->bo->aux_map_address = res->aux.bo->gtt_offset;
433 }
434 }
435
436 static bool
437 want_ccs_e_for_format(const struct gen_device_info *devinfo,
438 enum isl_format format)
439 {
440 if (!isl_format_supports_ccs_e(devinfo, format))
441 return false;
442
443 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
444
445 /* CCS_E seems to significantly hurt performance with 32-bit floating
446 * point formats. For example, Paraview's "Wavelet Volume" case uses
447 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
448 * formats causes a 62% FPS drop.
449 *
450 * However, many benchmarks seem to use 16-bit float with no issues.
451 */
452 if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
453 return false;
454
455 return true;
456 }
457
458 static bool
459 iris_resource_configure_main(const struct iris_screen *screen,
460 struct iris_resource *res,
461 const struct pipe_resource *templ,
462 uint64_t modifier, uint32_t row_pitch_B)
463 {
464 res->mod_info = isl_drm_modifier_get_info(modifier);
465
466 if (modifier != DRM_FORMAT_MOD_INVALID && res->mod_info == NULL)
467 return false;
468
469 isl_tiling_flags_t tiling_flags = 0;
470
471 if (res->mod_info != NULL) {
472 tiling_flags = 1 << res->mod_info->tiling;
473 } else if (templ->usage == PIPE_USAGE_STAGING ||
474 templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) {
475 tiling_flags = ISL_TILING_LINEAR_BIT;
476 } else if (templ->bind & PIPE_BIND_SCANOUT) {
477 tiling_flags = screen->devinfo.has_tiling_uapi ?
478 ISL_TILING_X_BIT : ISL_TILING_LINEAR_BIT;
479 } else {
480 tiling_flags = ISL_TILING_ANY_MASK;
481 }
482
483 isl_surf_usage_flags_t usage = 0;
484
485 if (templ->bind & PIPE_BIND_RENDER_TARGET)
486 usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
487
488 if (templ->bind & PIPE_BIND_SAMPLER_VIEW)
489 usage |= ISL_SURF_USAGE_TEXTURE_BIT;
490
491 if (templ->bind & PIPE_BIND_SHADER_IMAGE)
492 usage |= ISL_SURF_USAGE_STORAGE_BIT;
493
494 if (templ->bind & PIPE_BIND_SCANOUT)
495 usage |= ISL_SURF_USAGE_DISPLAY_BIT;
496
497 if (templ->target == PIPE_TEXTURE_CUBE ||
498 templ->target == PIPE_TEXTURE_CUBE_ARRAY) {
499 usage |= ISL_SURF_USAGE_CUBE_BIT;
500 }
501
502 if (templ->usage != PIPE_USAGE_STAGING &&
503 util_format_is_depth_or_stencil(templ->format)) {
504
505 /* Should be handled by u_transfer_helper */
506 assert(!util_format_is_depth_and_stencil(templ->format));
507
508 usage |= templ->format == PIPE_FORMAT_S8_UINT ?
509 ISL_SURF_USAGE_STENCIL_BIT : ISL_SURF_USAGE_DEPTH_BIT;
510 }
511
512 const enum isl_format format =
513 iris_format_for_usage(&screen->devinfo, templ->format, usage).fmt;
514
515 const struct isl_surf_init_info init_info = {
516 .dim = target_to_isl_surf_dim(templ->target),
517 .format = format,
518 .width = templ->width0,
519 .height = templ->height0,
520 .depth = templ->depth0,
521 .levels = templ->last_level + 1,
522 .array_len = templ->array_size,
523 .samples = MAX2(templ->nr_samples, 1),
524 .min_alignment_B = 0,
525 .row_pitch_B = row_pitch_B,
526 .usage = usage,
527 .tiling_flags = tiling_flags
528 };
529
530 if (!isl_surf_init_s(&screen->isl_dev, &res->surf, &init_info))
531 return false;
532
533 res->internal_format = templ->format;
534
535 return true;
536 }
537
538 /**
539 * Configure aux for the resource, but don't allocate it. For images which
540 * might be shared with modifiers, we must allocate the image and aux data in
541 * a single bo.
542 *
543 * Returns false on unexpected error (e.g. allocation failed, or invalid
544 * configuration result).
545 */
546 static bool
547 iris_resource_configure_aux(struct iris_screen *screen,
548 struct iris_resource *res, bool imported)
549 {
550 const struct gen_device_info *devinfo = &screen->devinfo;
551
552 /* Try to create the auxiliary surfaces allowed by the modifier or by
553 * the user if no modifier is specified.
554 */
555 assert(!res->mod_info ||
556 res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
557 res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
558 res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E);
559
560 const bool has_mcs = !res->mod_info &&
561 isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
562
563 const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
564 isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
565
566 const bool has_ccs =
567 ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
568 (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
569 isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
570 &res->aux.extra_aux.surf, 0);
571
572 /* Having both HIZ and MCS is impossible. */
573 assert(!has_mcs || !has_hiz);
574
575 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
576 if (has_ccs && (has_mcs || has_hiz)) {
577 assert(res->aux.extra_aux.surf.size_B > 0 &&
578 res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
579 assert(res->aux.surf.size_B > 0 &&
580 res->aux.surf.usage &
581 (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
582 }
583
584 if (res->mod_info && has_ccs) {
585 /* Only allow a CCS modifier if the aux was created successfully. */
586 res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
587 } else if (has_mcs) {
588 res->aux.possible_usages |=
589 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
590 } else if (has_hiz) {
591 if (!has_ccs) {
592 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
593 } else if (res->surf.samples == 1 &&
594 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
595 /* If this resource is single-sampled and will be used as a texture,
596 * put the HiZ surface in write-through mode so that we can sample
597 * from it.
598 */
599 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
600 } else {
601 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
602 }
603 } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
604 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
605 } else if (has_ccs) {
606 if (want_ccs_e_for_format(devinfo, res->surf.format)) {
607 res->aux.possible_usages |= devinfo->gen < 12 ?
608 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
609 } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
610 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
611 }
612 }
613
614 res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
615
616 res->aux.sampler_usages = res->aux.possible_usages;
617
618 /* We don't always support sampling with hiz. But when we do, it must be
619 * single sampled.
620 */
621 if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
622 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
623
624 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
625 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
626
627 enum isl_aux_state initial_state;
628 assert(!res->aux.bo);
629
630 switch (res->aux.usage) {
631 case ISL_AUX_USAGE_NONE:
632 /* Update relevant fields to indicate that aux is disabled. */
633 iris_resource_disable_aux(res);
634
635 /* Having no aux buffer is only okay if there's no modifier with aux. */
636 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
637 case ISL_AUX_USAGE_HIZ:
638 case ISL_AUX_USAGE_HIZ_CCS:
639 case ISL_AUX_USAGE_HIZ_CCS_WT:
640 initial_state = ISL_AUX_STATE_AUX_INVALID;
641 break;
642 case ISL_AUX_USAGE_MCS:
643 case ISL_AUX_USAGE_MCS_CCS:
644 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
645 *
646 * "When MCS buffer is enabled and bound to MSRT, it is required
647 * that it is cleared prior to any rendering."
648 *
649 * Since we only use the MCS buffer for rendering, we just clear it
650 * immediately on allocation. The clear value for MCS buffers is all
651 * 1's, so we simply memset it to 0xff.
652 */
653 initial_state = ISL_AUX_STATE_CLEAR;
654 break;
655 case ISL_AUX_USAGE_CCS_D:
656 case ISL_AUX_USAGE_CCS_E:
657 case ISL_AUX_USAGE_GEN12_CCS_E:
658 case ISL_AUX_USAGE_STC_CCS:
659 /* When CCS_E is used, we need to ensure that the CCS starts off in
660 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
661 * Target(s)":
662 *
663 * "If Software wants to enable Color Compression without Fast
664 * clear, Software needs to initialize MCS with zeros."
665 *
666 * A CCS value of 0 indicates that the corresponding block is in the
667 * pass-through state which is what we want.
668 *
669 * For CCS_D, do the same thing. On Gen9+, this avoids having any
670 * undefined bits in the aux buffer.
671 */
672 if (imported) {
673 assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
674 initial_state =
675 isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
676 } else {
677 initial_state = ISL_AUX_STATE_PASS_THROUGH;
678 }
679 break;
680 case ISL_AUX_USAGE_MC:
681 default:
682 unreachable("Unsupported aux mode");
683 }
684
685 /* Create the aux_state for the auxiliary buffer. */
686 res->aux.state = create_aux_state_map(res, initial_state);
687 if (!res->aux.state)
688 return false;
689
690 if (isl_aux_usage_has_hiz(res->aux.usage)) {
691 for (unsigned level = 0; level < res->surf.levels; ++level) {
692 uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
693 uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
694
695 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
696 * For LOD == 0, we can grow the dimensions to make it work.
697 */
698 if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
699 res->aux.has_hiz |= 1 << level;
700 }
701 }
702
703 return true;
704 }
705
706 /**
707 * Initialize the aux buffer contents.
708 *
709 * Returns false on unexpected error (e.g. mapping a BO failed).
710 */
711 static bool
712 iris_resource_init_aux_buf(struct iris_resource *res,
713 unsigned clear_color_state_size)
714 {
715 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
716
717 if (!map)
718 return false;
719
720 if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
721 /* See iris_resource_configure_aux for the memset_value rationale. */
722 uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
723 memset((char*)map + res->aux.offset, memset_value,
724 res->aux.surf.size_B);
725 }
726
727 memset((char*)map + res->aux.extra_aux.offset,
728 0, res->aux.extra_aux.surf.size_B);
729
730 /* Zero the indirect clear color to match ::fast_clear_color. */
731 memset((char *)map + res->aux.clear_color_offset, 0,
732 clear_color_state_size);
733
734 iris_bo_unmap(res->aux.bo);
735
736 if (clear_color_state_size > 0) {
737 res->aux.clear_color_bo = res->aux.bo;
738 iris_bo_reference(res->aux.clear_color_bo);
739 }
740
741 return true;
742 }
743
744 void
745 iris_resource_finish_aux_import(struct pipe_screen *pscreen,
746 struct iris_resource *res)
747 {
748 struct iris_screen *screen = (struct iris_screen *)pscreen;
749 assert(iris_resource_unfinished_aux_import(res));
750 assert(!res->mod_info->supports_clear_color);
751
752 struct iris_resource *aux_res = (void *) res->base.next;
753 assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset &&
754 aux_res->aux.bo);
755
756 assert(res->bo == aux_res->aux.bo);
757 iris_bo_reference(aux_res->aux.bo);
758 res->aux.bo = aux_res->aux.bo;
759
760 res->aux.offset = aux_res->aux.offset;
761
762 assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B));
763 assert(res->aux.clear_color_bo == NULL);
764
765 assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B);
766
767 unsigned clear_color_state_size =
768 iris_get_aux_clear_color_state_size(screen);
769
770 if (clear_color_state_size > 0) {
771 res->aux.clear_color_bo =
772 iris_bo_alloc_tiled(screen->bufmgr, "clear color_buffer",
773 clear_color_state_size, 1, IRIS_MEMZONE_OTHER,
774 I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
775 }
776
777 iris_resource_destroy(&screen->base, res->base.next);
778 res->base.next = NULL;
779
780 map_aux_addresses(screen, res);
781 }
782
783 static struct pipe_resource *
784 iris_resource_create_for_buffer(struct pipe_screen *pscreen,
785 const struct pipe_resource *templ)
786 {
787 struct iris_screen *screen = (struct iris_screen *)pscreen;
788 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
789
790 assert(templ->target == PIPE_BUFFER);
791 assert(templ->height0 <= 1);
792 assert(templ->depth0 <= 1);
793 assert(templ->format == PIPE_FORMAT_NONE ||
794 util_format_get_blocksize(templ->format) == 1);
795
796 res->internal_format = templ->format;
797 res->surf.tiling = ISL_TILING_LINEAR;
798
799 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
800 const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
801 if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
802 memzone = IRIS_MEMZONE_SHADER;
803 name = "shader kernels";
804 } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
805 memzone = IRIS_MEMZONE_SURFACE;
806 name = "surface state";
807 } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
808 memzone = IRIS_MEMZONE_DYNAMIC;
809 name = "dynamic state";
810 }
811
812 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
813 if (!res->bo) {
814 iris_resource_destroy(pscreen, &res->base);
815 return NULL;
816 }
817
818 if (templ->bind & PIPE_BIND_SHARED)
819 iris_bo_make_external(res->bo);
820
821 return &res->base;
822 }
823
824 static struct pipe_resource *
825 iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
826 const struct pipe_resource *templ,
827 const uint64_t *modifiers,
828 int modifiers_count)
829 {
830 struct iris_screen *screen = (struct iris_screen *)pscreen;
831 struct gen_device_info *devinfo = &screen->devinfo;
832 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
833
834 if (!res)
835 return NULL;
836
837 uint64_t modifier =
838 select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
839
840 if (modifier == DRM_FORMAT_MOD_INVALID && modifiers_count > 0) {
841 fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
842 goto fail;
843 }
844
845 UNUSED const bool isl_surf_created_successfully =
846 iris_resource_configure_main(screen, res, templ, modifier, 0);
847 assert(isl_surf_created_successfully);
848
849 const char *name = "miptree";
850 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
851
852 unsigned int flags = 0;
853 if (templ->usage == PIPE_USAGE_STAGING)
854 flags |= BO_ALLOC_COHERENT;
855
856 /* These are for u_upload_mgr buffers only */
857 assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
858 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
859 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
860
861 if (!iris_resource_configure_aux(screen, res, false))
862 goto fail;
863
864 /* Modifiers require the aux data to be in the same buffer as the main
865 * surface, but we combine them even when a modifier is not being used.
866 */
867 uint64_t bo_size = res->surf.size_B;
868
869 /* Allocate space for the aux buffer. */
870 if (res->aux.surf.size_B > 0) {
871 res->aux.offset = ALIGN(bo_size, res->aux.surf.alignment_B);
872 bo_size = res->aux.offset + res->aux.surf.size_B;
873 }
874
875 /* Allocate space for the extra aux buffer. */
876 if (res->aux.extra_aux.surf.size_B > 0) {
877 res->aux.extra_aux.offset =
878 ALIGN(bo_size, res->aux.extra_aux.surf.alignment_B);
879 bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
880 }
881
882 /* Allocate space for the indirect clear color.
883 *
884 * Also add some padding to make sure the fast clear color state buffer
885 * starts at a 4K alignment. We believe that 256B might be enough, but due
886 * to lack of testing we will leave this as 4K for now.
887 */
888 if (res->aux.surf.size_B > 0) {
889 res->aux.clear_color_offset = ALIGN(bo_size, 4096);
890 bo_size = res->aux.clear_color_offset +
891 iris_get_aux_clear_color_state_size(screen);
892 }
893
894 uint32_t alignment = MAX2(4096, res->surf.alignment_B);
895 res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
896 memzone,
897 isl_tiling_to_i915_tiling(res->surf.tiling),
898 res->surf.row_pitch_B, flags);
899
900 if (!res->bo)
901 goto fail;
902
903 if (res->aux.surf.size_B > 0) {
904 res->aux.bo = res->bo;
905 iris_bo_reference(res->aux.bo);
906 unsigned clear_color_state_size =
907 iris_get_aux_clear_color_state_size(screen);
908 if (!iris_resource_init_aux_buf(res, clear_color_state_size))
909 goto fail;
910 map_aux_addresses(screen, res);
911 }
912
913 if (templ->bind & PIPE_BIND_SHARED)
914 iris_bo_make_external(res->bo);
915
916 return &res->base;
917
918 fail:
919 fprintf(stderr, "XXX: resource creation failed\n");
920 iris_resource_destroy(pscreen, &res->base);
921 return NULL;
922
923 }
924
925 static struct pipe_resource *
926 iris_resource_create(struct pipe_screen *pscreen,
927 const struct pipe_resource *templ)
928 {
929 if (templ->target == PIPE_BUFFER)
930 return iris_resource_create_for_buffer(pscreen, templ);
931 else
932 return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
933 }
934
935 static uint64_t
936 tiling_to_modifier(uint32_t tiling)
937 {
938 static const uint64_t map[] = {
939 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
940 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
941 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
942 };
943
944 assert(tiling < ARRAY_SIZE(map));
945
946 return map[tiling];
947 }
948
949 static struct pipe_resource *
950 iris_resource_from_user_memory(struct pipe_screen *pscreen,
951 const struct pipe_resource *templ,
952 void *user_memory)
953 {
954 struct iris_screen *screen = (struct iris_screen *)pscreen;
955 struct iris_bufmgr *bufmgr = screen->bufmgr;
956 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
957 if (!res)
958 return NULL;
959
960 assert(templ->target == PIPE_BUFFER);
961
962 res->internal_format = templ->format;
963 res->bo = iris_bo_create_userptr(bufmgr, "user",
964 user_memory, templ->width0,
965 IRIS_MEMZONE_OTHER);
966 if (!res->bo) {
967 iris_resource_destroy(pscreen, &res->base);
968 return NULL;
969 }
970
971 util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
972
973 return &res->base;
974 }
975
976 static struct pipe_resource *
977 iris_resource_from_handle(struct pipe_screen *pscreen,
978 const struct pipe_resource *templ,
979 struct winsys_handle *whandle,
980 unsigned usage)
981 {
982 assert(templ->target != PIPE_BUFFER);
983
984 struct iris_screen *screen = (struct iris_screen *)pscreen;
985 struct iris_bufmgr *bufmgr = screen->bufmgr;
986 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
987 if (!res)
988 return NULL;
989
990 switch (whandle->type) {
991 case WINSYS_HANDLE_TYPE_FD:
992 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
993 whandle->modifier);
994 break;
995 case WINSYS_HANDLE_TYPE_SHARED:
996 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
997 whandle->handle);
998 break;
999 default:
1000 unreachable("invalid winsys handle type");
1001 }
1002 if (!res->bo)
1003 goto fail;
1004
1005 res->offset = whandle->offset;
1006 res->external_format = whandle->format;
1007
1008 /* Create a surface for each plane specified by the external format. */
1009 if (whandle->plane < util_format_get_num_planes(whandle->format)) {
1010
1011 const uint64_t modifier =
1012 whandle->modifier != DRM_FORMAT_MOD_INVALID ?
1013 whandle->modifier : tiling_to_modifier(res->bo->tiling_mode);
1014
1015 UNUSED const bool isl_surf_created_successfully =
1016 iris_resource_configure_main(screen, res, templ, modifier,
1017 whandle->stride);
1018 assert(isl_surf_created_successfully);
1019 assert(res->bo->tiling_mode ==
1020 isl_tiling_to_i915_tiling(res->surf.tiling));
1021
1022 UNUSED const bool ok = iris_resource_configure_aux(screen, res, true);
1023 assert(ok);
1024 /* The gallium dri layer will create a separate plane resource for the
1025 * aux image. iris_resource_finish_aux_import will merge the separate aux
1026 * parameters back into a single iris_resource.
1027 */
1028 } else {
1029 /* Save modifier import information to reconstruct later. After import,
1030 * this will be available under a second image accessible from the main
1031 * image with res->base.next. See iris_resource_finish_aux_import.
1032 */
1033 res->aux.surf.row_pitch_B = whandle->stride;
1034 res->aux.offset = whandle->offset;
1035 res->aux.bo = res->bo;
1036 res->bo = NULL;
1037 }
1038
1039 return &res->base;
1040
1041 fail:
1042 iris_resource_destroy(pscreen, &res->base);
1043 return NULL;
1044 }
1045
1046 static void
1047 iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
1048 {
1049 struct iris_context *ice = (struct iris_context *)ctx;
1050 struct iris_resource *res = (void *) resource;
1051 const struct isl_drm_modifier_info *mod = res->mod_info;
1052
1053 iris_resource_prepare_access(ice, res,
1054 0, INTEL_REMAINING_LEVELS,
1055 0, INTEL_REMAINING_LAYERS,
1056 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
1057 mod ? mod->supports_clear_color : false);
1058 }
1059
1060 static void
1061 iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
1062 unsigned usage)
1063 {
1064 struct iris_resource *res = (struct iris_resource *)resource;
1065 bool mod_with_aux =
1066 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1067
1068 /* Disable aux usage if explicit flush not set and this is the first time
1069 * we are dealing with this resource and the resource was not created with
1070 * a modifier with aux.
1071 */
1072 if (!mod_with_aux &&
1073 (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
1074 p_atomic_read(&resource->reference.count) == 1) {
1075 iris_resource_disable_aux(res);
1076 }
1077 }
1078
1079 static bool
1080 iris_resource_get_param(struct pipe_screen *pscreen,
1081 struct pipe_context *context,
1082 struct pipe_resource *resource,
1083 unsigned plane,
1084 unsigned layer,
1085 enum pipe_resource_param param,
1086 unsigned handle_usage,
1087 uint64_t *value)
1088 {
1089 struct iris_screen *screen = (struct iris_screen *)pscreen;
1090 struct iris_resource *res = (struct iris_resource *)resource;
1091 bool mod_with_aux =
1092 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1093 bool wants_aux = mod_with_aux && plane > 0;
1094 bool result;
1095 unsigned handle;
1096
1097 if (iris_resource_unfinished_aux_import(res))
1098 iris_resource_finish_aux_import(pscreen, res);
1099
1100 struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;
1101
1102 iris_resource_disable_aux_on_first_query(resource, handle_usage);
1103
1104 switch (param) {
1105 case PIPE_RESOURCE_PARAM_NPLANES:
1106 if (mod_with_aux) {
1107 *value = 2;
1108 } else {
1109 unsigned count = 0;
1110 for (struct pipe_resource *cur = resource; cur; cur = cur->next)
1111 count++;
1112 *value = count;
1113 }
1114 return true;
1115 case PIPE_RESOURCE_PARAM_STRIDE:
1116 *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
1117 return true;
1118 case PIPE_RESOURCE_PARAM_OFFSET:
1119 *value = wants_aux ? res->aux.offset : 0;
1120 return true;
1121 case PIPE_RESOURCE_PARAM_MODIFIER:
1122 *value = res->mod_info ? res->mod_info->modifier :
1123 tiling_to_modifier(res->bo->tiling_mode);
1124 return true;
1125 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
1126 result = iris_bo_flink(bo, &handle) == 0;
1127 if (result)
1128 *value = handle;
1129 return result;
1130 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
1131 /* Because we share the same drm file across multiple iris_screen, when
1132 * we export a GEM handle we must make sure it is valid in the DRM file
1133 * descriptor the caller is using (this is the FD given at screen
1134 * creation).
1135 */
1136 uint32_t handle;
1137 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1138 return false;
1139 *value = handle;
1140 return true;
1141 }
1142
1143 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
1144 result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
1145 if (result)
1146 *value = handle;
1147 return result;
1148 default:
1149 return false;
1150 }
1151 }
1152
1153 static bool
1154 iris_resource_get_handle(struct pipe_screen *pscreen,
1155 struct pipe_context *ctx,
1156 struct pipe_resource *resource,
1157 struct winsys_handle *whandle,
1158 unsigned usage)
1159 {
1160 struct iris_screen *screen = (struct iris_screen *) pscreen;
1161 struct iris_resource *res = (struct iris_resource *)resource;
1162 bool mod_with_aux =
1163 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1164
1165 iris_resource_disable_aux_on_first_query(resource, usage);
1166
1167 struct iris_bo *bo;
1168 if (mod_with_aux && whandle->plane > 0) {
1169 assert(res->aux.bo);
1170 bo = res->aux.bo;
1171 whandle->stride = res->aux.surf.row_pitch_B;
1172 whandle->offset = res->aux.offset;
1173 } else {
1174 /* If this is a buffer, stride should be 0 - no need to special case */
1175 whandle->stride = res->surf.row_pitch_B;
1176 bo = res->bo;
1177 }
1178
1179 whandle->format = res->external_format;
1180 whandle->modifier =
1181 res->mod_info ? res->mod_info->modifier
1182 : tiling_to_modifier(res->bo->tiling_mode);
1183
1184 #ifndef NDEBUG
1185 enum isl_aux_usage allowed_usage =
1186 usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH ? res->aux.usage :
1187 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
1188
1189 if (res->aux.usage != allowed_usage) {
1190 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
1191 assert(aux_state == ISL_AUX_STATE_RESOLVED ||
1192 aux_state == ISL_AUX_STATE_PASS_THROUGH);
1193 }
1194 #endif
1195
1196 switch (whandle->type) {
1197 case WINSYS_HANDLE_TYPE_SHARED:
1198 return iris_bo_flink(bo, &whandle->handle) == 0;
1199 case WINSYS_HANDLE_TYPE_KMS: {
1200 /* Because we share the same drm file across multiple iris_screen, when
1201 * we export a GEM handle we must make sure it is valid in the DRM file
1202 * descriptor the caller is using (this is the FD given at screen
1203 * creation).
1204 */
1205 uint32_t handle;
1206 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1207 return false;
1208 whandle->handle = handle;
1209 return true;
1210 }
1211 case WINSYS_HANDLE_TYPE_FD:
1212 return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
1213 }
1214
1215 return false;
1216 }
1217
1218 static bool
1219 resource_is_busy(struct iris_context *ice,
1220 struct iris_resource *res)
1221 {
1222 bool busy = iris_bo_busy(res->bo);
1223
1224 for (int i = 0; i < IRIS_BATCH_COUNT; i++)
1225 busy |= iris_batch_references(&ice->batches[i], res->bo);
1226
1227 return busy;
1228 }
1229
1230 static void
1231 iris_invalidate_resource(struct pipe_context *ctx,
1232 struct pipe_resource *resource)
1233 {
1234 struct iris_screen *screen = (void *) ctx->screen;
1235 struct iris_context *ice = (void *) ctx;
1236 struct iris_resource *res = (void *) resource;
1237
1238 if (resource->target != PIPE_BUFFER)
1239 return;
1240
1241 /* If it's already invalidated, don't bother doing anything. */
1242 if (res->valid_buffer_range.start > res->valid_buffer_range.end)
1243 return;
1244
1245 if (!resource_is_busy(ice, res)) {
1246 /* The resource is idle, so just mark that it contains no data and
1247 * keep using the same underlying buffer object.
1248 */
1249 util_range_set_empty(&res->valid_buffer_range);
1250 return;
1251 }
1252
1253 /* Otherwise, try and replace the backing storage with a new BO. */
1254
1255 /* We can't reallocate memory we didn't allocate in the first place. */
1256 if (res->bo->userptr)
1257 return;
1258
1259 // XXX: We should support this.
1260 if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
1261 return;
1262
1263 struct iris_bo *old_bo = res->bo;
1264 struct iris_bo *new_bo =
1265 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
1266 iris_memzone_for_address(old_bo->gtt_offset));
1267 if (!new_bo)
1268 return;
1269
1270 /* Swap out the backing storage */
1271 res->bo = new_bo;
1272
1273 /* Rebind the buffer, replacing any state referring to the old BO's
1274 * address, and marking state dirty so it's reemitted.
1275 */
1276 screen->vtbl.rebind_buffer(ice, res);
1277
1278 util_range_set_empty(&res->valid_buffer_range);
1279
1280 iris_bo_unreference(old_bo);
1281 }
1282
1283 static void
1284 iris_flush_staging_region(struct pipe_transfer *xfer,
1285 const struct pipe_box *flush_box)
1286 {
1287 if (!(xfer->usage & PIPE_TRANSFER_WRITE))
1288 return;
1289
1290 struct iris_transfer *map = (void *) xfer;
1291
1292 struct pipe_box src_box = *flush_box;
1293
1294 /* Account for extra alignment padding in staging buffer */
1295 if (xfer->resource->target == PIPE_BUFFER)
1296 src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
1297
1298 struct pipe_box dst_box = (struct pipe_box) {
1299 .x = xfer->box.x + flush_box->x,
1300 .y = xfer->box.y + flush_box->y,
1301 .z = xfer->box.z + flush_box->z,
1302 .width = flush_box->width,
1303 .height = flush_box->height,
1304 .depth = flush_box->depth,
1305 };
1306
1307 iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
1308 dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
1309 &src_box);
1310 }
1311
1312 static void
1313 iris_unmap_copy_region(struct iris_transfer *map)
1314 {
1315 iris_resource_destroy(map->staging->screen, map->staging);
1316
1317 map->ptr = NULL;
1318 }
1319
1320 static void
1321 iris_map_copy_region(struct iris_transfer *map)
1322 {
1323 struct pipe_screen *pscreen = &map->batch->screen->base;
1324 struct pipe_transfer *xfer = &map->base;
1325 struct pipe_box *box = &xfer->box;
1326 struct iris_resource *res = (void *) xfer->resource;
1327
1328 unsigned extra = xfer->resource->target == PIPE_BUFFER ?
1329 box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
1330
1331 struct pipe_resource templ = (struct pipe_resource) {
1332 .usage = PIPE_USAGE_STAGING,
1333 .width0 = box->width + extra,
1334 .height0 = box->height,
1335 .depth0 = 1,
1336 .nr_samples = xfer->resource->nr_samples,
1337 .nr_storage_samples = xfer->resource->nr_storage_samples,
1338 .array_size = box->depth,
1339 .format = res->internal_format,
1340 };
1341
1342 if (xfer->resource->target == PIPE_BUFFER)
1343 templ.target = PIPE_BUFFER;
1344 else if (templ.array_size > 1)
1345 templ.target = PIPE_TEXTURE_2D_ARRAY;
1346 else
1347 templ.target = PIPE_TEXTURE_2D;
1348
1349 map->staging = iris_resource_create(pscreen, &templ);
1350 assert(map->staging);
1351
1352 if (templ.target != PIPE_BUFFER) {
1353 struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
1354 xfer->stride = isl_surf_get_row_pitch_B(surf);
1355 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1356 }
1357
1358 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1359 iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
1360 xfer->resource, xfer->level, box);
1361 /* Ensure writes to the staging BO land before we map it below. */
1362 iris_emit_pipe_control_flush(map->batch,
1363 "transfer read: flush before mapping",
1364 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1365 PIPE_CONTROL_CS_STALL);
1366 }
1367
1368 struct iris_bo *staging_bo = iris_resource_bo(map->staging);
1369
1370 if (iris_batch_references(map->batch, staging_bo))
1371 iris_batch_flush(map->batch);
1372
1373 map->ptr =
1374 iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
1375
1376 map->unmap = iris_unmap_copy_region;
1377 }
1378
1379 static void
1380 get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z,
1381 unsigned *out_x0_el, unsigned *out_y0_el)
1382 {
1383 if (surf->dim == ISL_SURF_DIM_3D) {
1384 isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
1385 } else {
1386 isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
1387 }
1388 }
1389
1390 /**
1391 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1392 * different tiling patterns.
1393 */
1394 static void
1395 iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
1396 uint32_t *tile_w, uint32_t *tile_h)
1397 {
1398 switch (tiling) {
1399 case ISL_TILING_X:
1400 *tile_w = 512;
1401 *tile_h = 8;
1402 break;
1403 case ISL_TILING_Y0:
1404 *tile_w = 128;
1405 *tile_h = 32;
1406 break;
1407 case ISL_TILING_LINEAR:
1408 *tile_w = cpp;
1409 *tile_h = 1;
1410 break;
1411 default:
1412 unreachable("not reached");
1413 }
1414
1415 }
1416
1417 /**
1418 * This function computes masks that may be used to select the bits of the X
1419 * and Y coordinates that indicate the offset within a tile. If the BO is
1420 * untiled, the masks are set to 0.
1421 */
1422 static void
1423 iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
1424 uint32_t *mask_x, uint32_t *mask_y)
1425 {
1426 uint32_t tile_w_bytes, tile_h;
1427
1428 iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
1429
1430 *mask_x = tile_w_bytes / cpp - 1;
1431 *mask_y = tile_h - 1;
1432 }
1433
1434 /**
1435 * Compute the offset (in bytes) from the start of the BO to the given x
1436 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1437 * multiples of the tile size.
1438 */
1439 static uint32_t
1440 iris_resource_get_aligned_offset(const struct iris_resource *res,
1441 uint32_t x, uint32_t y)
1442 {
1443 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1444 unsigned cpp = fmtl->bpb / 8;
1445 uint32_t pitch = res->surf.row_pitch_B;
1446
1447 switch (res->surf.tiling) {
1448 default:
1449 unreachable("not reached");
1450 case ISL_TILING_LINEAR:
1451 return y * pitch + x * cpp;
1452 case ISL_TILING_X:
1453 assert((x % (512 / cpp)) == 0);
1454 assert((y % 8) == 0);
1455 return y * pitch + x / (512 / cpp) * 4096;
1456 case ISL_TILING_Y0:
1457 assert((x % (128 / cpp)) == 0);
1458 assert((y % 32) == 0);
1459 return y * pitch + x / (128 / cpp) * 4096;
1460 }
1461 }
1462
1463 /**
1464 * Rendering with tiled buffers requires that the base address of the buffer
1465 * be aligned to a page boundary. For renderbuffers, and sometimes with
1466 * textures, we may want the surface to point at a texture image level that
1467 * isn't at a page boundary.
1468 *
1469 * This function returns an appropriately-aligned base offset
1470 * according to the tiling restrictions, plus any required x/y offset
1471 * from there.
1472 */
1473 uint32_t
1474 iris_resource_get_tile_offsets(const struct iris_resource *res,
1475 uint32_t level, uint32_t z,
1476 uint32_t *tile_x, uint32_t *tile_y)
1477 {
1478 uint32_t x, y;
1479 uint32_t mask_x, mask_y;
1480
1481 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1482 const unsigned cpp = fmtl->bpb / 8;
1483
1484 iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y);
1485 get_image_offset_el(&res->surf, level, z, &x, &y);
1486
1487 *tile_x = x & mask_x;
1488 *tile_y = y & mask_y;
1489
1490 return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y);
1491 }
1492
1493 /**
1494 * Get pointer offset into stencil buffer.
1495 *
1496 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1497 * must decode the tile's layout in software.
1498 *
1499 * See
1500 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1501 * Format.
1502 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1503 *
1504 * Even though the returned offset is always positive, the return type is
1505 * signed due to
1506 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1507 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1508 */
1509 static intptr_t
1510 s8_offset(uint32_t stride, uint32_t x, uint32_t y)
1511 {
1512 uint32_t tile_size = 4096;
1513 uint32_t tile_width = 64;
1514 uint32_t tile_height = 64;
1515 uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
1516
1517 uint32_t tile_x = x / tile_width;
1518 uint32_t tile_y = y / tile_height;
1519
1520 /* The byte's address relative to the tile's base addres. */
1521 uint32_t byte_x = x % tile_width;
1522 uint32_t byte_y = y % tile_height;
1523
1524 uintptr_t u = tile_y * row_size
1525 + tile_x * tile_size
1526 + 512 * (byte_x / 8)
1527 + 64 * (byte_y / 8)
1528 + 32 * ((byte_y / 4) % 2)
1529 + 16 * ((byte_x / 4) % 2)
1530 + 8 * ((byte_y / 2) % 2)
1531 + 4 * ((byte_x / 2) % 2)
1532 + 2 * (byte_y % 2)
1533 + 1 * (byte_x % 2);
1534
1535 return u;
1536 }
1537
1538 static void
1539 iris_unmap_s8(struct iris_transfer *map)
1540 {
1541 struct pipe_transfer *xfer = &map->base;
1542 const struct pipe_box *box = &xfer->box;
1543 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1544 struct isl_surf *surf = &res->surf;
1545
1546 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1547 uint8_t *untiled_s8_map = map->ptr;
1548 uint8_t *tiled_s8_map =
1549 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1550
1551 for (int s = 0; s < box->depth; s++) {
1552 unsigned x0_el, y0_el;
1553 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1554
1555 for (uint32_t y = 0; y < box->height; y++) {
1556 for (uint32_t x = 0; x < box->width; x++) {
1557 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1558 x0_el + box->x + x,
1559 y0_el + box->y + y);
1560 tiled_s8_map[offset] =
1561 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
1562 }
1563 }
1564 }
1565 }
1566
1567 free(map->buffer);
1568 }
1569
1570 static void
1571 iris_map_s8(struct iris_transfer *map)
1572 {
1573 struct pipe_transfer *xfer = &map->base;
1574 const struct pipe_box *box = &xfer->box;
1575 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1576 struct isl_surf *surf = &res->surf;
1577
1578 xfer->stride = surf->row_pitch_B;
1579 xfer->layer_stride = xfer->stride * box->height;
1580
1581 /* The tiling and detiling functions require that the linear buffer has
1582 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1583 * over-allocate the linear buffer to get the proper alignment.
1584 */
1585 map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
1586 assert(map->buffer);
1587
1588 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1589 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1590 * invalidate is set, since we'll be writing the whole rectangle from our
1591 * temporary buffer back out.
1592 */
1593 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1594 uint8_t *untiled_s8_map = map->ptr;
1595 uint8_t *tiled_s8_map =
1596 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1597
1598 for (int s = 0; s < box->depth; s++) {
1599 unsigned x0_el, y0_el;
1600 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1601
1602 for (uint32_t y = 0; y < box->height; y++) {
1603 for (uint32_t x = 0; x < box->width; x++) {
1604 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1605 x0_el + box->x + x,
1606 y0_el + box->y + y);
1607 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
1608 tiled_s8_map[offset];
1609 }
1610 }
1611 }
1612 }
1613
1614 map->unmap = iris_unmap_s8;
1615 }
1616
1617 /* Compute extent parameters for use with tiled_memcpy functions.
1618 * xs are in units of bytes and ys are in units of strides.
1619 */
1620 static inline void
1621 tile_extents(const struct isl_surf *surf,
1622 const struct pipe_box *box,
1623 unsigned level, int z,
1624 unsigned *x1_B, unsigned *x2_B,
1625 unsigned *y1_el, unsigned *y2_el)
1626 {
1627 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1628 const unsigned cpp = fmtl->bpb / 8;
1629
1630 assert(box->x % fmtl->bw == 0);
1631 assert(box->y % fmtl->bh == 0);
1632
1633 unsigned x0_el, y0_el;
1634 get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
1635
1636 *x1_B = (box->x / fmtl->bw + x0_el) * cpp;
1637 *y1_el = box->y / fmtl->bh + y0_el;
1638 *x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
1639 *y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
1640 }
1641
1642 static void
1643 iris_unmap_tiled_memcpy(struct iris_transfer *map)
1644 {
1645 struct pipe_transfer *xfer = &map->base;
1646 const struct pipe_box *box = &xfer->box;
1647 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1648 struct isl_surf *surf = &res->surf;
1649
1650 const bool has_swizzling = false;
1651
1652 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1653 char *dst =
1654 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1655
1656 for (int s = 0; s < box->depth; s++) {
1657 unsigned x1, x2, y1, y2;
1658 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1659
1660 void *ptr = map->ptr + s * xfer->layer_stride;
1661
1662 isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
1663 surf->row_pitch_B, xfer->stride,
1664 has_swizzling, surf->tiling, ISL_MEMCPY);
1665 }
1666 }
1667 os_free_aligned(map->buffer);
1668 map->buffer = map->ptr = NULL;
1669 }
1670
1671 static void
1672 iris_map_tiled_memcpy(struct iris_transfer *map)
1673 {
1674 struct pipe_transfer *xfer = &map->base;
1675 const struct pipe_box *box = &xfer->box;
1676 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1677 struct isl_surf *surf = &res->surf;
1678
1679 xfer->stride = ALIGN(surf->row_pitch_B, 16);
1680 xfer->layer_stride = xfer->stride * box->height;
1681
1682 unsigned x1, x2, y1, y2;
1683 tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
1684
1685 /* The tiling and detiling functions require that the linear buffer has
1686 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1687 * over-allocate the linear buffer to get the proper alignment.
1688 */
1689 map->buffer =
1690 os_malloc_aligned(xfer->layer_stride * box->depth, 16);
1691 assert(map->buffer);
1692 map->ptr = (char *)map->buffer + (x1 & 0xf);
1693
1694 const bool has_swizzling = false;
1695
1696 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1697 char *src =
1698 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1699
1700 for (int s = 0; s < box->depth; s++) {
1701 unsigned x1, x2, y1, y2;
1702 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1703
1704 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1705 void *ptr = map->ptr + s * xfer->layer_stride;
1706
1707 isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
1708 surf->row_pitch_B, has_swizzling,
1709 surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
1710 }
1711 }
1712
1713 map->unmap = iris_unmap_tiled_memcpy;
1714 }
1715
1716 static void
1717 iris_map_direct(struct iris_transfer *map)
1718 {
1719 struct pipe_transfer *xfer = &map->base;
1720 struct pipe_box *box = &xfer->box;
1721 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1722
1723 void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
1724
1725 if (res->base.target == PIPE_BUFFER) {
1726 xfer->stride = 0;
1727 xfer->layer_stride = 0;
1728
1729 map->ptr = ptr + box->x;
1730 } else {
1731 struct isl_surf *surf = &res->surf;
1732 const struct isl_format_layout *fmtl =
1733 isl_format_get_layout(surf->format);
1734 const unsigned cpp = fmtl->bpb / 8;
1735 unsigned x0_el, y0_el;
1736
1737 get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
1738
1739 xfer->stride = isl_surf_get_row_pitch_B(surf);
1740 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1741
1742 map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
1743 }
1744 }
1745
1746 static bool
1747 can_promote_to_async(const struct iris_resource *res,
1748 const struct pipe_box *box,
1749 enum pipe_transfer_usage usage)
1750 {
1751 /* If we're writing to a section of the buffer that hasn't even been
1752 * initialized with useful data, then we can safely promote this write
1753 * to be unsynchronized. This helps the common pattern of appending data.
1754 */
1755 return res->base.target == PIPE_BUFFER && (usage & PIPE_TRANSFER_WRITE) &&
1756 !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
1757 !util_ranges_intersect(&res->valid_buffer_range, box->x,
1758 box->x + box->width);
1759 }
1760
1761 static void *
1762 iris_transfer_map(struct pipe_context *ctx,
1763 struct pipe_resource *resource,
1764 unsigned level,
1765 enum pipe_transfer_usage usage,
1766 const struct pipe_box *box,
1767 struct pipe_transfer **ptransfer)
1768 {
1769 struct iris_context *ice = (struct iris_context *)ctx;
1770 struct iris_resource *res = (struct iris_resource *)resource;
1771 struct isl_surf *surf = &res->surf;
1772
1773 if (iris_resource_unfinished_aux_import(res))
1774 iris_resource_finish_aux_import(ctx->screen, res);
1775
1776 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
1777 /* Replace the backing storage with a fresh buffer for non-async maps */
1778 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
1779 TC_TRANSFER_MAP_NO_INVALIDATE)))
1780 iris_invalidate_resource(ctx, resource);
1781
1782 /* If we can discard the whole resource, we can discard the range. */
1783 usage |= PIPE_TRANSFER_DISCARD_RANGE;
1784 }
1785
1786 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
1787 can_promote_to_async(res, box, usage)) {
1788 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1789 }
1790
1791 bool need_resolve = false;
1792
1793 if (resource->target != PIPE_BUFFER) {
1794 bool need_hiz_resolve = iris_resource_level_has_hiz(res, level);
1795 bool need_stencil_resolve = res->aux.usage == ISL_AUX_USAGE_STC_CCS;
1796
1797 bool need_color_resolve =
1798 (res->aux.usage == ISL_AUX_USAGE_CCS_D ||
1799 res->aux.usage == ISL_AUX_USAGE_CCS_E ||
1800 res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) &&
1801 iris_has_invalid_primary(res, level, 1, box->z, box->depth);
1802
1803 need_resolve = need_color_resolve ||
1804 need_hiz_resolve ||
1805 need_stencil_resolve;
1806 }
1807
1808 bool map_would_stall = false;
1809
1810 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1811 map_would_stall = need_resolve || resource_is_busy(ice, res);
1812
1813 if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
1814 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1815 return NULL;
1816 }
1817
1818 if (surf->tiling != ISL_TILING_LINEAR &&
1819 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1820 return NULL;
1821
1822 struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
1823 struct pipe_transfer *xfer = &map->base;
1824
1825 if (!map)
1826 return NULL;
1827
1828 memset(map, 0, sizeof(*map));
1829 map->dbg = &ice->dbg;
1830
1831 pipe_resource_reference(&xfer->resource, resource);
1832 xfer->level = level;
1833 xfer->usage = usage;
1834 xfer->box = *box;
1835 *ptransfer = xfer;
1836
1837 map->dest_had_defined_contents =
1838 util_ranges_intersect(&res->valid_buffer_range, box->x,
1839 box->x + box->width);
1840
1841 if (usage & PIPE_TRANSFER_WRITE)
1842 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1843
1844 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1845 * there is to access them simultaneously on the CPU & GPU. This also
1846 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1847 * contain state we're constructing for a GPU draw call, which would
1848 * kill us with infinite stack recursion.
1849 */
1850 bool no_gpu = usage & (PIPE_TRANSFER_PERSISTENT |
1851 PIPE_TRANSFER_COHERENT |
1852 PIPE_TRANSFER_MAP_DIRECTLY);
1853
1854 /* GPU copies are not useful for buffer reads. Instead of stalling to
1855 * read from the original buffer, we'd simply copy it to a temporary...
1856 * then stall (a bit longer) to read from that buffer.
1857 *
1858 * Images are less clear-cut. Resolves can be destructive, removing some
1859 * of the underlying compression, so we'd rather blit the data to a linear
1860 * temporary and map that, to avoid the resolve. (It might be better to
1861 * a tiled temporary and use the tiled_memcpy paths...)
1862 */
1863 if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) &&
1864 !iris_has_invalid_primary(res, level, 1, box->z, box->depth)) {
1865 no_gpu = true;
1866 }
1867
1868 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1869 if (fmtl->txc == ISL_TXC_ASTC)
1870 no_gpu = true;
1871
1872 if (!map_would_stall &&
1873 res->aux.usage != ISL_AUX_USAGE_CCS_E &&
1874 res->aux.usage != ISL_AUX_USAGE_GEN12_CCS_E) {
1875 no_gpu = true;
1876 }
1877
1878 if (!no_gpu) {
1879 /* If we need a synchronous mapping and the resource is busy, or needs
1880 * resolving, we copy to/from a linear temporary buffer using the GPU.
1881 */
1882 map->batch = &ice->batches[IRIS_BATCH_RENDER];
1883 map->blorp = &ice->blorp;
1884 iris_map_copy_region(map);
1885 } else {
1886 /* Otherwise we're free to map on the CPU. */
1887
1888 if (need_resolve) {
1889 iris_resource_access_raw(ice, res, level, box->z, box->depth,
1890 usage & PIPE_TRANSFER_WRITE);
1891 }
1892
1893 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1894 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1895 if (iris_batch_references(&ice->batches[i], res->bo))
1896 iris_batch_flush(&ice->batches[i]);
1897 }
1898 }
1899
1900 if (surf->tiling == ISL_TILING_W) {
1901 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1902 iris_map_s8(map);
1903 } else if (surf->tiling != ISL_TILING_LINEAR) {
1904 iris_map_tiled_memcpy(map);
1905 } else {
1906 iris_map_direct(map);
1907 }
1908 }
1909
1910 return map->ptr;
1911 }
1912
1913 static void
1914 iris_transfer_flush_region(struct pipe_context *ctx,
1915 struct pipe_transfer *xfer,
1916 const struct pipe_box *box)
1917 {
1918 struct iris_context *ice = (struct iris_context *)ctx;
1919 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1920 struct iris_transfer *map = (void *) xfer;
1921
1922 if (map->staging)
1923 iris_flush_staging_region(xfer, box);
1924
1925 uint32_t history_flush = 0;
1926
1927 if (res->base.target == PIPE_BUFFER) {
1928 if (map->staging)
1929 history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
1930
1931 if (map->dest_had_defined_contents)
1932 history_flush |= iris_flush_bits_for_history(res);
1933
1934 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1935 }
1936
1937 if (history_flush & ~PIPE_CONTROL_CS_STALL) {
1938 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1939 struct iris_batch *batch = &ice->batches[i];
1940 if (batch->contains_draw || batch->cache.render->entries) {
1941 iris_batch_maybe_flush(batch, 24);
1942 iris_emit_pipe_control_flush(batch,
1943 "cache history: transfer flush",
1944 history_flush);
1945 }
1946 }
1947 }
1948
1949 /* Make sure we flag constants dirty even if there's no need to emit
1950 * any PIPE_CONTROLs to a batch.
1951 */
1952 iris_dirty_for_history(ice, res);
1953 }
1954
1955 static void
1956 iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
1957 {
1958 struct iris_context *ice = (struct iris_context *)ctx;
1959 struct iris_transfer *map = (void *) xfer;
1960
1961 if (!(xfer->usage & (PIPE_TRANSFER_FLUSH_EXPLICIT |
1962 PIPE_TRANSFER_COHERENT))) {
1963 struct pipe_box flush_box = {
1964 .x = 0, .y = 0, .z = 0,
1965 .width = xfer->box.width,
1966 .height = xfer->box.height,
1967 .depth = xfer->box.depth,
1968 };
1969 iris_transfer_flush_region(ctx, xfer, &flush_box);
1970 }
1971
1972 if (map->unmap)
1973 map->unmap(map);
1974
1975 pipe_resource_reference(&xfer->resource, NULL);
1976 slab_free(&ice->transfer_pool, map);
1977 }
1978
1979 /**
1980 * The pipe->texture_subdata() driver hook.
1981 *
1982 * Mesa's state tracker takes this path whenever possible, even with
1983 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
1984 */
1985 static void
1986 iris_texture_subdata(struct pipe_context *ctx,
1987 struct pipe_resource *resource,
1988 unsigned level,
1989 unsigned usage,
1990 const struct pipe_box *box,
1991 const void *data,
1992 unsigned stride,
1993 unsigned layer_stride)
1994 {
1995 struct iris_context *ice = (struct iris_context *)ctx;
1996 struct iris_resource *res = (struct iris_resource *)resource;
1997 const struct isl_surf *surf = &res->surf;
1998
1999 assert(resource->target != PIPE_BUFFER);
2000
2001 if (iris_resource_unfinished_aux_import(res))
2002 iris_resource_finish_aux_import(ctx->screen, res);
2003
2004 /* Just use the transfer-based path for linear buffers - it will already
2005 * do a direct mapping, or a simple linear staging buffer.
2006 *
2007 * Linear staging buffers appear to be better than tiled ones, too, so
2008 * take that path if we need the GPU to perform color compression, or
2009 * stall-avoidance blits.
2010 */
2011 if (surf->tiling == ISL_TILING_LINEAR ||
2012 (isl_aux_usage_has_ccs(res->aux.usage) &&
2013 res->aux.usage != ISL_AUX_USAGE_CCS_D) ||
2014 resource_is_busy(ice, res)) {
2015 return u_default_texture_subdata(ctx, resource, level, usage, box,
2016 data, stride, layer_stride);
2017 }
2018
2019 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2020
2021 iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
2022
2023 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
2024 if (iris_batch_references(&ice->batches[i], res->bo))
2025 iris_batch_flush(&ice->batches[i]);
2026 }
2027
2028 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
2029
2030 for (int s = 0; s < box->depth; s++) {
2031 const uint8_t *src = data + s * layer_stride;
2032
2033 if (surf->tiling == ISL_TILING_W) {
2034 unsigned x0_el, y0_el;
2035 get_image_offset_el(surf, level, box->z + s, &x0_el, &y0_el);
2036
2037 for (unsigned y = 0; y < box->height; y++) {
2038 for (unsigned x = 0; x < box->width; x++) {
2039 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
2040 x0_el + box->x + x,
2041 y0_el + box->y + y);
2042 dst[offset] = src[y * stride + x];
2043 }
2044 }
2045 } else {
2046 unsigned x1, x2, y1, y2;
2047
2048 tile_extents(surf, box, level, s, &x1, &x2, &y1, &y2);
2049
2050 isl_memcpy_linear_to_tiled(x1, x2, y1, y2,
2051 (void *)dst, (void *)src,
2052 surf->row_pitch_B, stride,
2053 false, surf->tiling, ISL_MEMCPY);
2054 }
2055 }
2056 }
2057
2058 /**
2059 * Mark state dirty that needs to be re-emitted when a resource is written.
2060 */
2061 void
2062 iris_dirty_for_history(struct iris_context *ice,
2063 struct iris_resource *res)
2064 {
2065 uint64_t stage_dirty = 0ull;
2066
2067 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2068 stage_dirty |= ((uint64_t)res->bind_stages)
2069 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS;
2070 }
2071
2072 ice->state.stage_dirty |= stage_dirty;
2073 }
2074
2075 /**
2076 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2077 * resource becomes visible, and any stale read cache data is invalidated.
2078 */
2079 uint32_t
2080 iris_flush_bits_for_history(struct iris_resource *res)
2081 {
2082 uint32_t flush = PIPE_CONTROL_CS_STALL;
2083
2084 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2085 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
2086 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2087 }
2088
2089 if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
2090 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2091
2092 if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
2093 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2094
2095 if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
2096 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
2097
2098 return flush;
2099 }
2100
2101 void
2102 iris_flush_and_dirty_for_history(struct iris_context *ice,
2103 struct iris_batch *batch,
2104 struct iris_resource *res,
2105 uint32_t extra_flags,
2106 const char *reason)
2107 {
2108 if (res->base.target != PIPE_BUFFER)
2109 return;
2110
2111 uint32_t flush = iris_flush_bits_for_history(res) | extra_flags;
2112
2113 iris_emit_pipe_control_flush(batch, reason, flush);
2114
2115 iris_dirty_for_history(ice, res);
2116 }
2117
2118 bool
2119 iris_resource_set_clear_color(struct iris_context *ice,
2120 struct iris_resource *res,
2121 union isl_color_value color)
2122 {
2123 if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
2124 res->aux.clear_color = color;
2125 return true;
2126 }
2127
2128 return false;
2129 }
2130
2131 union isl_color_value
2132 iris_resource_get_clear_color(const struct iris_resource *res,
2133 struct iris_bo **clear_color_bo,
2134 uint64_t *clear_color_offset)
2135 {
2136 assert(res->aux.bo);
2137
2138 if (clear_color_bo)
2139 *clear_color_bo = res->aux.clear_color_bo;
2140 if (clear_color_offset)
2141 *clear_color_offset = res->aux.clear_color_offset;
2142 return res->aux.clear_color;
2143 }
2144
2145 static enum pipe_format
2146 iris_resource_get_internal_format(struct pipe_resource *p_res)
2147 {
2148 struct iris_resource *res = (void *) p_res;
2149 return res->internal_format;
2150 }
2151
2152 static const struct u_transfer_vtbl transfer_vtbl = {
2153 .resource_create = iris_resource_create,
2154 .resource_destroy = iris_resource_destroy,
2155 .transfer_map = iris_transfer_map,
2156 .transfer_unmap = iris_transfer_unmap,
2157 .transfer_flush_region = iris_transfer_flush_region,
2158 .get_internal_format = iris_resource_get_internal_format,
2159 .set_stencil = iris_resource_set_separate_stencil,
2160 .get_stencil = iris_resource_get_separate_stencil,
2161 };
2162
2163 void
2164 iris_init_screen_resource_functions(struct pipe_screen *pscreen)
2165 {
2166 pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
2167 pscreen->resource_create_with_modifiers =
2168 iris_resource_create_with_modifiers;
2169 pscreen->resource_create = u_transfer_helper_resource_create;
2170 pscreen->resource_from_user_memory = iris_resource_from_user_memory;
2171 pscreen->resource_from_handle = iris_resource_from_handle;
2172 pscreen->resource_get_handle = iris_resource_get_handle;
2173 pscreen->resource_get_param = iris_resource_get_param;
2174 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
2175 pscreen->transfer_helper =
2176 u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
2177 }
2178
2179 void
2180 iris_init_resource_functions(struct pipe_context *ctx)
2181 {
2182 ctx->flush_resource = iris_flush_resource;
2183 ctx->invalidate_resource = iris_invalidate_resource;
2184 ctx->transfer_map = u_transfer_helper_transfer_map;
2185 ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
2186 ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
2187 ctx->buffer_subdata = u_default_buffer_subdata;
2188 ctx->texture_subdata = iris_texture_subdata;
2189 }