2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS
,
65 static const uint64_t priority_to_modifier
[] = {
66 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
67 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
68 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
69 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
70 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS
] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
75 modifier_is_supported(const struct gen_device_info
*devinfo
,
76 enum pipe_format pfmt
, uint64_t modifier
)
78 /* Check for basic device support. */
80 case DRM_FORMAT_MOD_LINEAR
:
81 case I915_FORMAT_MOD_X_TILED
:
82 case I915_FORMAT_MOD_Y_TILED
:
84 case I915_FORMAT_MOD_Y_TILED_CCS
:
85 if (devinfo
->gen
<= 8 || devinfo
->gen
>= 12)
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
89 if (devinfo
->gen
!= 12)
92 case DRM_FORMAT_MOD_INVALID
:
97 /* Check remaining requirements. */
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
100 case I915_FORMAT_MOD_Y_TILED_CCS
: {
101 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
104 enum isl_format rt_format
=
105 iris_format_for_usage(devinfo
, pfmt
,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
108 if (rt_format
== ISL_FORMAT_UNSUPPORTED
||
109 !isl_format_supports_ccs_e(devinfo
, rt_format
))
120 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
121 const uint64_t *modifiers
,
124 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
126 for (int i
= 0; i
< count
; i
++) {
127 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
130 switch (modifiers
[i
]) {
131 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
:
132 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_GEN12_RC_CCS
);
134 case I915_FORMAT_MOD_Y_TILED_CCS
:
135 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
137 case I915_FORMAT_MOD_Y_TILED
:
138 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
140 case I915_FORMAT_MOD_X_TILED
:
141 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
143 case DRM_FORMAT_MOD_LINEAR
:
144 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
146 case DRM_FORMAT_MOD_INVALID
:
152 return priority_to_modifier
[prio
];
156 target_to_isl_surf_dim(enum pipe_texture_target target
)
160 case PIPE_TEXTURE_1D
:
161 case PIPE_TEXTURE_1D_ARRAY
:
162 return ISL_SURF_DIM_1D
;
163 case PIPE_TEXTURE_2D
:
164 case PIPE_TEXTURE_CUBE
:
165 case PIPE_TEXTURE_RECT
:
166 case PIPE_TEXTURE_2D_ARRAY
:
167 case PIPE_TEXTURE_CUBE_ARRAY
:
168 return ISL_SURF_DIM_2D
;
169 case PIPE_TEXTURE_3D
:
170 return ISL_SURF_DIM_3D
;
171 case PIPE_MAX_TEXTURE_TYPES
:
174 unreachable("invalid texture type");
178 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
179 enum pipe_format pfmt
,
182 unsigned int *external_only
,
185 struct iris_screen
*screen
= (void *) pscreen
;
186 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
188 uint64_t all_modifiers
[] = {
189 DRM_FORMAT_MOD_LINEAR
,
190 I915_FORMAT_MOD_X_TILED
,
191 I915_FORMAT_MOD_Y_TILED
,
192 I915_FORMAT_MOD_Y_TILED_CCS
,
193 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
,
196 int supported_mods
= 0;
198 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
199 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
202 if (supported_mods
< max
) {
204 modifiers
[supported_mods
] = all_modifiers
[i
];
207 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
213 *count
= supported_mods
;
216 static isl_surf_usage_flags_t
217 pipe_bind_to_isl_usage(unsigned bindings
)
219 isl_surf_usage_flags_t usage
= 0;
221 if (bindings
& PIPE_BIND_RENDER_TARGET
)
222 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
224 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
225 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
227 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
228 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
230 if (bindings
& PIPE_BIND_SCANOUT
)
231 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
237 iris_image_view_get_format(struct iris_context
*ice
,
238 const struct pipe_image_view
*img
)
240 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
241 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
243 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
244 enum isl_format isl_fmt
=
245 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
247 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
248 /* On Gen8, try to use typed surfaces reads (which support a
249 * limited number of formats), and if not possible, fall back
252 if (devinfo
->gen
== 8 &&
253 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
254 return ISL_FORMAT_RAW
;
256 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
262 struct pipe_resource
*
263 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
265 /* For packed depth-stencil, we treat depth as the primary resource
266 * and store S8 as the "second plane" resource.
268 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
276 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
277 struct pipe_resource
*stencil
)
279 assert(util_format_has_depth(util_format_description(p_res
->format
)));
280 pipe_resource_reference(&p_res
->next
, stencil
);
284 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
285 struct iris_resource
**out_z
,
286 struct iris_resource
**out_s
)
294 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
295 *out_z
= (void *) res
;
296 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
299 *out_s
= (void *) res
;
304 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
305 enum isl_tiling tiling
,
306 enum pipe_texture_target target
)
309 case PIPE_TEXTURE_1D
:
310 case PIPE_TEXTURE_1D_ARRAY
:
311 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
312 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
314 case PIPE_TEXTURE_2D
:
315 case PIPE_TEXTURE_2D_ARRAY
:
316 case PIPE_TEXTURE_RECT
:
317 case PIPE_TEXTURE_CUBE
:
318 case PIPE_TEXTURE_CUBE_ARRAY
:
319 return ISL_DIM_LAYOUT_GEN4_2D
;
321 case PIPE_TEXTURE_3D
:
322 return (devinfo
->gen
>= 9 ?
323 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
325 case PIPE_MAX_TEXTURE_TYPES
:
329 unreachable("invalid texture type");
333 iris_resource_disable_aux(struct iris_resource
*res
)
335 iris_bo_unreference(res
->aux
.bo
);
336 iris_bo_unreference(res
->aux
.clear_color_bo
);
337 free(res
->aux
.state
);
339 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
340 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
341 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
342 res
->aux
.has_hiz
= 0;
343 res
->aux
.surf
.size_B
= 0;
345 res
->aux
.extra_aux
.surf
.size_B
= 0;
346 res
->aux
.clear_color_bo
= NULL
;
347 res
->aux
.state
= NULL
;
351 iris_resource_destroy(struct pipe_screen
*screen
,
352 struct pipe_resource
*resource
)
354 struct iris_resource
*res
= (struct iris_resource
*)resource
;
356 if (resource
->target
== PIPE_BUFFER
)
357 util_range_destroy(&res
->valid_buffer_range
);
359 iris_resource_disable_aux(res
);
361 iris_bo_unreference(res
->bo
);
362 iris_pscreen_unref(res
->base
.screen
);
367 static struct iris_resource
*
368 iris_alloc_resource(struct pipe_screen
*pscreen
,
369 const struct pipe_resource
*templ
)
371 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
376 res
->base
.screen
= iris_pscreen_ref(pscreen
);
377 pipe_reference_init(&res
->base
.reference
, 1);
379 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
380 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
382 if (templ
->target
== PIPE_BUFFER
)
383 util_range_init(&res
->valid_buffer_range
);
389 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
391 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
392 return minify(res
->surf
.logical_level0_px
.depth
, level
);
394 return res
->surf
.logical_level0_px
.array_len
;
397 static enum isl_aux_state
**
398 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
400 assert(res
->aux
.state
== NULL
);
402 uint32_t total_slices
= 0;
403 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
404 total_slices
+= iris_get_num_logical_layers(res
, level
);
406 const size_t per_level_array_size
=
407 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
409 /* We're going to allocate a single chunk of data for both the per-level
410 * reference array and the arrays of aux_state. This makes cleanup
411 * significantly easier.
413 const size_t total_size
=
414 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
416 void *data
= malloc(total_size
);
420 enum isl_aux_state
**per_level_arr
= data
;
421 enum isl_aux_state
*s
= data
+ per_level_array_size
;
422 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
423 per_level_arr
[level
] = s
;
424 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
425 for (uint32_t a
= 0; a
< level_layers
; a
++)
428 assert((void *)s
== data
+ total_size
);
430 return per_level_arr
;
434 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
436 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
437 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
441 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
443 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
444 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
445 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
447 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
448 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
449 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
450 res
->aux
.bo
->gtt_offset
+ aux_offset
);
451 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
456 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
457 enum isl_format format
)
459 if (!isl_format_supports_ccs_e(devinfo
, format
))
462 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
464 /* CCS_E seems to significantly hurt performance with 32-bit floating
465 * point formats. For example, Paraview's "Wavelet Volume" case uses
466 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
467 * formats causes a 62% FPS drop.
469 * However, many benchmarks seem to use 16-bit float with no issues.
471 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
478 * Configure aux for the resource, but don't allocate it. For images which
479 * might be shared with modifiers, we must allocate the image and aux data in
482 * Returns false on unexpected error (e.g. allocation failed, or invalid
483 * configuration result).
486 iris_resource_configure_aux(struct iris_screen
*screen
,
487 struct iris_resource
*res
, bool imported
,
488 uint64_t *aux_size_B
,
489 uint32_t *alloc_flags
)
491 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
493 /* Try to create the auxiliary surfaces allowed by the modifier or by
494 * the user if no modifier is specified.
496 assert(!res
->mod_info
||
497 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
498 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
499 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
);
501 const bool has_mcs
= !res
->mod_info
&&
502 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
504 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
505 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
508 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
509 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
510 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
511 &res
->aux
.extra_aux
.surf
, 0);
513 /* Having both HIZ and MCS is impossible. */
514 assert(!has_mcs
|| !has_hiz
);
516 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
517 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
518 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
519 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
520 assert(res
->aux
.surf
.size_B
> 0 &&
521 res
->aux
.surf
.usage
&
522 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
525 if (res
->mod_info
&& has_ccs
) {
526 /* Only allow a CCS modifier if the aux was created successfully. */
527 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
528 } else if (has_mcs
) {
529 res
->aux
.possible_usages
|=
530 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
531 } else if (has_hiz
) {
533 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
534 } else if (res
->surf
.samples
== 1 &&
535 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
536 /* If this resource is single-sampled and will be used as a texture,
537 * put the HiZ surface in write-through mode so that we can sample
540 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
542 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
544 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
545 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
546 } else if (has_ccs
) {
547 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
)) {
548 res
->aux
.possible_usages
|= devinfo
->gen
< 12 ?
549 1 << ISL_AUX_USAGE_CCS_E
: 1 << ISL_AUX_USAGE_GEN12_CCS_E
;
550 } else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
)) {
551 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
555 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
557 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
559 /* We don't always support sampling with hiz. But when we do, it must be
562 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
563 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
565 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
566 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
568 enum isl_aux_state initial_state
;
571 assert(!res
->aux
.bo
);
573 switch (res
->aux
.usage
) {
574 case ISL_AUX_USAGE_NONE
:
575 /* Having no aux buffer is only okay if there's no modifier with aux. */
576 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
577 case ISL_AUX_USAGE_HIZ
:
578 case ISL_AUX_USAGE_HIZ_CCS
:
579 case ISL_AUX_USAGE_HIZ_CCS_WT
:
580 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
582 case ISL_AUX_USAGE_MCS
:
583 case ISL_AUX_USAGE_MCS_CCS
:
584 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
586 * "When MCS buffer is enabled and bound to MSRT, it is required
587 * that it is cleared prior to any rendering."
589 * Since we only use the MCS buffer for rendering, we just clear it
590 * immediately on allocation. The clear value for MCS buffers is all
591 * 1's, so we simply memset it to 0xff.
593 initial_state
= ISL_AUX_STATE_CLEAR
;
595 case ISL_AUX_USAGE_CCS_D
:
596 case ISL_AUX_USAGE_CCS_E
:
597 case ISL_AUX_USAGE_GEN12_CCS_E
:
598 case ISL_AUX_USAGE_STC_CCS
:
599 /* When CCS_E is used, we need to ensure that the CCS starts off in
600 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
603 * "If Software wants to enable Color Compression without Fast
604 * clear, Software needs to initialize MCS with zeros."
606 * A CCS value of 0 indicates that the corresponding block is in the
607 * pass-through state which is what we want.
609 * For CCS_D, do the same thing. On Gen9+, this avoids having any
610 * undefined bits in the aux buffer.
613 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
615 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
617 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
619 *alloc_flags
|= BO_ALLOC_ZEROED
;
621 case ISL_AUX_USAGE_MC
:
623 unreachable("Unsupported aux mode");
626 /* Create the aux_state for the auxiliary buffer. */
627 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
631 /* Increase the aux offset if the main and aux surfaces will share a BO. */
633 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
634 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
635 uint64_t size
= res
->aux
.surf
.size_B
;
637 /* Allocate space in the buffer for storing the CCS. */
638 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
639 const uint64_t padded_aux_size
=
640 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
641 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
642 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
645 /* Allocate space in the buffer for storing the clear color. On modern
646 * platforms (gen > 9), we can read it directly from such buffer.
648 * On gen <= 9, we are going to store the clear color on the buffer
649 * anyways, and copy it back to the surface state during state emission.
651 * Also add some padding to make sure the fast clear color state buffer
652 * starts at a 4K alignment. We believe that 256B might be enough, but due
653 * to lack of testing we will leave this as 4K for now.
655 size
= ALIGN(size
, 4096);
656 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
657 size
+= iris_get_aux_clear_color_state_size(screen
);
660 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
661 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
662 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
663 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
665 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
666 * For LOD == 0, we can grow the dimensions to make it work.
668 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
669 res
->aux
.has_hiz
|= 1 << level
;
677 * Initialize the aux buffer contents.
679 * Returns false on unexpected error (e.g. mapping a BO failed).
682 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
683 unsigned clear_color_state_size
)
685 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
686 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
691 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
692 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
693 memset((char*)map
+ res
->aux
.offset
, memset_value
,
694 res
->aux
.surf
.size_B
);
697 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
698 0, res
->aux
.extra_aux
.surf
.size_B
);
700 /* Zero the indirect clear color to match ::fast_clear_color. */
701 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
702 clear_color_state_size
);
704 iris_bo_unmap(res
->aux
.bo
);
707 if (clear_color_state_size
> 0) {
708 res
->aux
.clear_color_bo
= res
->aux
.bo
;
709 iris_bo_reference(res
->aux
.clear_color_bo
);
716 * Allocate the initial aux surface for a resource based on aux.usage
718 * Returns false on unexpected error (e.g. allocation failed, or invalid
719 * configuration result).
722 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
723 struct iris_resource
*res
)
725 uint32_t alloc_flags
;
727 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
733 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
734 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
735 * of bytes instead of trying to recalculate based on different format
738 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
740 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
741 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
746 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
747 iris_get_aux_clear_color_state_size(screen
)))
750 map_aux_addresses(screen
, res
);
756 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
757 struct iris_resource
*res
)
759 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
760 assert(iris_resource_unfinished_aux_import(res
));
761 assert(!res
->mod_info
->supports_clear_color
);
763 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
764 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
767 assert(res
->bo
== aux_res
->aux
.bo
);
768 iris_bo_reference(aux_res
->aux
.bo
);
769 res
->aux
.bo
= aux_res
->aux
.bo
;
771 res
->aux
.offset
= aux_res
->aux
.offset
;
773 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
774 assert(res
->aux
.clear_color_bo
== NULL
);
775 res
->aux
.clear_color_offset
= 0;
777 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
779 unsigned clear_color_state_size
=
780 iris_get_aux_clear_color_state_size(screen
);
782 if (clear_color_state_size
> 0) {
783 res
->aux
.clear_color_bo
=
784 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
785 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
786 res
->aux
.clear_color_offset
= 0;
789 iris_resource_destroy(&screen
->base
, res
->base
.next
);
790 res
->base
.next
= NULL
;
792 map_aux_addresses(screen
, res
);
795 static struct pipe_resource
*
796 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
797 const struct pipe_resource
*templ
)
799 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
800 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
802 assert(templ
->target
== PIPE_BUFFER
);
803 assert(templ
->height0
<= 1);
804 assert(templ
->depth0
<= 1);
805 assert(templ
->format
== PIPE_FORMAT_NONE
||
806 util_format_get_blocksize(templ
->format
) == 1);
808 res
->internal_format
= templ
->format
;
809 res
->surf
.tiling
= ISL_TILING_LINEAR
;
811 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
812 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
813 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
814 memzone
= IRIS_MEMZONE_SHADER
;
815 name
= "shader kernels";
816 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
817 memzone
= IRIS_MEMZONE_SURFACE
;
818 name
= "surface state";
819 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
820 memzone
= IRIS_MEMZONE_DYNAMIC
;
821 name
= "dynamic state";
824 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
826 iris_resource_destroy(pscreen
, &res
->base
);
830 if (templ
->bind
& PIPE_BIND_SHARED
)
831 iris_bo_make_external(res
->bo
);
836 static struct pipe_resource
*
837 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
838 const struct pipe_resource
*templ
,
839 const uint64_t *modifiers
,
842 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
843 struct gen_device_info
*devinfo
= &screen
->devinfo
;
844 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
849 const struct util_format_description
*format_desc
=
850 util_format_description(templ
->format
);
851 const bool has_depth
= util_format_has_depth(format_desc
);
853 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
855 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
857 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
858 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
860 tiling_flags
= 1 << res
->mod_info
->tiling
;
862 if (modifiers_count
> 0) {
863 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
867 /* Use linear for staging buffers */
868 if (templ
->usage
== PIPE_USAGE_STAGING
||
869 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) ) {
870 tiling_flags
= ISL_TILING_LINEAR_BIT
;
871 } else if (templ
->bind
& PIPE_BIND_SCANOUT
) {
872 if (devinfo
->has_tiling_uapi
)
873 tiling_flags
= ISL_TILING_X_BIT
;
875 tiling_flags
= ISL_TILING_LINEAR_BIT
;
879 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
881 if (templ
->target
== PIPE_TEXTURE_CUBE
||
882 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
883 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
885 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
886 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
887 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
889 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
892 enum pipe_format pfmt
= templ
->format
;
893 res
->internal_format
= pfmt
;
895 /* Should be handled by u_transfer_helper */
896 assert(!util_format_is_depth_and_stencil(pfmt
));
898 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
899 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
901 UNUSED
const bool isl_surf_created_successfully
=
902 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
903 .dim
= target_to_isl_surf_dim(templ
->target
),
905 .width
= templ
->width0
,
906 .height
= templ
->height0
,
907 .depth
= templ
->depth0
,
908 .levels
= templ
->last_level
+ 1,
909 .array_len
= templ
->array_size
,
910 .samples
= MAX2(templ
->nr_samples
, 1),
911 .min_alignment_B
= 0,
914 .tiling_flags
= tiling_flags
);
915 assert(isl_surf_created_successfully
);
917 const char *name
= "miptree";
918 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
920 unsigned int flags
= 0;
921 if (templ
->usage
== PIPE_USAGE_STAGING
)
922 flags
|= BO_ALLOC_COHERENT
;
924 /* These are for u_upload_mgr buffers only */
925 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
926 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
927 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
929 uint32_t aux_preferred_alloc_flags
;
930 uint64_t aux_size
= 0;
931 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
932 &aux_preferred_alloc_flags
)) {
936 /* Modifiers require the aux data to be in the same buffer as the main
937 * surface, but we combine them even when a modifiers is not being used.
939 const uint64_t bo_size
=
940 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
941 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
942 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
944 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
945 res
->surf
.row_pitch_B
, flags
);
951 res
->aux
.bo
= res
->bo
;
952 iris_bo_reference(res
->aux
.bo
);
953 unsigned clear_color_state_size
=
954 iris_get_aux_clear_color_state_size(screen
);
955 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
957 map_aux_addresses(screen
, res
);
960 if (templ
->bind
& PIPE_BIND_SHARED
)
961 iris_bo_make_external(res
->bo
);
966 fprintf(stderr
, "XXX: resource creation failed\n");
967 iris_resource_destroy(pscreen
, &res
->base
);
972 static struct pipe_resource
*
973 iris_resource_create(struct pipe_screen
*pscreen
,
974 const struct pipe_resource
*templ
)
976 if (templ
->target
== PIPE_BUFFER
)
977 return iris_resource_create_for_buffer(pscreen
, templ
);
979 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
983 tiling_to_modifier(uint32_t tiling
)
985 static const uint64_t map
[] = {
986 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
987 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
988 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
991 assert(tiling
< ARRAY_SIZE(map
));
996 static struct pipe_resource
*
997 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
998 const struct pipe_resource
*templ
,
1001 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1002 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1003 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1007 assert(templ
->target
== PIPE_BUFFER
);
1009 res
->internal_format
= templ
->format
;
1010 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
1011 user_memory
, templ
->width0
,
1012 IRIS_MEMZONE_OTHER
);
1014 iris_resource_destroy(pscreen
, &res
->base
);
1018 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
1023 static struct pipe_resource
*
1024 iris_resource_from_handle(struct pipe_screen
*pscreen
,
1025 const struct pipe_resource
*templ
,
1026 struct winsys_handle
*whandle
,
1029 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1030 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1031 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1032 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1033 const struct isl_drm_modifier_info
*mod_inf
=
1034 isl_drm_modifier_get_info(whandle
->modifier
);
1040 switch (whandle
->type
) {
1041 case WINSYS_HANDLE_TYPE_FD
:
1043 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1046 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1047 tiling
, whandle
->stride
);
1049 case WINSYS_HANDLE_TYPE_SHARED
:
1050 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1054 unreachable("invalid winsys handle type");
1059 res
->offset
= whandle
->offset
;
1061 if (mod_inf
== NULL
) {
1063 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1067 res
->external_format
= whandle
->format
;
1068 res
->mod_info
= mod_inf
;
1070 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1072 const struct iris_format_info fmt
=
1073 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1074 res
->internal_format
= templ
->format
;
1076 if (templ
->target
== PIPE_BUFFER
) {
1077 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1079 /* Create a surface for each plane specified by the external format. */
1080 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1081 UNUSED
const bool isl_surf_created_successfully
=
1082 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1083 .dim
= target_to_isl_surf_dim(templ
->target
),
1085 .width
= templ
->width0
,
1086 .height
= templ
->height0
,
1087 .depth
= templ
->depth0
,
1088 .levels
= templ
->last_level
+ 1,
1089 .array_len
= templ
->array_size
,
1090 .samples
= MAX2(templ
->nr_samples
, 1),
1091 .min_alignment_B
= 0,
1092 .row_pitch_B
= whandle
->stride
,
1094 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1095 assert(isl_surf_created_successfully
);
1096 assert(res
->bo
->tiling_mode
==
1097 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1099 // XXX: create_ccs_buf_for_image?
1100 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1101 if (!iris_resource_alloc_separate_aux(screen
, res
))
1104 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1105 uint32_t alloc_flags
;
1107 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1110 /* The gallium dri layer will create a separate plane resource
1111 * for the aux image. iris_resource_finish_aux_import will
1112 * merge the separate aux parameters back into a single
1118 /* Save modifier import information to reconstruct later. After
1119 * import, this will be available under a second image accessible
1120 * from the main image with res->base.next. See
1121 * iris_resource_finish_aux_import.
1123 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1124 res
->aux
.offset
= whandle
->offset
;
1125 res
->aux
.bo
= res
->bo
;
1133 iris_resource_destroy(pscreen
, &res
->base
);
1138 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1140 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1141 struct iris_resource
*res
= (void *) resource
;
1142 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1144 iris_resource_prepare_access(ice
, res
,
1145 0, INTEL_REMAINING_LEVELS
,
1146 0, INTEL_REMAINING_LAYERS
,
1147 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1148 mod
? mod
->supports_clear_color
: false);
1152 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1155 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1157 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1159 /* Disable aux usage if explicit flush not set and this is the first time
1160 * we are dealing with this resource and the resource was not created with
1161 * a modifier with aux.
1163 if (!mod_with_aux
&&
1164 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1165 p_atomic_read(&resource
->reference
.count
) == 1) {
1166 iris_resource_disable_aux(res
);
1171 iris_resource_get_param(struct pipe_screen
*pscreen
,
1172 struct pipe_context
*context
,
1173 struct pipe_resource
*resource
,
1176 enum pipe_resource_param param
,
1177 unsigned handle_usage
,
1180 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1181 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1183 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1184 bool wants_aux
= mod_with_aux
&& plane
> 0;
1188 if (iris_resource_unfinished_aux_import(res
))
1189 iris_resource_finish_aux_import(pscreen
, res
);
1191 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1193 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1196 case PIPE_RESOURCE_PARAM_NPLANES
:
1201 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1206 case PIPE_RESOURCE_PARAM_STRIDE
:
1207 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1209 case PIPE_RESOURCE_PARAM_OFFSET
:
1210 *value
= wants_aux
? res
->aux
.offset
: 0;
1212 case PIPE_RESOURCE_PARAM_MODIFIER
:
1213 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1214 tiling_to_modifier(res
->bo
->tiling_mode
);
1216 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1217 result
= iris_bo_flink(bo
, &handle
) == 0;
1221 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1222 /* Because we share the same drm file across multiple iris_screen, when
1223 * we export a GEM handle we must make sure it is valid in the DRM file
1224 * descriptor the caller is using (this is the FD given at screen
1228 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1234 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1235 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1245 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1246 struct pipe_context
*ctx
,
1247 struct pipe_resource
*resource
,
1248 struct winsys_handle
*whandle
,
1251 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1252 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1254 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1256 iris_resource_disable_aux_on_first_query(resource
, usage
);
1259 if (mod_with_aux
&& whandle
->plane
> 0) {
1260 assert(res
->aux
.bo
);
1262 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1263 whandle
->offset
= res
->aux
.offset
;
1265 /* If this is a buffer, stride should be 0 - no need to special case */
1266 whandle
->stride
= res
->surf
.row_pitch_B
;
1270 whandle
->format
= res
->external_format
;
1272 res
->mod_info
? res
->mod_info
->modifier
1273 : tiling_to_modifier(res
->bo
->tiling_mode
);
1276 enum isl_aux_usage allowed_usage
=
1277 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1279 if (res
->aux
.usage
!= allowed_usage
) {
1280 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1281 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1282 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1286 switch (whandle
->type
) {
1287 case WINSYS_HANDLE_TYPE_SHARED
:
1288 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1289 case WINSYS_HANDLE_TYPE_KMS
: {
1290 /* Because we share the same drm file across multiple iris_screen, when
1291 * we export a GEM handle we must make sure it is valid in the DRM file
1292 * descriptor the caller is using (this is the FD given at screen
1296 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1298 whandle
->handle
= handle
;
1301 case WINSYS_HANDLE_TYPE_FD
:
1302 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1309 resource_is_busy(struct iris_context
*ice
,
1310 struct iris_resource
*res
)
1312 bool busy
= iris_bo_busy(res
->bo
);
1314 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1315 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1321 iris_invalidate_resource(struct pipe_context
*ctx
,
1322 struct pipe_resource
*resource
)
1324 struct iris_screen
*screen
= (void *) ctx
->screen
;
1325 struct iris_context
*ice
= (void *) ctx
;
1326 struct iris_resource
*res
= (void *) resource
;
1328 if (resource
->target
!= PIPE_BUFFER
)
1331 /* If it's already invalidated, don't bother doing anything. */
1332 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1335 if (!resource_is_busy(ice
, res
)) {
1336 /* The resource is idle, so just mark that it contains no data and
1337 * keep using the same underlying buffer object.
1339 util_range_set_empty(&res
->valid_buffer_range
);
1343 /* Otherwise, try and replace the backing storage with a new BO. */
1345 /* We can't reallocate memory we didn't allocate in the first place. */
1346 if (res
->bo
->userptr
)
1349 // XXX: We should support this.
1350 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1353 struct iris_bo
*old_bo
= res
->bo
;
1354 struct iris_bo
*new_bo
=
1355 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1356 iris_memzone_for_address(old_bo
->gtt_offset
));
1360 /* Swap out the backing storage */
1363 /* Rebind the buffer, replacing any state referring to the old BO's
1364 * address, and marking state dirty so it's reemitted.
1366 screen
->vtbl
.rebind_buffer(ice
, res
);
1368 util_range_set_empty(&res
->valid_buffer_range
);
1370 iris_bo_unreference(old_bo
);
1374 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1375 const struct pipe_box
*flush_box
)
1377 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1380 struct iris_transfer
*map
= (void *) xfer
;
1382 struct pipe_box src_box
= *flush_box
;
1384 /* Account for extra alignment padding in staging buffer */
1385 if (xfer
->resource
->target
== PIPE_BUFFER
)
1386 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1388 struct pipe_box dst_box
= (struct pipe_box
) {
1389 .x
= xfer
->box
.x
+ flush_box
->x
,
1390 .y
= xfer
->box
.y
+ flush_box
->y
,
1391 .z
= xfer
->box
.z
+ flush_box
->z
,
1392 .width
= flush_box
->width
,
1393 .height
= flush_box
->height
,
1394 .depth
= flush_box
->depth
,
1397 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1398 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1403 iris_unmap_copy_region(struct iris_transfer
*map
)
1405 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1411 iris_map_copy_region(struct iris_transfer
*map
)
1413 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1414 struct pipe_transfer
*xfer
= &map
->base
;
1415 struct pipe_box
*box
= &xfer
->box
;
1416 struct iris_resource
*res
= (void *) xfer
->resource
;
1418 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1419 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1421 struct pipe_resource templ
= (struct pipe_resource
) {
1422 .usage
= PIPE_USAGE_STAGING
,
1423 .width0
= box
->width
+ extra
,
1424 .height0
= box
->height
,
1426 .nr_samples
= xfer
->resource
->nr_samples
,
1427 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1428 .array_size
= box
->depth
,
1429 .format
= res
->internal_format
,
1432 if (xfer
->resource
->target
== PIPE_BUFFER
)
1433 templ
.target
= PIPE_BUFFER
;
1434 else if (templ
.array_size
> 1)
1435 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1437 templ
.target
= PIPE_TEXTURE_2D
;
1439 map
->staging
= iris_resource_create(pscreen
, &templ
);
1440 assert(map
->staging
);
1442 if (templ
.target
!= PIPE_BUFFER
) {
1443 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1444 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1445 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1448 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1449 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1450 xfer
->resource
, xfer
->level
, box
);
1451 /* Ensure writes to the staging BO land before we map it below. */
1452 iris_emit_pipe_control_flush(map
->batch
,
1453 "transfer read: flush before mapping",
1454 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1455 PIPE_CONTROL_CS_STALL
);
1458 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1460 if (iris_batch_references(map
->batch
, staging_bo
))
1461 iris_batch_flush(map
->batch
);
1464 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1466 map
->unmap
= iris_unmap_copy_region
;
1470 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1471 unsigned *out_x0_el
, unsigned *out_y0_el
)
1473 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1474 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1476 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1481 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1482 * different tiling patterns.
1485 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1486 uint32_t *tile_w
, uint32_t *tile_h
)
1497 case ISL_TILING_LINEAR
:
1502 unreachable("not reached");
1508 * This function computes masks that may be used to select the bits of the X
1509 * and Y coordinates that indicate the offset within a tile. If the BO is
1510 * untiled, the masks are set to 0.
1513 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1514 uint32_t *mask_x
, uint32_t *mask_y
)
1516 uint32_t tile_w_bytes
, tile_h
;
1518 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1520 *mask_x
= tile_w_bytes
/ cpp
- 1;
1521 *mask_y
= tile_h
- 1;
1525 * Compute the offset (in bytes) from the start of the BO to the given x
1526 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1527 * multiples of the tile size.
1530 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1531 uint32_t x
, uint32_t y
)
1533 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1534 unsigned cpp
= fmtl
->bpb
/ 8;
1535 uint32_t pitch
= res
->surf
.row_pitch_B
;
1537 switch (res
->surf
.tiling
) {
1539 unreachable("not reached");
1540 case ISL_TILING_LINEAR
:
1541 return y
* pitch
+ x
* cpp
;
1543 assert((x
% (512 / cpp
)) == 0);
1544 assert((y
% 8) == 0);
1545 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1547 assert((x
% (128 / cpp
)) == 0);
1548 assert((y
% 32) == 0);
1549 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1554 * Rendering with tiled buffers requires that the base address of the buffer
1555 * be aligned to a page boundary. For renderbuffers, and sometimes with
1556 * textures, we may want the surface to point at a texture image level that
1557 * isn't at a page boundary.
1559 * This function returns an appropriately-aligned base offset
1560 * according to the tiling restrictions, plus any required x/y offset
1564 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1565 uint32_t level
, uint32_t z
,
1566 uint32_t *tile_x
, uint32_t *tile_y
)
1569 uint32_t mask_x
, mask_y
;
1571 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1572 const unsigned cpp
= fmtl
->bpb
/ 8;
1574 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1575 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1577 *tile_x
= x
& mask_x
;
1578 *tile_y
= y
& mask_y
;
1580 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1584 * Get pointer offset into stencil buffer.
1586 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1587 * must decode the tile's layout in software.
1590 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1592 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1594 * Even though the returned offset is always positive, the return type is
1596 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1597 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1600 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1602 uint32_t tile_size
= 4096;
1603 uint32_t tile_width
= 64;
1604 uint32_t tile_height
= 64;
1605 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1607 uint32_t tile_x
= x
/ tile_width
;
1608 uint32_t tile_y
= y
/ tile_height
;
1610 /* The byte's address relative to the tile's base addres. */
1611 uint32_t byte_x
= x
% tile_width
;
1612 uint32_t byte_y
= y
% tile_height
;
1614 uintptr_t u
= tile_y
* row_size
1615 + tile_x
* tile_size
1616 + 512 * (byte_x
/ 8)
1618 + 32 * ((byte_y
/ 4) % 2)
1619 + 16 * ((byte_x
/ 4) % 2)
1620 + 8 * ((byte_y
/ 2) % 2)
1621 + 4 * ((byte_x
/ 2) % 2)
1629 iris_unmap_s8(struct iris_transfer
*map
)
1631 struct pipe_transfer
*xfer
= &map
->base
;
1632 const struct pipe_box
*box
= &xfer
->box
;
1633 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1634 struct isl_surf
*surf
= &res
->surf
;
1636 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1637 uint8_t *untiled_s8_map
= map
->ptr
;
1638 uint8_t *tiled_s8_map
=
1639 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1641 for (int s
= 0; s
< box
->depth
; s
++) {
1642 unsigned x0_el
, y0_el
;
1643 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1645 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1646 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1647 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1649 y0_el
+ box
->y
+ y
);
1650 tiled_s8_map
[offset
] =
1651 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1661 iris_map_s8(struct iris_transfer
*map
)
1663 struct pipe_transfer
*xfer
= &map
->base
;
1664 const struct pipe_box
*box
= &xfer
->box
;
1665 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1666 struct isl_surf
*surf
= &res
->surf
;
1668 xfer
->stride
= surf
->row_pitch_B
;
1669 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1671 /* The tiling and detiling functions require that the linear buffer has
1672 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1673 * over-allocate the linear buffer to get the proper alignment.
1675 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1676 assert(map
->buffer
);
1678 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1679 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1680 * invalidate is set, since we'll be writing the whole rectangle from our
1681 * temporary buffer back out.
1683 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1684 uint8_t *untiled_s8_map
= map
->ptr
;
1685 uint8_t *tiled_s8_map
=
1686 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1688 for (int s
= 0; s
< box
->depth
; s
++) {
1689 unsigned x0_el
, y0_el
;
1690 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1692 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1693 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1694 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1696 y0_el
+ box
->y
+ y
);
1697 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1698 tiled_s8_map
[offset
];
1704 map
->unmap
= iris_unmap_s8
;
1707 /* Compute extent parameters for use with tiled_memcpy functions.
1708 * xs are in units of bytes and ys are in units of strides.
1711 tile_extents(const struct isl_surf
*surf
,
1712 const struct pipe_box
*box
,
1713 unsigned level
, int z
,
1714 unsigned *x1_B
, unsigned *x2_B
,
1715 unsigned *y1_el
, unsigned *y2_el
)
1717 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1718 const unsigned cpp
= fmtl
->bpb
/ 8;
1720 assert(box
->x
% fmtl
->bw
== 0);
1721 assert(box
->y
% fmtl
->bh
== 0);
1723 unsigned x0_el
, y0_el
;
1724 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1726 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1727 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1728 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1729 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1733 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1735 struct pipe_transfer
*xfer
= &map
->base
;
1736 const struct pipe_box
*box
= &xfer
->box
;
1737 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1738 struct isl_surf
*surf
= &res
->surf
;
1740 const bool has_swizzling
= false;
1742 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1744 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1746 for (int s
= 0; s
< box
->depth
; s
++) {
1747 unsigned x1
, x2
, y1
, y2
;
1748 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1750 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1752 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1753 surf
->row_pitch_B
, xfer
->stride
,
1754 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1757 os_free_aligned(map
->buffer
);
1758 map
->buffer
= map
->ptr
= NULL
;
1762 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1764 struct pipe_transfer
*xfer
= &map
->base
;
1765 const struct pipe_box
*box
= &xfer
->box
;
1766 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1767 struct isl_surf
*surf
= &res
->surf
;
1769 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1770 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1772 unsigned x1
, x2
, y1
, y2
;
1773 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1775 /* The tiling and detiling functions require that the linear buffer has
1776 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1777 * over-allocate the linear buffer to get the proper alignment.
1780 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1781 assert(map
->buffer
);
1782 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1784 const bool has_swizzling
= false;
1786 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1788 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1790 for (int s
= 0; s
< box
->depth
; s
++) {
1791 unsigned x1
, x2
, y1
, y2
;
1792 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1794 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1795 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1797 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1798 surf
->row_pitch_B
, has_swizzling
,
1799 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1803 map
->unmap
= iris_unmap_tiled_memcpy
;
1807 iris_map_direct(struct iris_transfer
*map
)
1809 struct pipe_transfer
*xfer
= &map
->base
;
1810 struct pipe_box
*box
= &xfer
->box
;
1811 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1813 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1815 if (res
->base
.target
== PIPE_BUFFER
) {
1817 xfer
->layer_stride
= 0;
1819 map
->ptr
= ptr
+ box
->x
;
1821 struct isl_surf
*surf
= &res
->surf
;
1822 const struct isl_format_layout
*fmtl
=
1823 isl_format_get_layout(surf
->format
);
1824 const unsigned cpp
= fmtl
->bpb
/ 8;
1825 unsigned x0_el
, y0_el
;
1827 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1829 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1830 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1832 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1837 can_promote_to_async(const struct iris_resource
*res
,
1838 const struct pipe_box
*box
,
1839 enum pipe_transfer_usage usage
)
1841 /* If we're writing to a section of the buffer that hasn't even been
1842 * initialized with useful data, then we can safely promote this write
1843 * to be unsynchronized. This helps the common pattern of appending data.
1845 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1846 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1847 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1848 box
->x
+ box
->width
);
1852 iris_transfer_map(struct pipe_context
*ctx
,
1853 struct pipe_resource
*resource
,
1855 enum pipe_transfer_usage usage
,
1856 const struct pipe_box
*box
,
1857 struct pipe_transfer
**ptransfer
)
1859 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1860 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1861 struct isl_surf
*surf
= &res
->surf
;
1863 if (iris_resource_unfinished_aux_import(res
))
1864 iris_resource_finish_aux_import(ctx
->screen
, res
);
1866 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1867 /* Replace the backing storage with a fresh buffer for non-async maps */
1868 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1869 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1870 iris_invalidate_resource(ctx
, resource
);
1872 /* If we can discard the whole resource, we can discard the range. */
1873 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1876 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1877 can_promote_to_async(res
, box
, usage
)) {
1878 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1881 bool need_resolve
= false;
1882 bool need_color_resolve
= false;
1884 if (resource
->target
!= PIPE_BUFFER
) {
1885 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1886 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1888 need_color_resolve
=
1889 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1890 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1891 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) &&
1892 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1894 need_resolve
= need_color_resolve
||
1896 need_stencil_resolve
;
1899 bool map_would_stall
= false;
1901 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1902 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1904 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1905 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1909 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1910 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1913 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1914 struct pipe_transfer
*xfer
= &map
->base
;
1919 memset(map
, 0, sizeof(*map
));
1920 map
->dbg
= &ice
->dbg
;
1922 pipe_resource_reference(&xfer
->resource
, resource
);
1923 xfer
->level
= level
;
1924 xfer
->usage
= usage
;
1928 map
->dest_had_defined_contents
=
1929 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1930 box
->x
+ box
->width
);
1932 if (usage
& PIPE_TRANSFER_WRITE
)
1933 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1935 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1936 * there is to access them simultaneously on the CPU & GPU. This also
1937 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1938 * contain state we're constructing for a GPU draw call, which would
1939 * kill us with infinite stack recursion.
1941 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1942 PIPE_TRANSFER_COHERENT
|
1943 PIPE_TRANSFER_MAP_DIRECTLY
);
1945 /* GPU copies are not useful for buffer reads. Instead of stalling to
1946 * read from the original buffer, we'd simply copy it to a temporary...
1947 * then stall (a bit longer) to read from that buffer.
1949 * Images are less clear-cut. Color resolves are destructive, removing
1950 * the underlying compression, so we'd rather blit the data to a linear
1951 * temporary and map that, to avoid the resolve. (It might be better to
1952 * a tiled temporary and use the tiled_memcpy paths...)
1954 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1957 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1958 if (fmtl
->txc
== ISL_TXC_ASTC
)
1961 if ((map_would_stall
||
1962 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1963 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) && !no_gpu
) {
1964 /* If we need a synchronous mapping and the resource is busy, or needs
1965 * resolving, we copy to/from a linear temporary buffer using the GPU.
1967 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1968 map
->blorp
= &ice
->blorp
;
1969 iris_map_copy_region(map
);
1971 /* Otherwise we're free to map on the CPU. */
1974 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1975 usage
& PIPE_TRANSFER_WRITE
);
1978 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1979 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1980 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1981 iris_batch_flush(&ice
->batches
[i
]);
1985 if (surf
->tiling
== ISL_TILING_W
) {
1986 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1988 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1989 iris_map_tiled_memcpy(map
);
1991 iris_map_direct(map
);
1999 iris_transfer_flush_region(struct pipe_context
*ctx
,
2000 struct pipe_transfer
*xfer
,
2001 const struct pipe_box
*box
)
2003 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2004 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
2005 struct iris_transfer
*map
= (void *) xfer
;
2008 iris_flush_staging_region(xfer
, box
);
2010 uint32_t history_flush
= 0;
2012 if (res
->base
.target
== PIPE_BUFFER
) {
2014 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2016 if (map
->dest_had_defined_contents
)
2017 history_flush
|= iris_flush_bits_for_history(res
);
2019 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
2022 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
2023 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2024 struct iris_batch
*batch
= &ice
->batches
[i
];
2025 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
2026 iris_batch_maybe_flush(batch
, 24);
2027 iris_emit_pipe_control_flush(batch
,
2028 "cache history: transfer flush",
2034 /* Make sure we flag constants dirty even if there's no need to emit
2035 * any PIPE_CONTROLs to a batch.
2037 iris_dirty_for_history(ice
, res
);
2041 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
2043 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2044 struct iris_transfer
*map
= (void *) xfer
;
2046 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
2047 PIPE_TRANSFER_COHERENT
))) {
2048 struct pipe_box flush_box
= {
2049 .x
= 0, .y
= 0, .z
= 0,
2050 .width
= xfer
->box
.width
,
2051 .height
= xfer
->box
.height
,
2052 .depth
= xfer
->box
.depth
,
2054 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2060 pipe_resource_reference(&xfer
->resource
, NULL
);
2061 slab_free(&ice
->transfer_pool
, map
);
2065 * The pipe->texture_subdata() driver hook.
2067 * Mesa's state tracker takes this path whenever possible, even with
2068 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2071 iris_texture_subdata(struct pipe_context
*ctx
,
2072 struct pipe_resource
*resource
,
2075 const struct pipe_box
*box
,
2078 unsigned layer_stride
)
2080 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2081 struct iris_resource
*res
= (struct iris_resource
*)resource
;
2082 const struct isl_surf
*surf
= &res
->surf
;
2084 assert(resource
->target
!= PIPE_BUFFER
);
2086 if (iris_resource_unfinished_aux_import(res
))
2087 iris_resource_finish_aux_import(ctx
->screen
, res
);
2089 /* Just use the transfer-based path for linear buffers - it will already
2090 * do a direct mapping, or a simple linear staging buffer.
2092 * Linear staging buffers appear to be better than tiled ones, too, so
2093 * take that path if we need the GPU to perform color compression, or
2094 * stall-avoidance blits.
2096 if (surf
->tiling
== ISL_TILING_LINEAR
||
2097 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
2098 resource_is_busy(ice
, res
)) {
2099 return u_default_texture_subdata(ctx
, resource
, level
, usage
, box
,
2100 data
, stride
, layer_stride
);
2103 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2105 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
, true);
2107 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2108 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
2109 iris_batch_flush(&ice
->batches
[i
]);
2112 uint8_t *dst
= iris_bo_map(&ice
->dbg
, res
->bo
, MAP_WRITE
| MAP_RAW
);
2114 for (int s
= 0; s
< box
->depth
; s
++) {
2115 const uint8_t *src
= data
+ s
* layer_stride
;
2117 if (surf
->tiling
== ISL_TILING_W
) {
2118 unsigned x0_el
, y0_el
;
2119 get_image_offset_el(surf
, level
, box
->z
+ s
, &x0_el
, &y0_el
);
2121 for (unsigned y
= 0; y
< box
->height
; y
++) {
2122 for (unsigned x
= 0; x
< box
->width
; x
++) {
2123 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
2125 y0_el
+ box
->y
+ y
);
2126 dst
[offset
] = src
[y
* stride
+ x
];
2130 unsigned x1
, x2
, y1
, y2
;
2132 tile_extents(surf
, box
, level
, s
, &x1
, &x2
, &y1
, &y2
);
2134 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
,
2135 (void *)dst
, (void *)src
,
2136 surf
->row_pitch_B
, stride
,
2137 false, surf
->tiling
, ISL_MEMCPY
);
2143 * Mark state dirty that needs to be re-emitted when a resource is written.
2146 iris_dirty_for_history(struct iris_context
*ice
,
2147 struct iris_resource
*res
)
2149 uint64_t stage_dirty
= 0ull;
2151 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2152 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2153 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2156 ice
->state
.stage_dirty
|= stage_dirty
;
2160 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2161 * resource becomes visible, and any stale read cache data is invalidated.
2164 iris_flush_bits_for_history(struct iris_resource
*res
)
2166 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2168 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2169 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2170 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2173 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2174 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2176 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2177 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2179 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2180 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2186 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2187 struct iris_batch
*batch
,
2188 struct iris_resource
*res
,
2189 uint32_t extra_flags
,
2192 if (res
->base
.target
!= PIPE_BUFFER
)
2195 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2197 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2199 iris_dirty_for_history(ice
, res
);
2203 iris_resource_set_clear_color(struct iris_context
*ice
,
2204 struct iris_resource
*res
,
2205 union isl_color_value color
)
2207 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2208 res
->aux
.clear_color
= color
;
2215 union isl_color_value
2216 iris_resource_get_clear_color(const struct iris_resource
*res
,
2217 struct iris_bo
**clear_color_bo
,
2218 uint64_t *clear_color_offset
)
2220 assert(res
->aux
.bo
);
2223 *clear_color_bo
= res
->aux
.clear_color_bo
;
2224 if (clear_color_offset
)
2225 *clear_color_offset
= res
->aux
.clear_color_offset
;
2226 return res
->aux
.clear_color
;
2229 static enum pipe_format
2230 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2232 struct iris_resource
*res
= (void *) p_res
;
2233 return res
->internal_format
;
2236 static const struct u_transfer_vtbl transfer_vtbl
= {
2237 .resource_create
= iris_resource_create
,
2238 .resource_destroy
= iris_resource_destroy
,
2239 .transfer_map
= iris_transfer_map
,
2240 .transfer_unmap
= iris_transfer_unmap
,
2241 .transfer_flush_region
= iris_transfer_flush_region
,
2242 .get_internal_format
= iris_resource_get_internal_format
,
2243 .set_stencil
= iris_resource_set_separate_stencil
,
2244 .get_stencil
= iris_resource_get_separate_stencil
,
2248 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2250 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2251 pscreen
->resource_create_with_modifiers
=
2252 iris_resource_create_with_modifiers
;
2253 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2254 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2255 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2256 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2257 pscreen
->resource_get_param
= iris_resource_get_param
;
2258 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2259 pscreen
->transfer_helper
=
2260 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2264 iris_init_resource_functions(struct pipe_context
*ctx
)
2266 ctx
->flush_resource
= iris_flush_resource
;
2267 ctx
->invalidate_resource
= iris_invalidate_resource
;
2268 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2269 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2270 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2271 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2272 ctx
->texture_subdata
= iris_texture_subdata
;