2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* Check for basic device support. */
78 case DRM_FORMAT_MOD_LINEAR
:
79 case I915_FORMAT_MOD_X_TILED
:
80 case I915_FORMAT_MOD_Y_TILED
:
82 case I915_FORMAT_MOD_Y_TILED_CCS
:
83 if (devinfo
->gen
<= 8 || devinfo
->gen
>= 12)
86 case DRM_FORMAT_MOD_INVALID
:
91 /* Check remaining requirements. */
93 case I915_FORMAT_MOD_Y_TILED_CCS
: {
94 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
97 enum isl_format rt_format
=
98 iris_format_for_usage(devinfo
, pfmt
,
99 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
101 if (rt_format
== ISL_FORMAT_UNSUPPORTED
||
102 !isl_format_supports_ccs_e(devinfo
, rt_format
))
113 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
114 const uint64_t *modifiers
,
117 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
119 for (int i
= 0; i
< count
; i
++) {
120 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
123 switch (modifiers
[i
]) {
124 case I915_FORMAT_MOD_Y_TILED_CCS
:
125 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
127 case I915_FORMAT_MOD_Y_TILED
:
128 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
130 case I915_FORMAT_MOD_X_TILED
:
131 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
133 case DRM_FORMAT_MOD_LINEAR
:
134 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
136 case DRM_FORMAT_MOD_INVALID
:
142 return priority_to_modifier
[prio
];
146 target_to_isl_surf_dim(enum pipe_texture_target target
)
150 case PIPE_TEXTURE_1D
:
151 case PIPE_TEXTURE_1D_ARRAY
:
152 return ISL_SURF_DIM_1D
;
153 case PIPE_TEXTURE_2D
:
154 case PIPE_TEXTURE_CUBE
:
155 case PIPE_TEXTURE_RECT
:
156 case PIPE_TEXTURE_2D_ARRAY
:
157 case PIPE_TEXTURE_CUBE_ARRAY
:
158 return ISL_SURF_DIM_2D
;
159 case PIPE_TEXTURE_3D
:
160 return ISL_SURF_DIM_3D
;
161 case PIPE_MAX_TEXTURE_TYPES
:
164 unreachable("invalid texture type");
168 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
169 enum pipe_format pfmt
,
172 unsigned int *external_only
,
175 struct iris_screen
*screen
= (void *) pscreen
;
176 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
178 uint64_t all_modifiers
[] = {
179 DRM_FORMAT_MOD_LINEAR
,
180 I915_FORMAT_MOD_X_TILED
,
181 I915_FORMAT_MOD_Y_TILED
,
182 I915_FORMAT_MOD_Y_TILED_CCS
,
185 int supported_mods
= 0;
187 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
188 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
191 if (supported_mods
< max
) {
193 modifiers
[supported_mods
] = all_modifiers
[i
];
196 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
202 *count
= supported_mods
;
205 static isl_surf_usage_flags_t
206 pipe_bind_to_isl_usage(unsigned bindings
)
208 isl_surf_usage_flags_t usage
= 0;
210 if (bindings
& PIPE_BIND_RENDER_TARGET
)
211 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
213 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
214 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
216 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
217 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
219 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
220 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
226 iris_image_view_get_format(struct iris_context
*ice
,
227 const struct pipe_image_view
*img
)
229 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
230 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
232 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
233 enum isl_format isl_fmt
=
234 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
236 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
237 /* On Gen8, try to use typed surfaces reads (which support a
238 * limited number of formats), and if not possible, fall back
241 if (devinfo
->gen
== 8 &&
242 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
243 return ISL_FORMAT_RAW
;
245 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
251 struct pipe_resource
*
252 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
254 /* For packed depth-stencil, we treat depth as the primary resource
255 * and store S8 as the "second plane" resource.
257 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
265 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
266 struct pipe_resource
*stencil
)
268 assert(util_format_has_depth(util_format_description(p_res
->format
)));
269 pipe_resource_reference(&p_res
->next
, stencil
);
273 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
274 struct iris_resource
**out_z
,
275 struct iris_resource
**out_s
)
283 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
284 *out_z
= (void *) res
;
285 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
288 *out_s
= (void *) res
;
293 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
294 enum isl_tiling tiling
,
295 enum pipe_texture_target target
)
298 case PIPE_TEXTURE_1D
:
299 case PIPE_TEXTURE_1D_ARRAY
:
300 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
301 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
303 case PIPE_TEXTURE_2D
:
304 case PIPE_TEXTURE_2D_ARRAY
:
305 case PIPE_TEXTURE_RECT
:
306 case PIPE_TEXTURE_CUBE
:
307 case PIPE_TEXTURE_CUBE_ARRAY
:
308 return ISL_DIM_LAYOUT_GEN4_2D
;
310 case PIPE_TEXTURE_3D
:
311 return (devinfo
->gen
>= 9 ?
312 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
314 case PIPE_MAX_TEXTURE_TYPES
:
318 unreachable("invalid texture type");
322 iris_resource_disable_aux(struct iris_resource
*res
)
324 iris_bo_unreference(res
->aux
.bo
);
325 iris_bo_unreference(res
->aux
.clear_color_bo
);
326 free(res
->aux
.state
);
328 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
329 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
330 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
331 res
->aux
.has_hiz
= 0;
332 res
->aux
.surf
.size_B
= 0;
334 res
->aux
.extra_aux
.surf
.size_B
= 0;
335 res
->aux
.clear_color_bo
= NULL
;
336 res
->aux
.state
= NULL
;
340 iris_resource_destroy(struct pipe_screen
*screen
,
341 struct pipe_resource
*resource
)
343 struct iris_resource
*res
= (struct iris_resource
*)resource
;
345 if (resource
->target
== PIPE_BUFFER
)
346 util_range_destroy(&res
->valid_buffer_range
);
348 iris_resource_disable_aux(res
);
350 iris_bo_unreference(res
->bo
);
351 iris_pscreen_unref(res
->base
.screen
);
356 static struct iris_resource
*
357 iris_alloc_resource(struct pipe_screen
*pscreen
,
358 const struct pipe_resource
*templ
)
360 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
365 res
->base
.screen
= iris_pscreen_ref(pscreen
);
366 pipe_reference_init(&res
->base
.reference
, 1);
368 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
369 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
371 if (templ
->target
== PIPE_BUFFER
)
372 util_range_init(&res
->valid_buffer_range
);
378 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
380 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
381 return minify(res
->surf
.logical_level0_px
.depth
, level
);
383 return res
->surf
.logical_level0_px
.array_len
;
386 static enum isl_aux_state
**
387 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
389 assert(res
->aux
.state
== NULL
);
391 uint32_t total_slices
= 0;
392 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
393 total_slices
+= iris_get_num_logical_layers(res
, level
);
395 const size_t per_level_array_size
=
396 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
398 /* We're going to allocate a single chunk of data for both the per-level
399 * reference array and the arrays of aux_state. This makes cleanup
400 * significantly easier.
402 const size_t total_size
=
403 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
405 void *data
= malloc(total_size
);
409 enum isl_aux_state
**per_level_arr
= data
;
410 enum isl_aux_state
*s
= data
+ per_level_array_size
;
411 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
412 per_level_arr
[level
] = s
;
413 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
414 for (uint32_t a
= 0; a
< level_layers
; a
++)
417 assert((void *)s
== data
+ total_size
);
419 return per_level_arr
;
423 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
425 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
426 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
430 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
432 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
433 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
434 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
436 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
437 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
438 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
439 res
->aux
.bo
->gtt_offset
+ aux_offset
);
440 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
445 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
446 enum isl_format format
)
448 if (!isl_format_supports_ccs_e(devinfo
, format
))
451 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
453 /* CCS_E seems to significantly hurt performance with 32-bit floating
454 * point formats. For example, Paraview's "Wavelet Volume" case uses
455 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
456 * formats causes a 62% FPS drop.
458 * However, many benchmarks seem to use 16-bit float with no issues.
460 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
467 * Configure aux for the resource, but don't allocate it. For images which
468 * might be shared with modifiers, we must allocate the image and aux data in
471 * Returns false on unexpected error (e.g. allocation failed, or invalid
472 * configuration result).
475 iris_resource_configure_aux(struct iris_screen
*screen
,
476 struct iris_resource
*res
, bool imported
,
477 uint64_t *aux_size_B
,
478 uint32_t *alloc_flags
)
480 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
482 /* Try to create the auxiliary surfaces allowed by the modifier or by
483 * the user if no modifier is specified.
485 assert(!res
->mod_info
||
486 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
487 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
488 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
);
490 const bool has_mcs
= !res
->mod_info
&&
491 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
493 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
494 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
497 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
498 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
499 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
500 &res
->aux
.extra_aux
.surf
, 0);
502 /* Having both HIZ and MCS is impossible. */
503 assert(!has_mcs
|| !has_hiz
);
505 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
506 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
507 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
508 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
509 assert(res
->aux
.surf
.size_B
> 0 &&
510 res
->aux
.surf
.usage
&
511 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
514 if (res
->mod_info
&& has_ccs
) {
515 /* Only allow a CCS modifier if the aux was created successfully. */
516 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
517 } else if (has_mcs
) {
518 res
->aux
.possible_usages
|=
519 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
520 } else if (has_hiz
) {
522 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
523 } else if (res
->surf
.samples
== 1 &&
524 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
525 /* If this resource is single-sampled and will be used as a texture,
526 * put the HiZ surface in write-through mode so that we can sample
529 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
531 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
533 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
534 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
535 } else if (has_ccs
) {
536 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
)) {
537 res
->aux
.possible_usages
|= devinfo
->gen
< 12 ?
538 1 << ISL_AUX_USAGE_CCS_E
: 1 << ISL_AUX_USAGE_GEN12_CCS_E
;
539 } else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
)) {
540 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
544 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
546 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
548 /* We don't always support sampling with hiz. But when we do, it must be
551 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
552 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
554 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
555 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
557 enum isl_aux_state initial_state
;
560 assert(!res
->aux
.bo
);
562 switch (res
->aux
.usage
) {
563 case ISL_AUX_USAGE_NONE
:
564 /* Having no aux buffer is only okay if there's no modifier with aux. */
565 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
566 case ISL_AUX_USAGE_HIZ
:
567 case ISL_AUX_USAGE_HIZ_CCS
:
568 case ISL_AUX_USAGE_HIZ_CCS_WT
:
569 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
571 case ISL_AUX_USAGE_MCS
:
572 case ISL_AUX_USAGE_MCS_CCS
:
573 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
575 * "When MCS buffer is enabled and bound to MSRT, it is required
576 * that it is cleared prior to any rendering."
578 * Since we only use the MCS buffer for rendering, we just clear it
579 * immediately on allocation. The clear value for MCS buffers is all
580 * 1's, so we simply memset it to 0xff.
582 initial_state
= ISL_AUX_STATE_CLEAR
;
584 case ISL_AUX_USAGE_CCS_D
:
585 case ISL_AUX_USAGE_CCS_E
:
586 case ISL_AUX_USAGE_GEN12_CCS_E
:
587 case ISL_AUX_USAGE_STC_CCS
:
588 /* When CCS_E is used, we need to ensure that the CCS starts off in
589 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
592 * "If Software wants to enable Color Compression without Fast
593 * clear, Software needs to initialize MCS with zeros."
595 * A CCS value of 0 indicates that the corresponding block is in the
596 * pass-through state which is what we want.
598 * For CCS_D, do the same thing. On Gen9+, this avoids having any
599 * undefined bits in the aux buffer.
602 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
604 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
606 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
608 *alloc_flags
|= BO_ALLOC_ZEROED
;
610 case ISL_AUX_USAGE_MC
:
611 unreachable("Unsupported aux mode");
614 /* Create the aux_state for the auxiliary buffer. */
615 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
619 /* Increase the aux offset if the main and aux surfaces will share a BO. */
621 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
622 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
623 uint64_t size
= res
->aux
.surf
.size_B
;
625 /* Allocate space in the buffer for storing the CCS. */
626 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
627 const uint64_t padded_aux_size
=
628 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
629 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
630 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
633 /* Allocate space in the buffer for storing the clear color. On modern
634 * platforms (gen > 9), we can read it directly from such buffer.
636 * On gen <= 9, we are going to store the clear color on the buffer
637 * anyways, and copy it back to the surface state during state emission.
639 * Also add some padding to make sure the fast clear color state buffer
640 * starts at a 4K alignment. We believe that 256B might be enough, but due
641 * to lack of testing we will leave this as 4K for now.
643 size
= ALIGN(size
, 4096);
644 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
645 size
+= iris_get_aux_clear_color_state_size(screen
);
648 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
649 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
650 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
651 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
653 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
654 * For LOD == 0, we can grow the dimensions to make it work.
656 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
657 res
->aux
.has_hiz
|= 1 << level
;
665 * Initialize the aux buffer contents.
667 * Returns false on unexpected error (e.g. mapping a BO failed).
670 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
671 unsigned clear_color_state_size
)
673 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
674 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
679 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
680 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
681 memset((char*)map
+ res
->aux
.offset
, memset_value
,
682 res
->aux
.surf
.size_B
);
685 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
686 0, res
->aux
.extra_aux
.surf
.size_B
);
688 /* Zero the indirect clear color to match ::fast_clear_color. */
689 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
690 clear_color_state_size
);
692 iris_bo_unmap(res
->aux
.bo
);
695 if (clear_color_state_size
> 0) {
696 res
->aux
.clear_color_bo
= res
->aux
.bo
;
697 iris_bo_reference(res
->aux
.clear_color_bo
);
704 * Allocate the initial aux surface for a resource based on aux.usage
706 * Returns false on unexpected error (e.g. allocation failed, or invalid
707 * configuration result).
710 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
711 struct iris_resource
*res
)
713 uint32_t alloc_flags
;
715 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
721 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
722 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
723 * of bytes instead of trying to recalculate based on different format
726 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
728 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
729 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
734 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
735 iris_get_aux_clear_color_state_size(screen
)))
738 map_aux_addresses(screen
, res
);
744 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
745 struct iris_resource
*res
)
747 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
748 assert(iris_resource_unfinished_aux_import(res
));
749 assert(!res
->mod_info
->supports_clear_color
);
751 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
752 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
755 assert(res
->bo
== aux_res
->aux
.bo
);
756 iris_bo_reference(aux_res
->aux
.bo
);
757 res
->aux
.bo
= aux_res
->aux
.bo
;
759 res
->aux
.offset
= aux_res
->aux
.offset
;
761 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
762 assert(res
->aux
.clear_color_bo
== NULL
);
763 res
->aux
.clear_color_offset
= 0;
765 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
767 unsigned clear_color_state_size
=
768 iris_get_aux_clear_color_state_size(screen
);
770 if (clear_color_state_size
> 0) {
771 res
->aux
.clear_color_bo
=
772 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
773 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
774 res
->aux
.clear_color_offset
= 0;
777 iris_resource_destroy(&screen
->base
, res
->base
.next
);
778 res
->base
.next
= NULL
;
780 map_aux_addresses(screen
, res
);
783 static struct pipe_resource
*
784 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
785 const struct pipe_resource
*templ
)
787 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
788 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
790 assert(templ
->target
== PIPE_BUFFER
);
791 assert(templ
->height0
<= 1);
792 assert(templ
->depth0
<= 1);
793 assert(templ
->format
== PIPE_FORMAT_NONE
||
794 util_format_get_blocksize(templ
->format
) == 1);
796 res
->internal_format
= templ
->format
;
797 res
->surf
.tiling
= ISL_TILING_LINEAR
;
799 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
800 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
801 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
802 memzone
= IRIS_MEMZONE_SHADER
;
803 name
= "shader kernels";
804 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
805 memzone
= IRIS_MEMZONE_SURFACE
;
806 name
= "surface state";
807 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
808 memzone
= IRIS_MEMZONE_DYNAMIC
;
809 name
= "dynamic state";
812 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
814 iris_resource_destroy(pscreen
, &res
->base
);
818 if (templ
->bind
& PIPE_BIND_SHARED
)
819 iris_bo_make_external(res
->bo
);
824 static struct pipe_resource
*
825 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
826 const struct pipe_resource
*templ
,
827 const uint64_t *modifiers
,
830 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
831 struct gen_device_info
*devinfo
= &screen
->devinfo
;
832 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
837 const struct util_format_description
*format_desc
=
838 util_format_description(templ
->format
);
839 const bool has_depth
= util_format_has_depth(format_desc
);
841 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
843 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
845 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
846 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
848 tiling_flags
= 1 << res
->mod_info
->tiling
;
850 if (modifiers_count
> 0) {
851 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
855 /* Use linear for staging buffers */
856 if (templ
->usage
== PIPE_USAGE_STAGING
||
857 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
858 tiling_flags
= ISL_TILING_LINEAR_BIT
;
859 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
860 tiling_flags
= ISL_TILING_X_BIT
;
863 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
865 if (templ
->target
== PIPE_TEXTURE_CUBE
||
866 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
867 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
869 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
870 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
871 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
873 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
876 enum pipe_format pfmt
= templ
->format
;
877 res
->internal_format
= pfmt
;
879 /* Should be handled by u_transfer_helper */
880 assert(!util_format_is_depth_and_stencil(pfmt
));
882 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
883 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
885 UNUSED
const bool isl_surf_created_successfully
=
886 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
887 .dim
= target_to_isl_surf_dim(templ
->target
),
889 .width
= templ
->width0
,
890 .height
= templ
->height0
,
891 .depth
= templ
->depth0
,
892 .levels
= templ
->last_level
+ 1,
893 .array_len
= templ
->array_size
,
894 .samples
= MAX2(templ
->nr_samples
, 1),
895 .min_alignment_B
= 0,
898 .tiling_flags
= tiling_flags
);
899 assert(isl_surf_created_successfully
);
901 const char *name
= "miptree";
902 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
904 unsigned int flags
= 0;
905 if (templ
->usage
== PIPE_USAGE_STAGING
)
906 flags
|= BO_ALLOC_COHERENT
;
908 /* These are for u_upload_mgr buffers only */
909 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
910 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
911 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
913 uint32_t aux_preferred_alloc_flags
;
914 uint64_t aux_size
= 0;
915 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
916 &aux_preferred_alloc_flags
)) {
920 /* Modifiers require the aux data to be in the same buffer as the main
921 * surface, but we combine them even when a modifiers is not being used.
923 const uint64_t bo_size
=
924 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
925 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
926 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
928 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
929 res
->surf
.row_pitch_B
, flags
);
935 res
->aux
.bo
= res
->bo
;
936 iris_bo_reference(res
->aux
.bo
);
937 unsigned clear_color_state_size
=
938 iris_get_aux_clear_color_state_size(screen
);
939 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
941 map_aux_addresses(screen
, res
);
944 if (templ
->bind
& PIPE_BIND_SHARED
)
945 iris_bo_make_external(res
->bo
);
950 fprintf(stderr
, "XXX: resource creation failed\n");
951 iris_resource_destroy(pscreen
, &res
->base
);
956 static struct pipe_resource
*
957 iris_resource_create(struct pipe_screen
*pscreen
,
958 const struct pipe_resource
*templ
)
960 if (templ
->target
== PIPE_BUFFER
)
961 return iris_resource_create_for_buffer(pscreen
, templ
);
963 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
967 tiling_to_modifier(uint32_t tiling
)
969 static const uint64_t map
[] = {
970 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
971 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
972 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
975 assert(tiling
< ARRAY_SIZE(map
));
980 static struct pipe_resource
*
981 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
982 const struct pipe_resource
*templ
,
985 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
986 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
987 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
991 assert(templ
->target
== PIPE_BUFFER
);
993 res
->internal_format
= templ
->format
;
994 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
995 user_memory
, templ
->width0
,
998 iris_resource_destroy(pscreen
, &res
->base
);
1002 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
1007 static struct pipe_resource
*
1008 iris_resource_from_handle(struct pipe_screen
*pscreen
,
1009 const struct pipe_resource
*templ
,
1010 struct winsys_handle
*whandle
,
1013 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1014 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1015 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1016 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1017 const struct isl_drm_modifier_info
*mod_inf
=
1018 isl_drm_modifier_get_info(whandle
->modifier
);
1024 switch (whandle
->type
) {
1025 case WINSYS_HANDLE_TYPE_FD
:
1027 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1029 tiling
= I915_TILING_LAST
+ 1;
1030 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1031 tiling
, whandle
->stride
);
1033 case WINSYS_HANDLE_TYPE_SHARED
:
1034 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1038 unreachable("invalid winsys handle type");
1043 res
->offset
= whandle
->offset
;
1045 if (mod_inf
== NULL
) {
1047 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1051 res
->external_format
= whandle
->format
;
1052 res
->mod_info
= mod_inf
;
1054 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1056 const struct iris_format_info fmt
=
1057 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1058 res
->internal_format
= templ
->format
;
1060 if (templ
->target
== PIPE_BUFFER
) {
1061 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1063 /* Create a surface for each plane specified by the external format. */
1064 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1065 UNUSED
const bool isl_surf_created_successfully
=
1066 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1067 .dim
= target_to_isl_surf_dim(templ
->target
),
1069 .width
= templ
->width0
,
1070 .height
= templ
->height0
,
1071 .depth
= templ
->depth0
,
1072 .levels
= templ
->last_level
+ 1,
1073 .array_len
= templ
->array_size
,
1074 .samples
= MAX2(templ
->nr_samples
, 1),
1075 .min_alignment_B
= 0,
1076 .row_pitch_B
= whandle
->stride
,
1078 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1079 assert(isl_surf_created_successfully
);
1080 assert(res
->bo
->tiling_mode
==
1081 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1083 // XXX: create_ccs_buf_for_image?
1084 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1085 if (!iris_resource_alloc_separate_aux(screen
, res
))
1088 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1089 uint32_t alloc_flags
;
1091 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1094 /* The gallium dri layer will create a separate plane resource
1095 * for the aux image. iris_resource_finish_aux_import will
1096 * merge the separate aux parameters back into a single
1102 /* Save modifier import information to reconstruct later. After
1103 * import, this will be available under a second image accessible
1104 * from the main image with res->base.next. See
1105 * iris_resource_finish_aux_import.
1107 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1108 res
->aux
.offset
= whandle
->offset
;
1109 res
->aux
.bo
= res
->bo
;
1117 iris_resource_destroy(pscreen
, &res
->base
);
1122 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1124 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1125 struct iris_resource
*res
= (void *) resource
;
1126 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1128 iris_resource_prepare_access(ice
, res
,
1129 0, INTEL_REMAINING_LEVELS
,
1130 0, INTEL_REMAINING_LAYERS
,
1131 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1132 mod
? mod
->supports_clear_color
: false);
1136 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1139 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1141 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1143 /* Disable aux usage if explicit flush not set and this is the first time
1144 * we are dealing with this resource and the resource was not created with
1145 * a modifier with aux.
1147 if (!mod_with_aux
&&
1148 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1149 p_atomic_read(&resource
->reference
.count
) == 1) {
1150 iris_resource_disable_aux(res
);
1155 iris_resource_get_param(struct pipe_screen
*pscreen
,
1156 struct pipe_context
*context
,
1157 struct pipe_resource
*resource
,
1160 enum pipe_resource_param param
,
1161 unsigned handle_usage
,
1164 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1165 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1167 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1168 bool wants_aux
= mod_with_aux
&& plane
> 0;
1172 if (iris_resource_unfinished_aux_import(res
))
1173 iris_resource_finish_aux_import(pscreen
, res
);
1175 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1177 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1180 case PIPE_RESOURCE_PARAM_NPLANES
:
1185 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1190 case PIPE_RESOURCE_PARAM_STRIDE
:
1191 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1193 case PIPE_RESOURCE_PARAM_OFFSET
:
1194 *value
= wants_aux
? res
->aux
.offset
: 0;
1196 case PIPE_RESOURCE_PARAM_MODIFIER
:
1197 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1198 tiling_to_modifier(res
->bo
->tiling_mode
);
1200 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1201 result
= iris_bo_flink(bo
, &handle
) == 0;
1205 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1206 /* Because we share the same drm file across multiple iris_screen, when
1207 * we export a GEM handle we must make sure it is valid in the DRM file
1208 * descriptor the caller is using (this is the FD given at screen
1212 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1218 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1219 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1229 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1230 struct pipe_context
*ctx
,
1231 struct pipe_resource
*resource
,
1232 struct winsys_handle
*whandle
,
1235 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1236 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1238 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1240 iris_resource_disable_aux_on_first_query(resource
, usage
);
1243 if (mod_with_aux
&& whandle
->plane
> 0) {
1244 assert(res
->aux
.bo
);
1246 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1247 whandle
->offset
= res
->aux
.offset
;
1249 /* If this is a buffer, stride should be 0 - no need to special case */
1250 whandle
->stride
= res
->surf
.row_pitch_B
;
1254 whandle
->format
= res
->external_format
;
1256 res
->mod_info
? res
->mod_info
->modifier
1257 : tiling_to_modifier(res
->bo
->tiling_mode
);
1260 enum isl_aux_usage allowed_usage
=
1261 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1263 if (res
->aux
.usage
!= allowed_usage
) {
1264 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1265 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1266 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1270 switch (whandle
->type
) {
1271 case WINSYS_HANDLE_TYPE_SHARED
:
1272 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1273 case WINSYS_HANDLE_TYPE_KMS
: {
1274 /* Because we share the same drm file across multiple iris_screen, when
1275 * we export a GEM handle we must make sure it is valid in the DRM file
1276 * descriptor the caller is using (this is the FD given at screen
1280 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1282 whandle
->handle
= handle
;
1285 case WINSYS_HANDLE_TYPE_FD
:
1286 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1293 resource_is_busy(struct iris_context
*ice
,
1294 struct iris_resource
*res
)
1296 bool busy
= iris_bo_busy(res
->bo
);
1298 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1299 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1305 iris_invalidate_resource(struct pipe_context
*ctx
,
1306 struct pipe_resource
*resource
)
1308 struct iris_screen
*screen
= (void *) ctx
->screen
;
1309 struct iris_context
*ice
= (void *) ctx
;
1310 struct iris_resource
*res
= (void *) resource
;
1312 if (resource
->target
!= PIPE_BUFFER
)
1315 /* If it's already invalidated, don't bother doing anything. */
1316 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1319 if (!resource_is_busy(ice
, res
)) {
1320 /* The resource is idle, so just mark that it contains no data and
1321 * keep using the same underlying buffer object.
1323 util_range_set_empty(&res
->valid_buffer_range
);
1327 /* Otherwise, try and replace the backing storage with a new BO. */
1329 /* We can't reallocate memory we didn't allocate in the first place. */
1330 if (res
->bo
->userptr
)
1333 // XXX: We should support this.
1334 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1337 struct iris_bo
*old_bo
= res
->bo
;
1338 struct iris_bo
*new_bo
=
1339 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1340 iris_memzone_for_address(old_bo
->gtt_offset
));
1344 /* Swap out the backing storage */
1347 /* Rebind the buffer, replacing any state referring to the old BO's
1348 * address, and marking state dirty so it's reemitted.
1350 screen
->vtbl
.rebind_buffer(ice
, res
);
1352 util_range_set_empty(&res
->valid_buffer_range
);
1354 iris_bo_unreference(old_bo
);
1358 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1359 const struct pipe_box
*flush_box
)
1361 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1364 struct iris_transfer
*map
= (void *) xfer
;
1366 struct pipe_box src_box
= *flush_box
;
1368 /* Account for extra alignment padding in staging buffer */
1369 if (xfer
->resource
->target
== PIPE_BUFFER
)
1370 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1372 struct pipe_box dst_box
= (struct pipe_box
) {
1373 .x
= xfer
->box
.x
+ flush_box
->x
,
1374 .y
= xfer
->box
.y
+ flush_box
->y
,
1375 .z
= xfer
->box
.z
+ flush_box
->z
,
1376 .width
= flush_box
->width
,
1377 .height
= flush_box
->height
,
1378 .depth
= flush_box
->depth
,
1381 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1382 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1387 iris_unmap_copy_region(struct iris_transfer
*map
)
1389 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1395 iris_map_copy_region(struct iris_transfer
*map
)
1397 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1398 struct pipe_transfer
*xfer
= &map
->base
;
1399 struct pipe_box
*box
= &xfer
->box
;
1400 struct iris_resource
*res
= (void *) xfer
->resource
;
1402 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1403 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1405 struct pipe_resource templ
= (struct pipe_resource
) {
1406 .usage
= PIPE_USAGE_STAGING
,
1407 .width0
= box
->width
+ extra
,
1408 .height0
= box
->height
,
1410 .nr_samples
= xfer
->resource
->nr_samples
,
1411 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1412 .array_size
= box
->depth
,
1413 .format
= res
->internal_format
,
1416 if (xfer
->resource
->target
== PIPE_BUFFER
)
1417 templ
.target
= PIPE_BUFFER
;
1418 else if (templ
.array_size
> 1)
1419 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1421 templ
.target
= PIPE_TEXTURE_2D
;
1423 map
->staging
= iris_resource_create(pscreen
, &templ
);
1424 assert(map
->staging
);
1426 if (templ
.target
!= PIPE_BUFFER
) {
1427 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1428 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1429 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1432 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1433 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1434 xfer
->resource
, xfer
->level
, box
);
1435 /* Ensure writes to the staging BO land before we map it below. */
1436 iris_emit_pipe_control_flush(map
->batch
,
1437 "transfer read: flush before mapping",
1438 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1439 PIPE_CONTROL_CS_STALL
);
1442 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1444 if (iris_batch_references(map
->batch
, staging_bo
))
1445 iris_batch_flush(map
->batch
);
1448 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1450 map
->unmap
= iris_unmap_copy_region
;
1454 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1455 unsigned *out_x0_el
, unsigned *out_y0_el
)
1457 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1458 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1460 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1465 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1466 * different tiling patterns.
1469 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1470 uint32_t *tile_w
, uint32_t *tile_h
)
1481 case ISL_TILING_LINEAR
:
1486 unreachable("not reached");
1492 * This function computes masks that may be used to select the bits of the X
1493 * and Y coordinates that indicate the offset within a tile. If the BO is
1494 * untiled, the masks are set to 0.
1497 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1498 uint32_t *mask_x
, uint32_t *mask_y
)
1500 uint32_t tile_w_bytes
, tile_h
;
1502 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1504 *mask_x
= tile_w_bytes
/ cpp
- 1;
1505 *mask_y
= tile_h
- 1;
1509 * Compute the offset (in bytes) from the start of the BO to the given x
1510 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1511 * multiples of the tile size.
1514 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1515 uint32_t x
, uint32_t y
)
1517 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1518 unsigned cpp
= fmtl
->bpb
/ 8;
1519 uint32_t pitch
= res
->surf
.row_pitch_B
;
1521 switch (res
->surf
.tiling
) {
1523 unreachable("not reached");
1524 case ISL_TILING_LINEAR
:
1525 return y
* pitch
+ x
* cpp
;
1527 assert((x
% (512 / cpp
)) == 0);
1528 assert((y
% 8) == 0);
1529 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1531 assert((x
% (128 / cpp
)) == 0);
1532 assert((y
% 32) == 0);
1533 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1538 * Rendering with tiled buffers requires that the base address of the buffer
1539 * be aligned to a page boundary. For renderbuffers, and sometimes with
1540 * textures, we may want the surface to point at a texture image level that
1541 * isn't at a page boundary.
1543 * This function returns an appropriately-aligned base offset
1544 * according to the tiling restrictions, plus any required x/y offset
1548 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1549 uint32_t level
, uint32_t z
,
1550 uint32_t *tile_x
, uint32_t *tile_y
)
1553 uint32_t mask_x
, mask_y
;
1555 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1556 const unsigned cpp
= fmtl
->bpb
/ 8;
1558 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1559 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1561 *tile_x
= x
& mask_x
;
1562 *tile_y
= y
& mask_y
;
1564 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1568 * Get pointer offset into stencil buffer.
1570 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1571 * must decode the tile's layout in software.
1574 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1576 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1578 * Even though the returned offset is always positive, the return type is
1580 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1581 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1584 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1586 uint32_t tile_size
= 4096;
1587 uint32_t tile_width
= 64;
1588 uint32_t tile_height
= 64;
1589 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1591 uint32_t tile_x
= x
/ tile_width
;
1592 uint32_t tile_y
= y
/ tile_height
;
1594 /* The byte's address relative to the tile's base addres. */
1595 uint32_t byte_x
= x
% tile_width
;
1596 uint32_t byte_y
= y
% tile_height
;
1598 uintptr_t u
= tile_y
* row_size
1599 + tile_x
* tile_size
1600 + 512 * (byte_x
/ 8)
1602 + 32 * ((byte_y
/ 4) % 2)
1603 + 16 * ((byte_x
/ 4) % 2)
1604 + 8 * ((byte_y
/ 2) % 2)
1605 + 4 * ((byte_x
/ 2) % 2)
1613 iris_unmap_s8(struct iris_transfer
*map
)
1615 struct pipe_transfer
*xfer
= &map
->base
;
1616 const struct pipe_box
*box
= &xfer
->box
;
1617 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1618 struct isl_surf
*surf
= &res
->surf
;
1620 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1621 uint8_t *untiled_s8_map
= map
->ptr
;
1622 uint8_t *tiled_s8_map
=
1623 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1625 for (int s
= 0; s
< box
->depth
; s
++) {
1626 unsigned x0_el
, y0_el
;
1627 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1629 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1630 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1631 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1633 y0_el
+ box
->y
+ y
);
1634 tiled_s8_map
[offset
] =
1635 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1645 iris_map_s8(struct iris_transfer
*map
)
1647 struct pipe_transfer
*xfer
= &map
->base
;
1648 const struct pipe_box
*box
= &xfer
->box
;
1649 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1650 struct isl_surf
*surf
= &res
->surf
;
1652 xfer
->stride
= surf
->row_pitch_B
;
1653 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1655 /* The tiling and detiling functions require that the linear buffer has
1656 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1657 * over-allocate the linear buffer to get the proper alignment.
1659 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1660 assert(map
->buffer
);
1662 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1663 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1664 * invalidate is set, since we'll be writing the whole rectangle from our
1665 * temporary buffer back out.
1667 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1668 uint8_t *untiled_s8_map
= map
->ptr
;
1669 uint8_t *tiled_s8_map
=
1670 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1672 for (int s
= 0; s
< box
->depth
; s
++) {
1673 unsigned x0_el
, y0_el
;
1674 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1676 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1677 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1678 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1680 y0_el
+ box
->y
+ y
);
1681 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1682 tiled_s8_map
[offset
];
1688 map
->unmap
= iris_unmap_s8
;
1691 /* Compute extent parameters for use with tiled_memcpy functions.
1692 * xs are in units of bytes and ys are in units of strides.
1695 tile_extents(const struct isl_surf
*surf
,
1696 const struct pipe_box
*box
,
1697 unsigned level
, int z
,
1698 unsigned *x1_B
, unsigned *x2_B
,
1699 unsigned *y1_el
, unsigned *y2_el
)
1701 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1702 const unsigned cpp
= fmtl
->bpb
/ 8;
1704 assert(box
->x
% fmtl
->bw
== 0);
1705 assert(box
->y
% fmtl
->bh
== 0);
1707 unsigned x0_el
, y0_el
;
1708 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1710 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1711 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1712 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1713 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1717 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1719 struct pipe_transfer
*xfer
= &map
->base
;
1720 const struct pipe_box
*box
= &xfer
->box
;
1721 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1722 struct isl_surf
*surf
= &res
->surf
;
1724 const bool has_swizzling
= false;
1726 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1728 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1730 for (int s
= 0; s
< box
->depth
; s
++) {
1731 unsigned x1
, x2
, y1
, y2
;
1732 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1734 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1736 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1737 surf
->row_pitch_B
, xfer
->stride
,
1738 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1741 os_free_aligned(map
->buffer
);
1742 map
->buffer
= map
->ptr
= NULL
;
1746 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1748 struct pipe_transfer
*xfer
= &map
->base
;
1749 const struct pipe_box
*box
= &xfer
->box
;
1750 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1751 struct isl_surf
*surf
= &res
->surf
;
1753 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1754 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1756 unsigned x1
, x2
, y1
, y2
;
1757 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1759 /* The tiling and detiling functions require that the linear buffer has
1760 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1761 * over-allocate the linear buffer to get the proper alignment.
1764 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1765 assert(map
->buffer
);
1766 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1768 const bool has_swizzling
= false;
1770 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1772 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1774 for (int s
= 0; s
< box
->depth
; s
++) {
1775 unsigned x1
, x2
, y1
, y2
;
1776 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1778 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1779 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1781 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1782 surf
->row_pitch_B
, has_swizzling
,
1783 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1787 map
->unmap
= iris_unmap_tiled_memcpy
;
1791 iris_map_direct(struct iris_transfer
*map
)
1793 struct pipe_transfer
*xfer
= &map
->base
;
1794 struct pipe_box
*box
= &xfer
->box
;
1795 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1797 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1799 if (res
->base
.target
== PIPE_BUFFER
) {
1801 xfer
->layer_stride
= 0;
1803 map
->ptr
= ptr
+ box
->x
;
1805 struct isl_surf
*surf
= &res
->surf
;
1806 const struct isl_format_layout
*fmtl
=
1807 isl_format_get_layout(surf
->format
);
1808 const unsigned cpp
= fmtl
->bpb
/ 8;
1809 unsigned x0_el
, y0_el
;
1811 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1813 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1814 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1816 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1821 can_promote_to_async(const struct iris_resource
*res
,
1822 const struct pipe_box
*box
,
1823 enum pipe_transfer_usage usage
)
1825 /* If we're writing to a section of the buffer that hasn't even been
1826 * initialized with useful data, then we can safely promote this write
1827 * to be unsynchronized. This helps the common pattern of appending data.
1829 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1830 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1831 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1832 box
->x
+ box
->width
);
1836 iris_transfer_map(struct pipe_context
*ctx
,
1837 struct pipe_resource
*resource
,
1839 enum pipe_transfer_usage usage
,
1840 const struct pipe_box
*box
,
1841 struct pipe_transfer
**ptransfer
)
1843 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1844 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1845 struct isl_surf
*surf
= &res
->surf
;
1847 if (iris_resource_unfinished_aux_import(res
))
1848 iris_resource_finish_aux_import(ctx
->screen
, res
);
1850 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1851 /* Replace the backing storage with a fresh buffer for non-async maps */
1852 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1853 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1854 iris_invalidate_resource(ctx
, resource
);
1856 /* If we can discard the whole resource, we can discard the range. */
1857 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1860 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1861 can_promote_to_async(res
, box
, usage
)) {
1862 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1865 bool need_resolve
= false;
1866 bool need_color_resolve
= false;
1868 if (resource
->target
!= PIPE_BUFFER
) {
1869 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1870 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1872 need_color_resolve
=
1873 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1874 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1875 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) &&
1876 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1878 need_resolve
= need_color_resolve
||
1880 need_stencil_resolve
;
1883 bool map_would_stall
= false;
1885 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1886 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1888 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1889 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1893 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1894 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1897 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1898 struct pipe_transfer
*xfer
= &map
->base
;
1903 memset(map
, 0, sizeof(*map
));
1904 map
->dbg
= &ice
->dbg
;
1906 pipe_resource_reference(&xfer
->resource
, resource
);
1907 xfer
->level
= level
;
1908 xfer
->usage
= usage
;
1912 map
->dest_had_defined_contents
=
1913 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1914 box
->x
+ box
->width
);
1916 if (usage
& PIPE_TRANSFER_WRITE
)
1917 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1919 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1920 * there is to access them simultaneously on the CPU & GPU. This also
1921 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1922 * contain state we're constructing for a GPU draw call, which would
1923 * kill us with infinite stack recursion.
1925 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1926 PIPE_TRANSFER_COHERENT
|
1927 PIPE_TRANSFER_MAP_DIRECTLY
);
1929 /* GPU copies are not useful for buffer reads. Instead of stalling to
1930 * read from the original buffer, we'd simply copy it to a temporary...
1931 * then stall (a bit longer) to read from that buffer.
1933 * Images are less clear-cut. Color resolves are destructive, removing
1934 * the underlying compression, so we'd rather blit the data to a linear
1935 * temporary and map that, to avoid the resolve. (It might be better to
1936 * a tiled temporary and use the tiled_memcpy paths...)
1938 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1941 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1942 if (fmtl
->txc
== ISL_TXC_ASTC
)
1945 if ((map_would_stall
||
1946 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1947 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) && !no_gpu
) {
1948 /* If we need a synchronous mapping and the resource is busy, or needs
1949 * resolving, we copy to/from a linear temporary buffer using the GPU.
1951 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1952 map
->blorp
= &ice
->blorp
;
1953 iris_map_copy_region(map
);
1955 /* Otherwise we're free to map on the CPU. */
1958 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1959 usage
& PIPE_TRANSFER_WRITE
);
1962 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1963 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1964 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1965 iris_batch_flush(&ice
->batches
[i
]);
1969 if (surf
->tiling
== ISL_TILING_W
) {
1970 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1972 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1973 iris_map_tiled_memcpy(map
);
1975 iris_map_direct(map
);
1983 iris_transfer_flush_region(struct pipe_context
*ctx
,
1984 struct pipe_transfer
*xfer
,
1985 const struct pipe_box
*box
)
1987 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1988 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1989 struct iris_transfer
*map
= (void *) xfer
;
1992 iris_flush_staging_region(xfer
, box
);
1994 uint32_t history_flush
= 0;
1996 if (res
->base
.target
== PIPE_BUFFER
) {
1998 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2000 if (map
->dest_had_defined_contents
)
2001 history_flush
|= iris_flush_bits_for_history(res
);
2003 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
2006 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
2007 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
2008 struct iris_batch
*batch
= &ice
->batches
[i
];
2009 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
2010 iris_batch_maybe_flush(batch
, 24);
2011 iris_emit_pipe_control_flush(batch
,
2012 "cache history: transfer flush",
2018 /* Make sure we flag constants dirty even if there's no need to emit
2019 * any PIPE_CONTROLs to a batch.
2021 iris_dirty_for_history(ice
, res
);
2025 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
2027 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2028 struct iris_transfer
*map
= (void *) xfer
;
2030 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
2031 PIPE_TRANSFER_COHERENT
))) {
2032 struct pipe_box flush_box
= {
2033 .x
= 0, .y
= 0, .z
= 0,
2034 .width
= xfer
->box
.width
,
2035 .height
= xfer
->box
.height
,
2036 .depth
= xfer
->box
.depth
,
2038 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2044 pipe_resource_reference(&xfer
->resource
, NULL
);
2045 slab_free(&ice
->transfer_pool
, map
);
2049 * Mark state dirty that needs to be re-emitted when a resource is written.
2052 iris_dirty_for_history(struct iris_context
*ice
,
2053 struct iris_resource
*res
)
2055 uint64_t stage_dirty
= 0ull;
2057 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2058 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2059 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2062 ice
->state
.stage_dirty
|= stage_dirty
;
2066 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2067 * resource becomes visible, and any stale read cache data is invalidated.
2070 iris_flush_bits_for_history(struct iris_resource
*res
)
2072 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2074 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2075 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2076 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2079 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2080 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2082 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2083 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2085 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2086 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2092 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2093 struct iris_batch
*batch
,
2094 struct iris_resource
*res
,
2095 uint32_t extra_flags
,
2098 if (res
->base
.target
!= PIPE_BUFFER
)
2101 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2103 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2105 iris_dirty_for_history(ice
, res
);
2109 iris_resource_set_clear_color(struct iris_context
*ice
,
2110 struct iris_resource
*res
,
2111 union isl_color_value color
)
2113 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2114 res
->aux
.clear_color
= color
;
2121 union isl_color_value
2122 iris_resource_get_clear_color(const struct iris_resource
*res
,
2123 struct iris_bo
**clear_color_bo
,
2124 uint64_t *clear_color_offset
)
2126 assert(res
->aux
.bo
);
2129 *clear_color_bo
= res
->aux
.clear_color_bo
;
2130 if (clear_color_offset
)
2131 *clear_color_offset
= res
->aux
.clear_color_offset
;
2132 return res
->aux
.clear_color
;
2135 static enum pipe_format
2136 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2138 struct iris_resource
*res
= (void *) p_res
;
2139 return res
->internal_format
;
2142 static const struct u_transfer_vtbl transfer_vtbl
= {
2143 .resource_create
= iris_resource_create
,
2144 .resource_destroy
= iris_resource_destroy
,
2145 .transfer_map
= iris_transfer_map
,
2146 .transfer_unmap
= iris_transfer_unmap
,
2147 .transfer_flush_region
= iris_transfer_flush_region
,
2148 .get_internal_format
= iris_resource_get_internal_format
,
2149 .set_stencil
= iris_resource_set_separate_stencil
,
2150 .get_stencil
= iris_resource_get_separate_stencil
,
2154 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2156 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2157 pscreen
->resource_create_with_modifiers
=
2158 iris_resource_create_with_modifiers
;
2159 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2160 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2161 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2162 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2163 pscreen
->resource_get_param
= iris_resource_get_param
;
2164 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2165 pscreen
->transfer_helper
=
2166 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2170 iris_init_resource_functions(struct pipe_context
*ctx
)
2172 ctx
->flush_resource
= iris_flush_resource
;
2173 ctx
->invalidate_resource
= iris_invalidate_resource
;
2174 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2175 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2176 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2177 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2178 ctx
->texture_subdata
= u_default_texture_subdata
;