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iris: Make iris_bo_import_dmabuf take a modifier
[mesa.git] / src / gallium / drivers / iris / iris_resource.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_resource.c
25 *
26 * Resources are images, buffers, and other objects used by the GPU.
27 *
28 * XXX: explain resources
29 */
30
31 #include <stdio.h>
32 #include <errno.h>
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
52 #include "isl/isl.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
55
56 enum modifier_priority {
57 MODIFIER_PRIORITY_INVALID = 0,
58 MODIFIER_PRIORITY_LINEAR,
59 MODIFIER_PRIORITY_X,
60 MODIFIER_PRIORITY_Y,
61 MODIFIER_PRIORITY_Y_CCS,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS,
63 };
64
65 static const uint64_t priority_to_modifier[] = {
66 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
67 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
68 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
69 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
70 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
72 };
73
74 static bool
75 modifier_is_supported(const struct gen_device_info *devinfo,
76 enum pipe_format pfmt, uint64_t modifier)
77 {
78 /* Check for basic device support. */
79 switch (modifier) {
80 case DRM_FORMAT_MOD_LINEAR:
81 case I915_FORMAT_MOD_X_TILED:
82 case I915_FORMAT_MOD_Y_TILED:
83 break;
84 case I915_FORMAT_MOD_Y_TILED_CCS:
85 if (devinfo->gen <= 8 || devinfo->gen >= 12)
86 return false;
87 break;
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
89 if (devinfo->gen != 12)
90 return false;
91 break;
92 case DRM_FORMAT_MOD_INVALID:
93 default:
94 return false;
95 }
96
97 /* Check remaining requirements. */
98 switch (modifier) {
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
100 case I915_FORMAT_MOD_Y_TILED_CCS: {
101 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
102 return false;
103
104 enum isl_format rt_format =
105 iris_format_for_usage(devinfo, pfmt,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;
107
108 if (rt_format == ISL_FORMAT_UNSUPPORTED ||
109 !isl_format_supports_ccs_e(devinfo, rt_format))
110 return false;
111 break;
112 }
113 default:
114 break;
115 }
116
117 return true;
118 }
119
120 static uint64_t
121 select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
122 const uint64_t *modifiers,
123 int count)
124 {
125 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
126
127 for (int i = 0; i < count; i++) {
128 if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
129 continue;
130
131 switch (modifiers[i]) {
132 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
133 prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS);
134 break;
135 case I915_FORMAT_MOD_Y_TILED_CCS:
136 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
137 break;
138 case I915_FORMAT_MOD_Y_TILED:
139 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
140 break;
141 case I915_FORMAT_MOD_X_TILED:
142 prio = MAX2(prio, MODIFIER_PRIORITY_X);
143 break;
144 case DRM_FORMAT_MOD_LINEAR:
145 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
146 break;
147 case DRM_FORMAT_MOD_INVALID:
148 default:
149 break;
150 }
151 }
152
153 return priority_to_modifier[prio];
154 }
155
156 enum isl_surf_dim
157 target_to_isl_surf_dim(enum pipe_texture_target target)
158 {
159 switch (target) {
160 case PIPE_BUFFER:
161 case PIPE_TEXTURE_1D:
162 case PIPE_TEXTURE_1D_ARRAY:
163 return ISL_SURF_DIM_1D;
164 case PIPE_TEXTURE_2D:
165 case PIPE_TEXTURE_CUBE:
166 case PIPE_TEXTURE_RECT:
167 case PIPE_TEXTURE_2D_ARRAY:
168 case PIPE_TEXTURE_CUBE_ARRAY:
169 return ISL_SURF_DIM_2D;
170 case PIPE_TEXTURE_3D:
171 return ISL_SURF_DIM_3D;
172 case PIPE_MAX_TEXTURE_TYPES:
173 break;
174 }
175 unreachable("invalid texture type");
176 }
177
178 static void
179 iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
180 enum pipe_format pfmt,
181 int max,
182 uint64_t *modifiers,
183 unsigned int *external_only,
184 int *count)
185 {
186 struct iris_screen *screen = (void *) pscreen;
187 const struct gen_device_info *devinfo = &screen->devinfo;
188
189 uint64_t all_modifiers[] = {
190 DRM_FORMAT_MOD_LINEAR,
191 I915_FORMAT_MOD_X_TILED,
192 I915_FORMAT_MOD_Y_TILED,
193 I915_FORMAT_MOD_Y_TILED_CCS,
194 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
195 };
196
197 int supported_mods = 0;
198
199 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
200 if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
201 continue;
202
203 if (supported_mods < max) {
204 if (modifiers)
205 modifiers[supported_mods] = all_modifiers[i];
206
207 if (external_only)
208 external_only[supported_mods] = util_format_is_yuv(pfmt);
209 }
210
211 supported_mods++;
212 }
213
214 *count = supported_mods;
215 }
216
217 static isl_surf_usage_flags_t
218 pipe_bind_to_isl_usage(unsigned bindings)
219 {
220 isl_surf_usage_flags_t usage = 0;
221
222 if (bindings & PIPE_BIND_RENDER_TARGET)
223 usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
224
225 if (bindings & PIPE_BIND_SAMPLER_VIEW)
226 usage |= ISL_SURF_USAGE_TEXTURE_BIT;
227
228 if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
229 usage |= ISL_SURF_USAGE_STORAGE_BIT;
230
231 if (bindings & PIPE_BIND_SCANOUT)
232 usage |= ISL_SURF_USAGE_DISPLAY_BIT;
233
234 return usage;
235 }
236
237 enum isl_format
238 iris_image_view_get_format(struct iris_context *ice,
239 const struct pipe_image_view *img)
240 {
241 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
242 const struct gen_device_info *devinfo = &screen->devinfo;
243
244 isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
245 enum isl_format isl_fmt =
246 iris_format_for_usage(devinfo, img->format, usage).fmt;
247
248 if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
249 /* On Gen8, try to use typed surfaces reads (which support a
250 * limited number of formats), and if not possible, fall back
251 * to untyped reads.
252 */
253 if (devinfo->gen == 8 &&
254 !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
255 return ISL_FORMAT_RAW;
256 else
257 return isl_lower_storage_image_format(devinfo, isl_fmt);
258 }
259
260 return isl_fmt;
261 }
262
263 struct pipe_resource *
264 iris_resource_get_separate_stencil(struct pipe_resource *p_res)
265 {
266 /* For packed depth-stencil, we treat depth as the primary resource
267 * and store S8 as the "second plane" resource.
268 */
269 if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT)
270 return p_res->next;
271
272 return NULL;
273
274 }
275
276 static void
277 iris_resource_set_separate_stencil(struct pipe_resource *p_res,
278 struct pipe_resource *stencil)
279 {
280 assert(util_format_has_depth(util_format_description(p_res->format)));
281 pipe_resource_reference(&p_res->next, stencil);
282 }
283
284 void
285 iris_get_depth_stencil_resources(struct pipe_resource *res,
286 struct iris_resource **out_z,
287 struct iris_resource **out_s)
288 {
289 if (!res) {
290 *out_z = NULL;
291 *out_s = NULL;
292 return;
293 }
294
295 if (res->format != PIPE_FORMAT_S8_UINT) {
296 *out_z = (void *) res;
297 *out_s = (void *) iris_resource_get_separate_stencil(res);
298 } else {
299 *out_z = NULL;
300 *out_s = (void *) res;
301 }
302 }
303
304 enum isl_dim_layout
305 iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
306 enum isl_tiling tiling,
307 enum pipe_texture_target target)
308 {
309 switch (target) {
310 case PIPE_TEXTURE_1D:
311 case PIPE_TEXTURE_1D_ARRAY:
312 return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
313 ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
314
315 case PIPE_TEXTURE_2D:
316 case PIPE_TEXTURE_2D_ARRAY:
317 case PIPE_TEXTURE_RECT:
318 case PIPE_TEXTURE_CUBE:
319 case PIPE_TEXTURE_CUBE_ARRAY:
320 return ISL_DIM_LAYOUT_GEN4_2D;
321
322 case PIPE_TEXTURE_3D:
323 return (devinfo->gen >= 9 ?
324 ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
325
326 case PIPE_MAX_TEXTURE_TYPES:
327 case PIPE_BUFFER:
328 break;
329 }
330 unreachable("invalid texture type");
331 }
332
333 void
334 iris_resource_disable_aux(struct iris_resource *res)
335 {
336 iris_bo_unreference(res->aux.bo);
337 iris_bo_unreference(res->aux.clear_color_bo);
338 free(res->aux.state);
339
340 res->aux.usage = ISL_AUX_USAGE_NONE;
341 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
342 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
343 res->aux.has_hiz = 0;
344 res->aux.surf.size_B = 0;
345 res->aux.bo = NULL;
346 res->aux.extra_aux.surf.size_B = 0;
347 res->aux.clear_color_bo = NULL;
348 res->aux.state = NULL;
349 }
350
351 static void
352 iris_resource_destroy(struct pipe_screen *screen,
353 struct pipe_resource *resource)
354 {
355 struct iris_resource *res = (struct iris_resource *)resource;
356
357 if (resource->target == PIPE_BUFFER)
358 util_range_destroy(&res->valid_buffer_range);
359
360 iris_resource_disable_aux(res);
361
362 iris_bo_unreference(res->bo);
363 iris_pscreen_unref(res->base.screen);
364
365 free(res);
366 }
367
368 static struct iris_resource *
369 iris_alloc_resource(struct pipe_screen *pscreen,
370 const struct pipe_resource *templ)
371 {
372 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
373 if (!res)
374 return NULL;
375
376 res->base = *templ;
377 res->base.screen = iris_pscreen_ref(pscreen);
378 pipe_reference_init(&res->base.reference, 1);
379
380 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
381 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
382
383 if (templ->target == PIPE_BUFFER)
384 util_range_init(&res->valid_buffer_range);
385
386 return res;
387 }
388
389 unsigned
390 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
391 {
392 if (res->surf.dim == ISL_SURF_DIM_3D)
393 return minify(res->surf.logical_level0_px.depth, level);
394 else
395 return res->surf.logical_level0_px.array_len;
396 }
397
398 static enum isl_aux_state **
399 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
400 {
401 assert(res->aux.state == NULL);
402
403 uint32_t total_slices = 0;
404 for (uint32_t level = 0; level < res->surf.levels; level++)
405 total_slices += iris_get_num_logical_layers(res, level);
406
407 const size_t per_level_array_size =
408 res->surf.levels * sizeof(enum isl_aux_state *);
409
410 /* We're going to allocate a single chunk of data for both the per-level
411 * reference array and the arrays of aux_state. This makes cleanup
412 * significantly easier.
413 */
414 const size_t total_size =
415 per_level_array_size + total_slices * sizeof(enum isl_aux_state);
416
417 void *data = malloc(total_size);
418 if (!data)
419 return NULL;
420
421 enum isl_aux_state **per_level_arr = data;
422 enum isl_aux_state *s = data + per_level_array_size;
423 for (uint32_t level = 0; level < res->surf.levels; level++) {
424 per_level_arr[level] = s;
425 const unsigned level_layers = iris_get_num_logical_layers(res, level);
426 for (uint32_t a = 0; a < level_layers; a++)
427 *(s++) = initial;
428 }
429 assert((void *)s == data + total_size);
430
431 return per_level_arr;
432 }
433
434 static unsigned
435 iris_get_aux_clear_color_state_size(struct iris_screen *screen)
436 {
437 const struct gen_device_info *devinfo = &screen->devinfo;
438 return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
439 }
440
441 static void
442 map_aux_addresses(struct iris_screen *screen, struct iris_resource *res)
443 {
444 const struct gen_device_info *devinfo = &screen->devinfo;
445 if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
446 void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
447 assert(aux_map_ctx);
448 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
449 res->aux.extra_aux.offset : res->aux.offset;
450 gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset,
451 res->aux.bo->gtt_offset + aux_offset);
452 res->bo->aux_map_address = res->aux.bo->gtt_offset;
453 }
454 }
455
456 static bool
457 want_ccs_e_for_format(const struct gen_device_info *devinfo,
458 enum isl_format format)
459 {
460 if (!isl_format_supports_ccs_e(devinfo, format))
461 return false;
462
463 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
464
465 /* CCS_E seems to significantly hurt performance with 32-bit floating
466 * point formats. For example, Paraview's "Wavelet Volume" case uses
467 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
468 * formats causes a 62% FPS drop.
469 *
470 * However, many benchmarks seem to use 16-bit float with no issues.
471 */
472 if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
473 return false;
474
475 return true;
476 }
477
478 /**
479 * Configure aux for the resource, but don't allocate it. For images which
480 * might be shared with modifiers, we must allocate the image and aux data in
481 * a single bo.
482 *
483 * Returns false on unexpected error (e.g. allocation failed, or invalid
484 * configuration result).
485 */
486 static bool
487 iris_resource_configure_aux(struct iris_screen *screen,
488 struct iris_resource *res, bool imported,
489 uint64_t *aux_size_B,
490 uint32_t *alloc_flags)
491 {
492 const struct gen_device_info *devinfo = &screen->devinfo;
493
494 /* Try to create the auxiliary surfaces allowed by the modifier or by
495 * the user if no modifier is specified.
496 */
497 assert(!res->mod_info ||
498 res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
499 res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
500 res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E);
501
502 const bool has_mcs = !res->mod_info &&
503 isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
504
505 const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
506 isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
507
508 const bool has_ccs =
509 ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
510 (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
511 isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
512 &res->aux.extra_aux.surf, 0);
513
514 /* Having both HIZ and MCS is impossible. */
515 assert(!has_mcs || !has_hiz);
516
517 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
518 if (has_ccs && (has_mcs || has_hiz)) {
519 assert(res->aux.extra_aux.surf.size_B > 0 &&
520 res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
521 assert(res->aux.surf.size_B > 0 &&
522 res->aux.surf.usage &
523 (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
524 }
525
526 if (res->mod_info && has_ccs) {
527 /* Only allow a CCS modifier if the aux was created successfully. */
528 res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
529 } else if (has_mcs) {
530 res->aux.possible_usages |=
531 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
532 } else if (has_hiz) {
533 if (!has_ccs) {
534 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
535 } else if (res->surf.samples == 1 &&
536 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
537 /* If this resource is single-sampled and will be used as a texture,
538 * put the HiZ surface in write-through mode so that we can sample
539 * from it.
540 */
541 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
542 } else {
543 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
544 }
545 } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
546 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
547 } else if (has_ccs) {
548 if (want_ccs_e_for_format(devinfo, res->surf.format)) {
549 res->aux.possible_usages |= devinfo->gen < 12 ?
550 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
551 } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
552 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
553 }
554 }
555
556 res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
557
558 res->aux.sampler_usages = res->aux.possible_usages;
559
560 /* We don't always support sampling with hiz. But when we do, it must be
561 * single sampled.
562 */
563 if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
564 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
565
566 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
567 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
568
569 enum isl_aux_state initial_state;
570 *aux_size_B = 0;
571 *alloc_flags = 0;
572 assert(!res->aux.bo);
573
574 switch (res->aux.usage) {
575 case ISL_AUX_USAGE_NONE:
576 /* Having no aux buffer is only okay if there's no modifier with aux. */
577 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
578 case ISL_AUX_USAGE_HIZ:
579 case ISL_AUX_USAGE_HIZ_CCS:
580 case ISL_AUX_USAGE_HIZ_CCS_WT:
581 initial_state = ISL_AUX_STATE_AUX_INVALID;
582 break;
583 case ISL_AUX_USAGE_MCS:
584 case ISL_AUX_USAGE_MCS_CCS:
585 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
586 *
587 * "When MCS buffer is enabled and bound to MSRT, it is required
588 * that it is cleared prior to any rendering."
589 *
590 * Since we only use the MCS buffer for rendering, we just clear it
591 * immediately on allocation. The clear value for MCS buffers is all
592 * 1's, so we simply memset it to 0xff.
593 */
594 initial_state = ISL_AUX_STATE_CLEAR;
595 break;
596 case ISL_AUX_USAGE_CCS_D:
597 case ISL_AUX_USAGE_CCS_E:
598 case ISL_AUX_USAGE_GEN12_CCS_E:
599 case ISL_AUX_USAGE_STC_CCS:
600 /* When CCS_E is used, we need to ensure that the CCS starts off in
601 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
602 * Target(s)":
603 *
604 * "If Software wants to enable Color Compression without Fast
605 * clear, Software needs to initialize MCS with zeros."
606 *
607 * A CCS value of 0 indicates that the corresponding block is in the
608 * pass-through state which is what we want.
609 *
610 * For CCS_D, do the same thing. On Gen9+, this avoids having any
611 * undefined bits in the aux buffer.
612 */
613 if (imported) {
614 assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
615 initial_state =
616 isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
617 } else {
618 initial_state = ISL_AUX_STATE_PASS_THROUGH;
619 }
620 *alloc_flags |= BO_ALLOC_ZEROED;
621 break;
622 case ISL_AUX_USAGE_MC:
623 default:
624 unreachable("Unsupported aux mode");
625 }
626
627 /* Create the aux_state for the auxiliary buffer. */
628 res->aux.state = create_aux_state_map(res, initial_state);
629 if (!res->aux.state)
630 return false;
631
632 /* Increase the aux offset if the main and aux surfaces will share a BO. */
633 res->aux.offset =
634 !res->mod_info || res->mod_info->aux_usage == res->aux.usage ?
635 ALIGN(res->surf.size_B, res->aux.surf.alignment_B) : 0;
636 uint64_t size = res->aux.surf.size_B;
637
638 /* Allocate space in the buffer for storing the CCS. */
639 if (res->aux.extra_aux.surf.size_B > 0) {
640 const uint64_t padded_aux_size =
641 ALIGN(size, res->aux.extra_aux.surf.alignment_B);
642 res->aux.extra_aux.offset = res->aux.offset + padded_aux_size;
643 size = padded_aux_size + res->aux.extra_aux.surf.size_B;
644 }
645
646 /* Allocate space in the buffer for storing the clear color. On modern
647 * platforms (gen > 9), we can read it directly from such buffer.
648 *
649 * On gen <= 9, we are going to store the clear color on the buffer
650 * anyways, and copy it back to the surface state during state emission.
651 *
652 * Also add some padding to make sure the fast clear color state buffer
653 * starts at a 4K alignment. We believe that 256B might be enough, but due
654 * to lack of testing we will leave this as 4K for now.
655 */
656 size = ALIGN(size, 4096);
657 res->aux.clear_color_offset = res->aux.offset + size;
658 size += iris_get_aux_clear_color_state_size(screen);
659 *aux_size_B = size;
660
661 if (isl_aux_usage_has_hiz(res->aux.usage)) {
662 for (unsigned level = 0; level < res->surf.levels; ++level) {
663 uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
664 uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
665
666 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
667 * For LOD == 0, we can grow the dimensions to make it work.
668 */
669 if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
670 res->aux.has_hiz |= 1 << level;
671 }
672 }
673
674 return true;
675 }
676
677 /**
678 * Initialize the aux buffer contents.
679 *
680 * Returns false on unexpected error (e.g. mapping a BO failed).
681 */
682 static bool
683 iris_resource_init_aux_buf(struct iris_resource *res, uint32_t alloc_flags,
684 unsigned clear_color_state_size)
685 {
686 if (!(alloc_flags & BO_ALLOC_ZEROED)) {
687 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
688
689 if (!map)
690 return false;
691
692 if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
693 uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
694 memset((char*)map + res->aux.offset, memset_value,
695 res->aux.surf.size_B);
696 }
697
698 memset((char*)map + res->aux.extra_aux.offset,
699 0, res->aux.extra_aux.surf.size_B);
700
701 /* Zero the indirect clear color to match ::fast_clear_color. */
702 memset((char *)map + res->aux.clear_color_offset, 0,
703 clear_color_state_size);
704
705 iris_bo_unmap(res->aux.bo);
706 }
707
708 if (clear_color_state_size > 0) {
709 res->aux.clear_color_bo = res->aux.bo;
710 iris_bo_reference(res->aux.clear_color_bo);
711 }
712
713 return true;
714 }
715
716 /**
717 * Allocate the initial aux surface for a resource based on aux.usage
718 *
719 * Returns false on unexpected error (e.g. allocation failed, or invalid
720 * configuration result).
721 */
722 static bool
723 iris_resource_alloc_separate_aux(struct iris_screen *screen,
724 struct iris_resource *res)
725 {
726 uint32_t alloc_flags;
727 uint64_t size;
728 if (!iris_resource_configure_aux(screen, res, false, &size, &alloc_flags))
729 return false;
730
731 if (size == 0)
732 return true;
733
734 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
735 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
736 * of bytes instead of trying to recalculate based on different format
737 * block sizes.
738 */
739 res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, 4096,
740 IRIS_MEMZONE_OTHER,
741 isl_tiling_to_i915_tiling(res->aux.surf.tiling),
742 res->aux.surf.row_pitch_B, alloc_flags);
743 if (!res->aux.bo) {
744 return false;
745 }
746
747 if (!iris_resource_init_aux_buf(res, alloc_flags,
748 iris_get_aux_clear_color_state_size(screen)))
749 return false;
750
751 map_aux_addresses(screen, res);
752
753 return true;
754 }
755
756 void
757 iris_resource_finish_aux_import(struct pipe_screen *pscreen,
758 struct iris_resource *res)
759 {
760 struct iris_screen *screen = (struct iris_screen *)pscreen;
761 assert(iris_resource_unfinished_aux_import(res));
762 assert(!res->mod_info->supports_clear_color);
763
764 struct iris_resource *aux_res = (void *) res->base.next;
765 assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset &&
766 aux_res->aux.bo);
767
768 assert(res->bo == aux_res->aux.bo);
769 iris_bo_reference(aux_res->aux.bo);
770 res->aux.bo = aux_res->aux.bo;
771
772 res->aux.offset = aux_res->aux.offset;
773
774 assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B));
775 assert(res->aux.clear_color_bo == NULL);
776 res->aux.clear_color_offset = 0;
777
778 assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B);
779
780 unsigned clear_color_state_size =
781 iris_get_aux_clear_color_state_size(screen);
782
783 if (clear_color_state_size > 0) {
784 res->aux.clear_color_bo =
785 iris_bo_alloc_tiled(screen->bufmgr, "clear color_buffer",
786 clear_color_state_size, 1, IRIS_MEMZONE_OTHER,
787 I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
788 res->aux.clear_color_offset = 0;
789 }
790
791 iris_resource_destroy(&screen->base, res->base.next);
792 res->base.next = NULL;
793
794 map_aux_addresses(screen, res);
795 }
796
797 static struct pipe_resource *
798 iris_resource_create_for_buffer(struct pipe_screen *pscreen,
799 const struct pipe_resource *templ)
800 {
801 struct iris_screen *screen = (struct iris_screen *)pscreen;
802 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
803
804 assert(templ->target == PIPE_BUFFER);
805 assert(templ->height0 <= 1);
806 assert(templ->depth0 <= 1);
807 assert(templ->format == PIPE_FORMAT_NONE ||
808 util_format_get_blocksize(templ->format) == 1);
809
810 res->internal_format = templ->format;
811 res->surf.tiling = ISL_TILING_LINEAR;
812
813 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
814 const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
815 if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
816 memzone = IRIS_MEMZONE_SHADER;
817 name = "shader kernels";
818 } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
819 memzone = IRIS_MEMZONE_SURFACE;
820 name = "surface state";
821 } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
822 memzone = IRIS_MEMZONE_DYNAMIC;
823 name = "dynamic state";
824 }
825
826 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
827 if (!res->bo) {
828 iris_resource_destroy(pscreen, &res->base);
829 return NULL;
830 }
831
832 if (templ->bind & PIPE_BIND_SHARED)
833 iris_bo_make_external(res->bo);
834
835 return &res->base;
836 }
837
838 static struct pipe_resource *
839 iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
840 const struct pipe_resource *templ,
841 const uint64_t *modifiers,
842 int modifiers_count)
843 {
844 struct iris_screen *screen = (struct iris_screen *)pscreen;
845 struct gen_device_info *devinfo = &screen->devinfo;
846 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
847
848 if (!res)
849 return NULL;
850
851 const struct util_format_description *format_desc =
852 util_format_description(templ->format);
853 const bool has_depth = util_format_has_depth(format_desc);
854 uint64_t modifier =
855 select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
856
857 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
858
859 if (modifier != DRM_FORMAT_MOD_INVALID) {
860 res->mod_info = isl_drm_modifier_get_info(modifier);
861
862 tiling_flags = 1 << res->mod_info->tiling;
863 } else {
864 if (modifiers_count > 0) {
865 fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
866 goto fail;
867 }
868
869 /* Use linear for staging buffers */
870 if (templ->usage == PIPE_USAGE_STAGING ||
871 templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) ) {
872 tiling_flags = ISL_TILING_LINEAR_BIT;
873 } else if (templ->bind & PIPE_BIND_SCANOUT) {
874 if (devinfo->has_tiling_uapi)
875 tiling_flags = ISL_TILING_X_BIT;
876 else
877 tiling_flags = ISL_TILING_LINEAR_BIT;
878 }
879 }
880
881 isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
882
883 if (templ->target == PIPE_TEXTURE_CUBE ||
884 templ->target == PIPE_TEXTURE_CUBE_ARRAY)
885 usage |= ISL_SURF_USAGE_CUBE_BIT;
886
887 if (templ->usage != PIPE_USAGE_STAGING) {
888 if (templ->format == PIPE_FORMAT_S8_UINT)
889 usage |= ISL_SURF_USAGE_STENCIL_BIT;
890 else if (has_depth)
891 usage |= ISL_SURF_USAGE_DEPTH_BIT;
892 }
893
894 enum pipe_format pfmt = templ->format;
895 res->internal_format = pfmt;
896
897 /* Should be handled by u_transfer_helper */
898 assert(!util_format_is_depth_and_stencil(pfmt));
899
900 struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
901 assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
902
903 UNUSED const bool isl_surf_created_successfully =
904 isl_surf_init(&screen->isl_dev, &res->surf,
905 .dim = target_to_isl_surf_dim(templ->target),
906 .format = fmt.fmt,
907 .width = templ->width0,
908 .height = templ->height0,
909 .depth = templ->depth0,
910 .levels = templ->last_level + 1,
911 .array_len = templ->array_size,
912 .samples = MAX2(templ->nr_samples, 1),
913 .min_alignment_B = 0,
914 .row_pitch_B = 0,
915 .usage = usage,
916 .tiling_flags = tiling_flags);
917 assert(isl_surf_created_successfully);
918
919 const char *name = "miptree";
920 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
921
922 unsigned int flags = 0;
923 if (templ->usage == PIPE_USAGE_STAGING)
924 flags |= BO_ALLOC_COHERENT;
925
926 /* These are for u_upload_mgr buffers only */
927 assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
928 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
929 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
930
931 uint32_t aux_preferred_alloc_flags;
932 uint64_t aux_size = 0;
933 if (!iris_resource_configure_aux(screen, res, false, &aux_size,
934 &aux_preferred_alloc_flags)) {
935 goto fail;
936 }
937
938 /* Modifiers require the aux data to be in the same buffer as the main
939 * surface, but we combine them even when a modifiers is not being used.
940 */
941 const uint64_t bo_size =
942 MAX2(res->surf.size_B, res->aux.offset + aux_size);
943 uint32_t alignment = MAX2(4096, res->surf.alignment_B);
944 res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
945 memzone,
946 isl_tiling_to_i915_tiling(res->surf.tiling),
947 res->surf.row_pitch_B, flags);
948
949 if (!res->bo)
950 goto fail;
951
952 if (aux_size > 0) {
953 res->aux.bo = res->bo;
954 iris_bo_reference(res->aux.bo);
955 unsigned clear_color_state_size =
956 iris_get_aux_clear_color_state_size(screen);
957 if (!iris_resource_init_aux_buf(res, flags, clear_color_state_size))
958 goto fail;
959 map_aux_addresses(screen, res);
960 }
961
962 if (templ->bind & PIPE_BIND_SHARED)
963 iris_bo_make_external(res->bo);
964
965 return &res->base;
966
967 fail:
968 fprintf(stderr, "XXX: resource creation failed\n");
969 iris_resource_destroy(pscreen, &res->base);
970 return NULL;
971
972 }
973
974 static struct pipe_resource *
975 iris_resource_create(struct pipe_screen *pscreen,
976 const struct pipe_resource *templ)
977 {
978 if (templ->target == PIPE_BUFFER)
979 return iris_resource_create_for_buffer(pscreen, templ);
980 else
981 return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
982 }
983
984 static uint64_t
985 tiling_to_modifier(uint32_t tiling)
986 {
987 static const uint64_t map[] = {
988 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
989 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
990 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
991 };
992
993 assert(tiling < ARRAY_SIZE(map));
994
995 return map[tiling];
996 }
997
998 static struct pipe_resource *
999 iris_resource_from_user_memory(struct pipe_screen *pscreen,
1000 const struct pipe_resource *templ,
1001 void *user_memory)
1002 {
1003 struct iris_screen *screen = (struct iris_screen *)pscreen;
1004 struct iris_bufmgr *bufmgr = screen->bufmgr;
1005 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1006 if (!res)
1007 return NULL;
1008
1009 assert(templ->target == PIPE_BUFFER);
1010
1011 res->internal_format = templ->format;
1012 res->bo = iris_bo_create_userptr(bufmgr, "user",
1013 user_memory, templ->width0,
1014 IRIS_MEMZONE_OTHER);
1015 if (!res->bo) {
1016 iris_resource_destroy(pscreen, &res->base);
1017 return NULL;
1018 }
1019
1020 util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
1021
1022 return &res->base;
1023 }
1024
1025 static struct pipe_resource *
1026 iris_resource_from_handle(struct pipe_screen *pscreen,
1027 const struct pipe_resource *templ,
1028 struct winsys_handle *whandle,
1029 unsigned usage)
1030 {
1031 struct iris_screen *screen = (struct iris_screen *)pscreen;
1032 struct gen_device_info *devinfo = &screen->devinfo;
1033 struct iris_bufmgr *bufmgr = screen->bufmgr;
1034 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1035 const struct isl_drm_modifier_info *mod_inf =
1036 isl_drm_modifier_get_info(whandle->modifier);
1037
1038 if (!res)
1039 return NULL;
1040
1041 switch (whandle->type) {
1042 case WINSYS_HANDLE_TYPE_FD:
1043 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
1044 whandle->modifier);
1045 break;
1046 case WINSYS_HANDLE_TYPE_SHARED:
1047 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
1048 whandle->handle);
1049 break;
1050 default:
1051 unreachable("invalid winsys handle type");
1052 }
1053 if (!res->bo)
1054 goto fail;
1055
1056 res->offset = whandle->offset;
1057
1058 if (mod_inf == NULL) {
1059 mod_inf =
1060 isl_drm_modifier_get_info(tiling_to_modifier(res->bo->tiling_mode));
1061 }
1062 assert(mod_inf);
1063
1064 res->external_format = whandle->format;
1065 res->mod_info = mod_inf;
1066
1067 isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
1068
1069 const struct iris_format_info fmt =
1070 iris_format_for_usage(devinfo, templ->format, isl_usage);
1071 res->internal_format = templ->format;
1072
1073 if (templ->target == PIPE_BUFFER) {
1074 res->surf.tiling = ISL_TILING_LINEAR;
1075 } else {
1076 /* Create a surface for each plane specified by the external format. */
1077 if (whandle->plane < util_format_get_num_planes(whandle->format)) {
1078 UNUSED const bool isl_surf_created_successfully =
1079 isl_surf_init(&screen->isl_dev, &res->surf,
1080 .dim = target_to_isl_surf_dim(templ->target),
1081 .format = fmt.fmt,
1082 .width = templ->width0,
1083 .height = templ->height0,
1084 .depth = templ->depth0,
1085 .levels = templ->last_level + 1,
1086 .array_len = templ->array_size,
1087 .samples = MAX2(templ->nr_samples, 1),
1088 .min_alignment_B = 0,
1089 .row_pitch_B = whandle->stride,
1090 .usage = isl_usage,
1091 .tiling_flags = 1 << res->mod_info->tiling);
1092 assert(isl_surf_created_successfully);
1093 assert(res->bo->tiling_mode ==
1094 isl_tiling_to_i915_tiling(res->surf.tiling));
1095
1096 // XXX: create_ccs_buf_for_image?
1097 if (whandle->modifier == DRM_FORMAT_MOD_INVALID) {
1098 if (!iris_resource_alloc_separate_aux(screen, res))
1099 goto fail;
1100 } else {
1101 if (res->mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
1102 uint32_t alloc_flags;
1103 uint64_t size;
1104 bool ok = iris_resource_configure_aux(screen, res, true, &size,
1105 &alloc_flags);
1106 assert(ok);
1107 /* The gallium dri layer will create a separate plane resource
1108 * for the aux image. iris_resource_finish_aux_import will
1109 * merge the separate aux parameters back into a single
1110 * iris_resource.
1111 */
1112 }
1113 }
1114 } else {
1115 /* Save modifier import information to reconstruct later. After
1116 * import, this will be available under a second image accessible
1117 * from the main image with res->base.next. See
1118 * iris_resource_finish_aux_import.
1119 */
1120 res->aux.surf.row_pitch_B = whandle->stride;
1121 res->aux.offset = whandle->offset;
1122 res->aux.bo = res->bo;
1123 res->bo = NULL;
1124 }
1125 }
1126
1127 return &res->base;
1128
1129 fail:
1130 iris_resource_destroy(pscreen, &res->base);
1131 return NULL;
1132 }
1133
1134 static void
1135 iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
1136 {
1137 struct iris_context *ice = (struct iris_context *)ctx;
1138 struct iris_resource *res = (void *) resource;
1139 const struct isl_drm_modifier_info *mod = res->mod_info;
1140
1141 iris_resource_prepare_access(ice, res,
1142 0, INTEL_REMAINING_LEVELS,
1143 0, INTEL_REMAINING_LAYERS,
1144 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
1145 mod ? mod->supports_clear_color : false);
1146 }
1147
1148 static void
1149 iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
1150 unsigned usage)
1151 {
1152 struct iris_resource *res = (struct iris_resource *)resource;
1153 bool mod_with_aux =
1154 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1155
1156 /* Disable aux usage if explicit flush not set and this is the first time
1157 * we are dealing with this resource and the resource was not created with
1158 * a modifier with aux.
1159 */
1160 if (!mod_with_aux &&
1161 (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
1162 p_atomic_read(&resource->reference.count) == 1) {
1163 iris_resource_disable_aux(res);
1164 }
1165 }
1166
1167 static bool
1168 iris_resource_get_param(struct pipe_screen *pscreen,
1169 struct pipe_context *context,
1170 struct pipe_resource *resource,
1171 unsigned plane,
1172 unsigned layer,
1173 enum pipe_resource_param param,
1174 unsigned handle_usage,
1175 uint64_t *value)
1176 {
1177 struct iris_screen *screen = (struct iris_screen *)pscreen;
1178 struct iris_resource *res = (struct iris_resource *)resource;
1179 bool mod_with_aux =
1180 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1181 bool wants_aux = mod_with_aux && plane > 0;
1182 bool result;
1183 unsigned handle;
1184
1185 if (iris_resource_unfinished_aux_import(res))
1186 iris_resource_finish_aux_import(pscreen, res);
1187
1188 struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;
1189
1190 iris_resource_disable_aux_on_first_query(resource, handle_usage);
1191
1192 switch (param) {
1193 case PIPE_RESOURCE_PARAM_NPLANES:
1194 if (mod_with_aux) {
1195 *value = 2;
1196 } else {
1197 unsigned count = 0;
1198 for (struct pipe_resource *cur = resource; cur; cur = cur->next)
1199 count++;
1200 *value = count;
1201 }
1202 return true;
1203 case PIPE_RESOURCE_PARAM_STRIDE:
1204 *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
1205 return true;
1206 case PIPE_RESOURCE_PARAM_OFFSET:
1207 *value = wants_aux ? res->aux.offset : 0;
1208 return true;
1209 case PIPE_RESOURCE_PARAM_MODIFIER:
1210 *value = res->mod_info ? res->mod_info->modifier :
1211 tiling_to_modifier(res->bo->tiling_mode);
1212 return true;
1213 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
1214 result = iris_bo_flink(bo, &handle) == 0;
1215 if (result)
1216 *value = handle;
1217 return result;
1218 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
1219 /* Because we share the same drm file across multiple iris_screen, when
1220 * we export a GEM handle we must make sure it is valid in the DRM file
1221 * descriptor the caller is using (this is the FD given at screen
1222 * creation).
1223 */
1224 uint32_t handle;
1225 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1226 return false;
1227 *value = handle;
1228 return true;
1229 }
1230
1231 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
1232 result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
1233 if (result)
1234 *value = handle;
1235 return result;
1236 default:
1237 return false;
1238 }
1239 }
1240
1241 static bool
1242 iris_resource_get_handle(struct pipe_screen *pscreen,
1243 struct pipe_context *ctx,
1244 struct pipe_resource *resource,
1245 struct winsys_handle *whandle,
1246 unsigned usage)
1247 {
1248 struct iris_screen *screen = (struct iris_screen *) pscreen;
1249 struct iris_resource *res = (struct iris_resource *)resource;
1250 bool mod_with_aux =
1251 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1252
1253 iris_resource_disable_aux_on_first_query(resource, usage);
1254
1255 struct iris_bo *bo;
1256 if (mod_with_aux && whandle->plane > 0) {
1257 assert(res->aux.bo);
1258 bo = res->aux.bo;
1259 whandle->stride = res->aux.surf.row_pitch_B;
1260 whandle->offset = res->aux.offset;
1261 } else {
1262 /* If this is a buffer, stride should be 0 - no need to special case */
1263 whandle->stride = res->surf.row_pitch_B;
1264 bo = res->bo;
1265 }
1266
1267 whandle->format = res->external_format;
1268 whandle->modifier =
1269 res->mod_info ? res->mod_info->modifier
1270 : tiling_to_modifier(res->bo->tiling_mode);
1271
1272 #ifndef NDEBUG
1273 enum isl_aux_usage allowed_usage =
1274 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
1275
1276 if (res->aux.usage != allowed_usage) {
1277 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
1278 assert(aux_state == ISL_AUX_STATE_RESOLVED ||
1279 aux_state == ISL_AUX_STATE_PASS_THROUGH);
1280 }
1281 #endif
1282
1283 switch (whandle->type) {
1284 case WINSYS_HANDLE_TYPE_SHARED:
1285 return iris_bo_flink(bo, &whandle->handle) == 0;
1286 case WINSYS_HANDLE_TYPE_KMS: {
1287 /* Because we share the same drm file across multiple iris_screen, when
1288 * we export a GEM handle we must make sure it is valid in the DRM file
1289 * descriptor the caller is using (this is the FD given at screen
1290 * creation).
1291 */
1292 uint32_t handle;
1293 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1294 return false;
1295 whandle->handle = handle;
1296 return true;
1297 }
1298 case WINSYS_HANDLE_TYPE_FD:
1299 return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
1300 }
1301
1302 return false;
1303 }
1304
1305 static bool
1306 resource_is_busy(struct iris_context *ice,
1307 struct iris_resource *res)
1308 {
1309 bool busy = iris_bo_busy(res->bo);
1310
1311 for (int i = 0; i < IRIS_BATCH_COUNT; i++)
1312 busy |= iris_batch_references(&ice->batches[i], res->bo);
1313
1314 return busy;
1315 }
1316
1317 static void
1318 iris_invalidate_resource(struct pipe_context *ctx,
1319 struct pipe_resource *resource)
1320 {
1321 struct iris_screen *screen = (void *) ctx->screen;
1322 struct iris_context *ice = (void *) ctx;
1323 struct iris_resource *res = (void *) resource;
1324
1325 if (resource->target != PIPE_BUFFER)
1326 return;
1327
1328 /* If it's already invalidated, don't bother doing anything. */
1329 if (res->valid_buffer_range.start > res->valid_buffer_range.end)
1330 return;
1331
1332 if (!resource_is_busy(ice, res)) {
1333 /* The resource is idle, so just mark that it contains no data and
1334 * keep using the same underlying buffer object.
1335 */
1336 util_range_set_empty(&res->valid_buffer_range);
1337 return;
1338 }
1339
1340 /* Otherwise, try and replace the backing storage with a new BO. */
1341
1342 /* We can't reallocate memory we didn't allocate in the first place. */
1343 if (res->bo->userptr)
1344 return;
1345
1346 // XXX: We should support this.
1347 if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
1348 return;
1349
1350 struct iris_bo *old_bo = res->bo;
1351 struct iris_bo *new_bo =
1352 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
1353 iris_memzone_for_address(old_bo->gtt_offset));
1354 if (!new_bo)
1355 return;
1356
1357 /* Swap out the backing storage */
1358 res->bo = new_bo;
1359
1360 /* Rebind the buffer, replacing any state referring to the old BO's
1361 * address, and marking state dirty so it's reemitted.
1362 */
1363 screen->vtbl.rebind_buffer(ice, res);
1364
1365 util_range_set_empty(&res->valid_buffer_range);
1366
1367 iris_bo_unreference(old_bo);
1368 }
1369
1370 static void
1371 iris_flush_staging_region(struct pipe_transfer *xfer,
1372 const struct pipe_box *flush_box)
1373 {
1374 if (!(xfer->usage & PIPE_TRANSFER_WRITE))
1375 return;
1376
1377 struct iris_transfer *map = (void *) xfer;
1378
1379 struct pipe_box src_box = *flush_box;
1380
1381 /* Account for extra alignment padding in staging buffer */
1382 if (xfer->resource->target == PIPE_BUFFER)
1383 src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
1384
1385 struct pipe_box dst_box = (struct pipe_box) {
1386 .x = xfer->box.x + flush_box->x,
1387 .y = xfer->box.y + flush_box->y,
1388 .z = xfer->box.z + flush_box->z,
1389 .width = flush_box->width,
1390 .height = flush_box->height,
1391 .depth = flush_box->depth,
1392 };
1393
1394 iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
1395 dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
1396 &src_box);
1397 }
1398
1399 static void
1400 iris_unmap_copy_region(struct iris_transfer *map)
1401 {
1402 iris_resource_destroy(map->staging->screen, map->staging);
1403
1404 map->ptr = NULL;
1405 }
1406
1407 static void
1408 iris_map_copy_region(struct iris_transfer *map)
1409 {
1410 struct pipe_screen *pscreen = &map->batch->screen->base;
1411 struct pipe_transfer *xfer = &map->base;
1412 struct pipe_box *box = &xfer->box;
1413 struct iris_resource *res = (void *) xfer->resource;
1414
1415 unsigned extra = xfer->resource->target == PIPE_BUFFER ?
1416 box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
1417
1418 struct pipe_resource templ = (struct pipe_resource) {
1419 .usage = PIPE_USAGE_STAGING,
1420 .width0 = box->width + extra,
1421 .height0 = box->height,
1422 .depth0 = 1,
1423 .nr_samples = xfer->resource->nr_samples,
1424 .nr_storage_samples = xfer->resource->nr_storage_samples,
1425 .array_size = box->depth,
1426 .format = res->internal_format,
1427 };
1428
1429 if (xfer->resource->target == PIPE_BUFFER)
1430 templ.target = PIPE_BUFFER;
1431 else if (templ.array_size > 1)
1432 templ.target = PIPE_TEXTURE_2D_ARRAY;
1433 else
1434 templ.target = PIPE_TEXTURE_2D;
1435
1436 map->staging = iris_resource_create(pscreen, &templ);
1437 assert(map->staging);
1438
1439 if (templ.target != PIPE_BUFFER) {
1440 struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
1441 xfer->stride = isl_surf_get_row_pitch_B(surf);
1442 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1443 }
1444
1445 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1446 iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
1447 xfer->resource, xfer->level, box);
1448 /* Ensure writes to the staging BO land before we map it below. */
1449 iris_emit_pipe_control_flush(map->batch,
1450 "transfer read: flush before mapping",
1451 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1452 PIPE_CONTROL_CS_STALL);
1453 }
1454
1455 struct iris_bo *staging_bo = iris_resource_bo(map->staging);
1456
1457 if (iris_batch_references(map->batch, staging_bo))
1458 iris_batch_flush(map->batch);
1459
1460 map->ptr =
1461 iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
1462
1463 map->unmap = iris_unmap_copy_region;
1464 }
1465
1466 static void
1467 get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z,
1468 unsigned *out_x0_el, unsigned *out_y0_el)
1469 {
1470 if (surf->dim == ISL_SURF_DIM_3D) {
1471 isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
1472 } else {
1473 isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
1474 }
1475 }
1476
1477 /**
1478 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1479 * different tiling patterns.
1480 */
1481 static void
1482 iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
1483 uint32_t *tile_w, uint32_t *tile_h)
1484 {
1485 switch (tiling) {
1486 case ISL_TILING_X:
1487 *tile_w = 512;
1488 *tile_h = 8;
1489 break;
1490 case ISL_TILING_Y0:
1491 *tile_w = 128;
1492 *tile_h = 32;
1493 break;
1494 case ISL_TILING_LINEAR:
1495 *tile_w = cpp;
1496 *tile_h = 1;
1497 break;
1498 default:
1499 unreachable("not reached");
1500 }
1501
1502 }
1503
1504 /**
1505 * This function computes masks that may be used to select the bits of the X
1506 * and Y coordinates that indicate the offset within a tile. If the BO is
1507 * untiled, the masks are set to 0.
1508 */
1509 static void
1510 iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
1511 uint32_t *mask_x, uint32_t *mask_y)
1512 {
1513 uint32_t tile_w_bytes, tile_h;
1514
1515 iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
1516
1517 *mask_x = tile_w_bytes / cpp - 1;
1518 *mask_y = tile_h - 1;
1519 }
1520
1521 /**
1522 * Compute the offset (in bytes) from the start of the BO to the given x
1523 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1524 * multiples of the tile size.
1525 */
1526 static uint32_t
1527 iris_resource_get_aligned_offset(const struct iris_resource *res,
1528 uint32_t x, uint32_t y)
1529 {
1530 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1531 unsigned cpp = fmtl->bpb / 8;
1532 uint32_t pitch = res->surf.row_pitch_B;
1533
1534 switch (res->surf.tiling) {
1535 default:
1536 unreachable("not reached");
1537 case ISL_TILING_LINEAR:
1538 return y * pitch + x * cpp;
1539 case ISL_TILING_X:
1540 assert((x % (512 / cpp)) == 0);
1541 assert((y % 8) == 0);
1542 return y * pitch + x / (512 / cpp) * 4096;
1543 case ISL_TILING_Y0:
1544 assert((x % (128 / cpp)) == 0);
1545 assert((y % 32) == 0);
1546 return y * pitch + x / (128 / cpp) * 4096;
1547 }
1548 }
1549
1550 /**
1551 * Rendering with tiled buffers requires that the base address of the buffer
1552 * be aligned to a page boundary. For renderbuffers, and sometimes with
1553 * textures, we may want the surface to point at a texture image level that
1554 * isn't at a page boundary.
1555 *
1556 * This function returns an appropriately-aligned base offset
1557 * according to the tiling restrictions, plus any required x/y offset
1558 * from there.
1559 */
1560 uint32_t
1561 iris_resource_get_tile_offsets(const struct iris_resource *res,
1562 uint32_t level, uint32_t z,
1563 uint32_t *tile_x, uint32_t *tile_y)
1564 {
1565 uint32_t x, y;
1566 uint32_t mask_x, mask_y;
1567
1568 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1569 const unsigned cpp = fmtl->bpb / 8;
1570
1571 iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y);
1572 get_image_offset_el(&res->surf, level, z, &x, &y);
1573
1574 *tile_x = x & mask_x;
1575 *tile_y = y & mask_y;
1576
1577 return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y);
1578 }
1579
1580 /**
1581 * Get pointer offset into stencil buffer.
1582 *
1583 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1584 * must decode the tile's layout in software.
1585 *
1586 * See
1587 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1588 * Format.
1589 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1590 *
1591 * Even though the returned offset is always positive, the return type is
1592 * signed due to
1593 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1594 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1595 */
1596 static intptr_t
1597 s8_offset(uint32_t stride, uint32_t x, uint32_t y)
1598 {
1599 uint32_t tile_size = 4096;
1600 uint32_t tile_width = 64;
1601 uint32_t tile_height = 64;
1602 uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
1603
1604 uint32_t tile_x = x / tile_width;
1605 uint32_t tile_y = y / tile_height;
1606
1607 /* The byte's address relative to the tile's base addres. */
1608 uint32_t byte_x = x % tile_width;
1609 uint32_t byte_y = y % tile_height;
1610
1611 uintptr_t u = tile_y * row_size
1612 + tile_x * tile_size
1613 + 512 * (byte_x / 8)
1614 + 64 * (byte_y / 8)
1615 + 32 * ((byte_y / 4) % 2)
1616 + 16 * ((byte_x / 4) % 2)
1617 + 8 * ((byte_y / 2) % 2)
1618 + 4 * ((byte_x / 2) % 2)
1619 + 2 * (byte_y % 2)
1620 + 1 * (byte_x % 2);
1621
1622 return u;
1623 }
1624
1625 static void
1626 iris_unmap_s8(struct iris_transfer *map)
1627 {
1628 struct pipe_transfer *xfer = &map->base;
1629 const struct pipe_box *box = &xfer->box;
1630 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1631 struct isl_surf *surf = &res->surf;
1632
1633 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1634 uint8_t *untiled_s8_map = map->ptr;
1635 uint8_t *tiled_s8_map =
1636 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1637
1638 for (int s = 0; s < box->depth; s++) {
1639 unsigned x0_el, y0_el;
1640 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1641
1642 for (uint32_t y = 0; y < box->height; y++) {
1643 for (uint32_t x = 0; x < box->width; x++) {
1644 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1645 x0_el + box->x + x,
1646 y0_el + box->y + y);
1647 tiled_s8_map[offset] =
1648 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
1649 }
1650 }
1651 }
1652 }
1653
1654 free(map->buffer);
1655 }
1656
1657 static void
1658 iris_map_s8(struct iris_transfer *map)
1659 {
1660 struct pipe_transfer *xfer = &map->base;
1661 const struct pipe_box *box = &xfer->box;
1662 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1663 struct isl_surf *surf = &res->surf;
1664
1665 xfer->stride = surf->row_pitch_B;
1666 xfer->layer_stride = xfer->stride * box->height;
1667
1668 /* The tiling and detiling functions require that the linear buffer has
1669 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1670 * over-allocate the linear buffer to get the proper alignment.
1671 */
1672 map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
1673 assert(map->buffer);
1674
1675 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1676 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1677 * invalidate is set, since we'll be writing the whole rectangle from our
1678 * temporary buffer back out.
1679 */
1680 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1681 uint8_t *untiled_s8_map = map->ptr;
1682 uint8_t *tiled_s8_map =
1683 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1684
1685 for (int s = 0; s < box->depth; s++) {
1686 unsigned x0_el, y0_el;
1687 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1688
1689 for (uint32_t y = 0; y < box->height; y++) {
1690 for (uint32_t x = 0; x < box->width; x++) {
1691 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1692 x0_el + box->x + x,
1693 y0_el + box->y + y);
1694 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
1695 tiled_s8_map[offset];
1696 }
1697 }
1698 }
1699 }
1700
1701 map->unmap = iris_unmap_s8;
1702 }
1703
1704 /* Compute extent parameters for use with tiled_memcpy functions.
1705 * xs are in units of bytes and ys are in units of strides.
1706 */
1707 static inline void
1708 tile_extents(const struct isl_surf *surf,
1709 const struct pipe_box *box,
1710 unsigned level, int z,
1711 unsigned *x1_B, unsigned *x2_B,
1712 unsigned *y1_el, unsigned *y2_el)
1713 {
1714 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1715 const unsigned cpp = fmtl->bpb / 8;
1716
1717 assert(box->x % fmtl->bw == 0);
1718 assert(box->y % fmtl->bh == 0);
1719
1720 unsigned x0_el, y0_el;
1721 get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
1722
1723 *x1_B = (box->x / fmtl->bw + x0_el) * cpp;
1724 *y1_el = box->y / fmtl->bh + y0_el;
1725 *x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
1726 *y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
1727 }
1728
1729 static void
1730 iris_unmap_tiled_memcpy(struct iris_transfer *map)
1731 {
1732 struct pipe_transfer *xfer = &map->base;
1733 const struct pipe_box *box = &xfer->box;
1734 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1735 struct isl_surf *surf = &res->surf;
1736
1737 const bool has_swizzling = false;
1738
1739 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1740 char *dst =
1741 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1742
1743 for (int s = 0; s < box->depth; s++) {
1744 unsigned x1, x2, y1, y2;
1745 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1746
1747 void *ptr = map->ptr + s * xfer->layer_stride;
1748
1749 isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
1750 surf->row_pitch_B, xfer->stride,
1751 has_swizzling, surf->tiling, ISL_MEMCPY);
1752 }
1753 }
1754 os_free_aligned(map->buffer);
1755 map->buffer = map->ptr = NULL;
1756 }
1757
1758 static void
1759 iris_map_tiled_memcpy(struct iris_transfer *map)
1760 {
1761 struct pipe_transfer *xfer = &map->base;
1762 const struct pipe_box *box = &xfer->box;
1763 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1764 struct isl_surf *surf = &res->surf;
1765
1766 xfer->stride = ALIGN(surf->row_pitch_B, 16);
1767 xfer->layer_stride = xfer->stride * box->height;
1768
1769 unsigned x1, x2, y1, y2;
1770 tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
1771
1772 /* The tiling and detiling functions require that the linear buffer has
1773 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1774 * over-allocate the linear buffer to get the proper alignment.
1775 */
1776 map->buffer =
1777 os_malloc_aligned(xfer->layer_stride * box->depth, 16);
1778 assert(map->buffer);
1779 map->ptr = (char *)map->buffer + (x1 & 0xf);
1780
1781 const bool has_swizzling = false;
1782
1783 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1784 char *src =
1785 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1786
1787 for (int s = 0; s < box->depth; s++) {
1788 unsigned x1, x2, y1, y2;
1789 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1790
1791 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1792 void *ptr = map->ptr + s * xfer->layer_stride;
1793
1794 isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
1795 surf->row_pitch_B, has_swizzling,
1796 surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
1797 }
1798 }
1799
1800 map->unmap = iris_unmap_tiled_memcpy;
1801 }
1802
1803 static void
1804 iris_map_direct(struct iris_transfer *map)
1805 {
1806 struct pipe_transfer *xfer = &map->base;
1807 struct pipe_box *box = &xfer->box;
1808 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1809
1810 void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
1811
1812 if (res->base.target == PIPE_BUFFER) {
1813 xfer->stride = 0;
1814 xfer->layer_stride = 0;
1815
1816 map->ptr = ptr + box->x;
1817 } else {
1818 struct isl_surf *surf = &res->surf;
1819 const struct isl_format_layout *fmtl =
1820 isl_format_get_layout(surf->format);
1821 const unsigned cpp = fmtl->bpb / 8;
1822 unsigned x0_el, y0_el;
1823
1824 get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
1825
1826 xfer->stride = isl_surf_get_row_pitch_B(surf);
1827 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1828
1829 map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
1830 }
1831 }
1832
1833 static bool
1834 can_promote_to_async(const struct iris_resource *res,
1835 const struct pipe_box *box,
1836 enum pipe_transfer_usage usage)
1837 {
1838 /* If we're writing to a section of the buffer that hasn't even been
1839 * initialized with useful data, then we can safely promote this write
1840 * to be unsynchronized. This helps the common pattern of appending data.
1841 */
1842 return res->base.target == PIPE_BUFFER && (usage & PIPE_TRANSFER_WRITE) &&
1843 !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
1844 !util_ranges_intersect(&res->valid_buffer_range, box->x,
1845 box->x + box->width);
1846 }
1847
1848 static void *
1849 iris_transfer_map(struct pipe_context *ctx,
1850 struct pipe_resource *resource,
1851 unsigned level,
1852 enum pipe_transfer_usage usage,
1853 const struct pipe_box *box,
1854 struct pipe_transfer **ptransfer)
1855 {
1856 struct iris_context *ice = (struct iris_context *)ctx;
1857 struct iris_resource *res = (struct iris_resource *)resource;
1858 struct isl_surf *surf = &res->surf;
1859
1860 if (iris_resource_unfinished_aux_import(res))
1861 iris_resource_finish_aux_import(ctx->screen, res);
1862
1863 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
1864 /* Replace the backing storage with a fresh buffer for non-async maps */
1865 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
1866 TC_TRANSFER_MAP_NO_INVALIDATE)))
1867 iris_invalidate_resource(ctx, resource);
1868
1869 /* If we can discard the whole resource, we can discard the range. */
1870 usage |= PIPE_TRANSFER_DISCARD_RANGE;
1871 }
1872
1873 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
1874 can_promote_to_async(res, box, usage)) {
1875 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1876 }
1877
1878 bool need_resolve = false;
1879 bool need_color_resolve = false;
1880
1881 if (resource->target != PIPE_BUFFER) {
1882 bool need_hiz_resolve = iris_resource_level_has_hiz(res, level);
1883 bool need_stencil_resolve = res->aux.usage == ISL_AUX_USAGE_STC_CCS;
1884
1885 need_color_resolve =
1886 (res->aux.usage == ISL_AUX_USAGE_CCS_D ||
1887 res->aux.usage == ISL_AUX_USAGE_CCS_E ||
1888 res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) &&
1889 iris_has_color_unresolved(res, level, 1, box->z, box->depth);
1890
1891 need_resolve = need_color_resolve ||
1892 need_hiz_resolve ||
1893 need_stencil_resolve;
1894 }
1895
1896 bool map_would_stall = false;
1897
1898 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1899 map_would_stall = need_resolve || resource_is_busy(ice, res);
1900
1901 if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
1902 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1903 return NULL;
1904 }
1905
1906 if (surf->tiling != ISL_TILING_LINEAR &&
1907 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1908 return NULL;
1909
1910 struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
1911 struct pipe_transfer *xfer = &map->base;
1912
1913 if (!map)
1914 return NULL;
1915
1916 memset(map, 0, sizeof(*map));
1917 map->dbg = &ice->dbg;
1918
1919 pipe_resource_reference(&xfer->resource, resource);
1920 xfer->level = level;
1921 xfer->usage = usage;
1922 xfer->box = *box;
1923 *ptransfer = xfer;
1924
1925 map->dest_had_defined_contents =
1926 util_ranges_intersect(&res->valid_buffer_range, box->x,
1927 box->x + box->width);
1928
1929 if (usage & PIPE_TRANSFER_WRITE)
1930 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1931
1932 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1933 * there is to access them simultaneously on the CPU & GPU. This also
1934 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1935 * contain state we're constructing for a GPU draw call, which would
1936 * kill us with infinite stack recursion.
1937 */
1938 bool no_gpu = usage & (PIPE_TRANSFER_PERSISTENT |
1939 PIPE_TRANSFER_COHERENT |
1940 PIPE_TRANSFER_MAP_DIRECTLY);
1941
1942 /* GPU copies are not useful for buffer reads. Instead of stalling to
1943 * read from the original buffer, we'd simply copy it to a temporary...
1944 * then stall (a bit longer) to read from that buffer.
1945 *
1946 * Images are less clear-cut. Color resolves are destructive, removing
1947 * the underlying compression, so we'd rather blit the data to a linear
1948 * temporary and map that, to avoid the resolve. (It might be better to
1949 * a tiled temporary and use the tiled_memcpy paths...)
1950 */
1951 if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && !need_color_resolve)
1952 no_gpu = true;
1953
1954 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1955 if (fmtl->txc == ISL_TXC_ASTC)
1956 no_gpu = true;
1957
1958 if ((map_would_stall ||
1959 res->aux.usage == ISL_AUX_USAGE_CCS_E ||
1960 res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) && !no_gpu) {
1961 /* If we need a synchronous mapping and the resource is busy, or needs
1962 * resolving, we copy to/from a linear temporary buffer using the GPU.
1963 */
1964 map->batch = &ice->batches[IRIS_BATCH_RENDER];
1965 map->blorp = &ice->blorp;
1966 iris_map_copy_region(map);
1967 } else {
1968 /* Otherwise we're free to map on the CPU. */
1969
1970 if (need_resolve) {
1971 iris_resource_access_raw(ice, res, level, box->z, box->depth,
1972 usage & PIPE_TRANSFER_WRITE);
1973 }
1974
1975 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1976 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1977 if (iris_batch_references(&ice->batches[i], res->bo))
1978 iris_batch_flush(&ice->batches[i]);
1979 }
1980 }
1981
1982 if (surf->tiling == ISL_TILING_W) {
1983 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1984 iris_map_s8(map);
1985 } else if (surf->tiling != ISL_TILING_LINEAR) {
1986 iris_map_tiled_memcpy(map);
1987 } else {
1988 iris_map_direct(map);
1989 }
1990 }
1991
1992 return map->ptr;
1993 }
1994
1995 static void
1996 iris_transfer_flush_region(struct pipe_context *ctx,
1997 struct pipe_transfer *xfer,
1998 const struct pipe_box *box)
1999 {
2000 struct iris_context *ice = (struct iris_context *)ctx;
2001 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2002 struct iris_transfer *map = (void *) xfer;
2003
2004 if (map->staging)
2005 iris_flush_staging_region(xfer, box);
2006
2007 uint32_t history_flush = 0;
2008
2009 if (res->base.target == PIPE_BUFFER) {
2010 if (map->staging)
2011 history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
2012
2013 if (map->dest_had_defined_contents)
2014 history_flush |= iris_flush_bits_for_history(res);
2015
2016 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
2017 }
2018
2019 if (history_flush & ~PIPE_CONTROL_CS_STALL) {
2020 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
2021 struct iris_batch *batch = &ice->batches[i];
2022 if (batch->contains_draw || batch->cache.render->entries) {
2023 iris_batch_maybe_flush(batch, 24);
2024 iris_emit_pipe_control_flush(batch,
2025 "cache history: transfer flush",
2026 history_flush);
2027 }
2028 }
2029 }
2030
2031 /* Make sure we flag constants dirty even if there's no need to emit
2032 * any PIPE_CONTROLs to a batch.
2033 */
2034 iris_dirty_for_history(ice, res);
2035 }
2036
2037 static void
2038 iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
2039 {
2040 struct iris_context *ice = (struct iris_context *)ctx;
2041 struct iris_transfer *map = (void *) xfer;
2042
2043 if (!(xfer->usage & (PIPE_TRANSFER_FLUSH_EXPLICIT |
2044 PIPE_TRANSFER_COHERENT))) {
2045 struct pipe_box flush_box = {
2046 .x = 0, .y = 0, .z = 0,
2047 .width = xfer->box.width,
2048 .height = xfer->box.height,
2049 .depth = xfer->box.depth,
2050 };
2051 iris_transfer_flush_region(ctx, xfer, &flush_box);
2052 }
2053
2054 if (map->unmap)
2055 map->unmap(map);
2056
2057 pipe_resource_reference(&xfer->resource, NULL);
2058 slab_free(&ice->transfer_pool, map);
2059 }
2060
2061 /**
2062 * The pipe->texture_subdata() driver hook.
2063 *
2064 * Mesa's state tracker takes this path whenever possible, even with
2065 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2066 */
2067 static void
2068 iris_texture_subdata(struct pipe_context *ctx,
2069 struct pipe_resource *resource,
2070 unsigned level,
2071 unsigned usage,
2072 const struct pipe_box *box,
2073 const void *data,
2074 unsigned stride,
2075 unsigned layer_stride)
2076 {
2077 struct iris_context *ice = (struct iris_context *)ctx;
2078 struct iris_resource *res = (struct iris_resource *)resource;
2079 const struct isl_surf *surf = &res->surf;
2080
2081 assert(resource->target != PIPE_BUFFER);
2082
2083 if (iris_resource_unfinished_aux_import(res))
2084 iris_resource_finish_aux_import(ctx->screen, res);
2085
2086 /* Just use the transfer-based path for linear buffers - it will already
2087 * do a direct mapping, or a simple linear staging buffer.
2088 *
2089 * Linear staging buffers appear to be better than tiled ones, too, so
2090 * take that path if we need the GPU to perform color compression, or
2091 * stall-avoidance blits.
2092 */
2093 if (surf->tiling == ISL_TILING_LINEAR ||
2094 (isl_aux_usage_has_ccs(res->aux.usage) &&
2095 res->aux.usage != ISL_AUX_USAGE_CCS_D) ||
2096 resource_is_busy(ice, res)) {
2097 return u_default_texture_subdata(ctx, resource, level, usage, box,
2098 data, stride, layer_stride);
2099 }
2100
2101 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2102
2103 iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
2104
2105 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
2106 if (iris_batch_references(&ice->batches[i], res->bo))
2107 iris_batch_flush(&ice->batches[i]);
2108 }
2109
2110 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
2111
2112 for (int s = 0; s < box->depth; s++) {
2113 const uint8_t *src = data + s * layer_stride;
2114
2115 if (surf->tiling == ISL_TILING_W) {
2116 unsigned x0_el, y0_el;
2117 get_image_offset_el(surf, level, box->z + s, &x0_el, &y0_el);
2118
2119 for (unsigned y = 0; y < box->height; y++) {
2120 for (unsigned x = 0; x < box->width; x++) {
2121 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
2122 x0_el + box->x + x,
2123 y0_el + box->y + y);
2124 dst[offset] = src[y * stride + x];
2125 }
2126 }
2127 } else {
2128 unsigned x1, x2, y1, y2;
2129
2130 tile_extents(surf, box, level, s, &x1, &x2, &y1, &y2);
2131
2132 isl_memcpy_linear_to_tiled(x1, x2, y1, y2,
2133 (void *)dst, (void *)src,
2134 surf->row_pitch_B, stride,
2135 false, surf->tiling, ISL_MEMCPY);
2136 }
2137 }
2138 }
2139
2140 /**
2141 * Mark state dirty that needs to be re-emitted when a resource is written.
2142 */
2143 void
2144 iris_dirty_for_history(struct iris_context *ice,
2145 struct iris_resource *res)
2146 {
2147 uint64_t stage_dirty = 0ull;
2148
2149 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2150 stage_dirty |= ((uint64_t)res->bind_stages)
2151 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS;
2152 }
2153
2154 ice->state.stage_dirty |= stage_dirty;
2155 }
2156
2157 /**
2158 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2159 * resource becomes visible, and any stale read cache data is invalidated.
2160 */
2161 uint32_t
2162 iris_flush_bits_for_history(struct iris_resource *res)
2163 {
2164 uint32_t flush = PIPE_CONTROL_CS_STALL;
2165
2166 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2167 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
2168 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2169 }
2170
2171 if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
2172 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2173
2174 if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
2175 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2176
2177 if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
2178 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
2179
2180 return flush;
2181 }
2182
2183 void
2184 iris_flush_and_dirty_for_history(struct iris_context *ice,
2185 struct iris_batch *batch,
2186 struct iris_resource *res,
2187 uint32_t extra_flags,
2188 const char *reason)
2189 {
2190 if (res->base.target != PIPE_BUFFER)
2191 return;
2192
2193 uint32_t flush = iris_flush_bits_for_history(res) | extra_flags;
2194
2195 iris_emit_pipe_control_flush(batch, reason, flush);
2196
2197 iris_dirty_for_history(ice, res);
2198 }
2199
2200 bool
2201 iris_resource_set_clear_color(struct iris_context *ice,
2202 struct iris_resource *res,
2203 union isl_color_value color)
2204 {
2205 if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
2206 res->aux.clear_color = color;
2207 return true;
2208 }
2209
2210 return false;
2211 }
2212
2213 union isl_color_value
2214 iris_resource_get_clear_color(const struct iris_resource *res,
2215 struct iris_bo **clear_color_bo,
2216 uint64_t *clear_color_offset)
2217 {
2218 assert(res->aux.bo);
2219
2220 if (clear_color_bo)
2221 *clear_color_bo = res->aux.clear_color_bo;
2222 if (clear_color_offset)
2223 *clear_color_offset = res->aux.clear_color_offset;
2224 return res->aux.clear_color;
2225 }
2226
2227 static enum pipe_format
2228 iris_resource_get_internal_format(struct pipe_resource *p_res)
2229 {
2230 struct iris_resource *res = (void *) p_res;
2231 return res->internal_format;
2232 }
2233
2234 static const struct u_transfer_vtbl transfer_vtbl = {
2235 .resource_create = iris_resource_create,
2236 .resource_destroy = iris_resource_destroy,
2237 .transfer_map = iris_transfer_map,
2238 .transfer_unmap = iris_transfer_unmap,
2239 .transfer_flush_region = iris_transfer_flush_region,
2240 .get_internal_format = iris_resource_get_internal_format,
2241 .set_stencil = iris_resource_set_separate_stencil,
2242 .get_stencil = iris_resource_get_separate_stencil,
2243 };
2244
2245 void
2246 iris_init_screen_resource_functions(struct pipe_screen *pscreen)
2247 {
2248 pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
2249 pscreen->resource_create_with_modifiers =
2250 iris_resource_create_with_modifiers;
2251 pscreen->resource_create = u_transfer_helper_resource_create;
2252 pscreen->resource_from_user_memory = iris_resource_from_user_memory;
2253 pscreen->resource_from_handle = iris_resource_from_handle;
2254 pscreen->resource_get_handle = iris_resource_get_handle;
2255 pscreen->resource_get_param = iris_resource_get_param;
2256 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
2257 pscreen->transfer_helper =
2258 u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
2259 }
2260
2261 void
2262 iris_init_resource_functions(struct pipe_context *ctx)
2263 {
2264 ctx->flush_resource = iris_flush_resource;
2265 ctx->invalidate_resource = iris_invalidate_resource;
2266 ctx->transfer_map = u_transfer_helper_transfer_map;
2267 ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
2268 ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
2269 ctx->buffer_subdata = u_default_buffer_subdata;
2270 ctx->texture_subdata = iris_texture_subdata;
2271 }