iris/resource: Fall back to no aux if creation fails
[mesa.git] / src / gallium / drivers / iris / iris_resource.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_resource.c
25 *
26 * Resources are images, buffers, and other objects used by the GPU.
27 *
28 * XXX: explain resources
29 */
30
31 #include <stdio.h>
32 #include <errno.h>
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
51 #include "isl/isl.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
54
55 enum modifier_priority {
56 MODIFIER_PRIORITY_INVALID = 0,
57 MODIFIER_PRIORITY_LINEAR,
58 MODIFIER_PRIORITY_X,
59 MODIFIER_PRIORITY_Y,
60 MODIFIER_PRIORITY_Y_CCS,
61 };
62
63 static const uint64_t priority_to_modifier[] = {
64 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
65 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
66 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
67 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
68 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
69 };
70
71 static bool
72 modifier_is_supported(const struct gen_device_info *devinfo,
73 uint64_t modifier)
74 {
75 /* XXX: do something real */
76 switch (modifier) {
77 case I915_FORMAT_MOD_Y_TILED:
78 case I915_FORMAT_MOD_X_TILED:
79 case DRM_FORMAT_MOD_LINEAR:
80 return true;
81 case I915_FORMAT_MOD_Y_TILED_CCS:
82 case DRM_FORMAT_MOD_INVALID:
83 default:
84 return false;
85 }
86 }
87
88 static uint64_t
89 select_best_modifier(struct gen_device_info *devinfo,
90 const uint64_t *modifiers,
91 int count)
92 {
93 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
94
95 for (int i = 0; i < count; i++) {
96 if (!modifier_is_supported(devinfo, modifiers[i]))
97 continue;
98
99 switch (modifiers[i]) {
100 case I915_FORMAT_MOD_Y_TILED_CCS:
101 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
102 break;
103 case I915_FORMAT_MOD_Y_TILED:
104 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
105 break;
106 case I915_FORMAT_MOD_X_TILED:
107 prio = MAX2(prio, MODIFIER_PRIORITY_X);
108 break;
109 case DRM_FORMAT_MOD_LINEAR:
110 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
111 break;
112 case DRM_FORMAT_MOD_INVALID:
113 default:
114 break;
115 }
116 }
117
118 return priority_to_modifier[prio];
119 }
120
121 static enum isl_surf_dim
122 target_to_isl_surf_dim(enum pipe_texture_target target)
123 {
124 switch (target) {
125 case PIPE_BUFFER:
126 case PIPE_TEXTURE_1D:
127 case PIPE_TEXTURE_1D_ARRAY:
128 return ISL_SURF_DIM_1D;
129 case PIPE_TEXTURE_2D:
130 case PIPE_TEXTURE_CUBE:
131 case PIPE_TEXTURE_RECT:
132 case PIPE_TEXTURE_2D_ARRAY:
133 case PIPE_TEXTURE_CUBE_ARRAY:
134 return ISL_SURF_DIM_2D;
135 case PIPE_TEXTURE_3D:
136 return ISL_SURF_DIM_3D;
137 case PIPE_MAX_TEXTURE_TYPES:
138 break;
139 }
140 unreachable("invalid texture type");
141 }
142
143 static void
144 iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
145 enum pipe_format pfmt,
146 int max,
147 uint64_t *modifiers,
148 unsigned int *external_only,
149 int *count)
150 {
151 struct iris_screen *screen = (void *) pscreen;
152 const struct gen_device_info *devinfo = &screen->devinfo;
153
154 uint64_t all_modifiers[] = {
155 DRM_FORMAT_MOD_LINEAR,
156 I915_FORMAT_MOD_X_TILED,
157 I915_FORMAT_MOD_Y_TILED,
158 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
159 };
160
161 int supported_mods = 0;
162
163 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
164 if (!modifier_is_supported(devinfo, all_modifiers[i]))
165 continue;
166
167 if (supported_mods < max) {
168 if (modifiers)
169 modifiers[supported_mods] = all_modifiers[i];
170
171 if (external_only)
172 external_only[supported_mods] = util_format_is_yuv(pfmt);
173 }
174
175 supported_mods++;
176 }
177
178 *count = supported_mods;
179 }
180
181 static isl_surf_usage_flags_t
182 pipe_bind_to_isl_usage(unsigned bindings)
183 {
184 isl_surf_usage_flags_t usage = 0;
185
186 if (bindings & PIPE_BIND_RENDER_TARGET)
187 usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
188
189 if (bindings & PIPE_BIND_SAMPLER_VIEW)
190 usage |= ISL_SURF_USAGE_TEXTURE_BIT;
191
192 if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
193 usage |= ISL_SURF_USAGE_STORAGE_BIT;
194
195 if (bindings & PIPE_BIND_DISPLAY_TARGET)
196 usage |= ISL_SURF_USAGE_DISPLAY_BIT;
197
198 return usage;
199 }
200
201 struct pipe_resource *
202 iris_resource_get_separate_stencil(struct pipe_resource *p_res)
203 {
204 /* For packed depth-stencil, we treat depth as the primary resource
205 * and store S8 as the "second plane" resource.
206 */
207 return p_res->next;
208 }
209
210 static void
211 iris_resource_set_separate_stencil(struct pipe_resource *p_res,
212 struct pipe_resource *stencil)
213 {
214 assert(util_format_has_depth(util_format_description(p_res->format)));
215 pipe_resource_reference(&p_res->next, stencil);
216 }
217
218 void
219 iris_get_depth_stencil_resources(struct pipe_resource *res,
220 struct iris_resource **out_z,
221 struct iris_resource **out_s)
222 {
223 if (!res) {
224 *out_z = NULL;
225 *out_s = NULL;
226 return;
227 }
228
229 if (res->format != PIPE_FORMAT_S8_UINT) {
230 *out_z = (void *) res;
231 *out_s = (void *) iris_resource_get_separate_stencil(res);
232 } else {
233 *out_z = NULL;
234 *out_s = (void *) res;
235 }
236 }
237
238 void
239 iris_resource_disable_aux(struct iris_resource *res)
240 {
241 iris_bo_unreference(res->aux.bo);
242 iris_bo_unreference(res->aux.clear_color_bo);
243 free(res->aux.state);
244
245 res->aux.usage = ISL_AUX_USAGE_NONE;
246 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
247 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
248 res->aux.surf.size_B = 0;
249 res->aux.bo = NULL;
250 res->aux.clear_color_bo = NULL;
251 res->aux.state = NULL;
252 }
253
254 static void
255 iris_resource_destroy(struct pipe_screen *screen,
256 struct pipe_resource *resource)
257 {
258 struct iris_resource *res = (struct iris_resource *)resource;
259
260 if (resource->target == PIPE_BUFFER)
261 util_range_destroy(&res->valid_buffer_range);
262
263 iris_resource_disable_aux(res);
264
265 iris_bo_unreference(res->bo);
266 free(res);
267 }
268
269 static struct iris_resource *
270 iris_alloc_resource(struct pipe_screen *pscreen,
271 const struct pipe_resource *templ)
272 {
273 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
274 if (!res)
275 return NULL;
276
277 res->base = *templ;
278 res->base.screen = pscreen;
279 pipe_reference_init(&res->base.reference, 1);
280
281 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
282 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
283
284 if (templ->target == PIPE_BUFFER)
285 util_range_init(&res->valid_buffer_range);
286
287 return res;
288 }
289
290 unsigned
291 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
292 {
293 if (res->surf.dim == ISL_SURF_DIM_3D)
294 return minify(res->surf.logical_level0_px.depth, level);
295 else
296 return res->surf.logical_level0_px.array_len;
297 }
298
299 static enum isl_aux_state **
300 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
301 {
302 uint32_t total_slices = 0;
303 for (uint32_t level = 0; level < res->surf.levels; level++)
304 total_slices += iris_get_num_logical_layers(res, level);
305
306 const size_t per_level_array_size =
307 res->surf.levels * sizeof(enum isl_aux_state *);
308
309 /* We're going to allocate a single chunk of data for both the per-level
310 * reference array and the arrays of aux_state. This makes cleanup
311 * significantly easier.
312 */
313 const size_t total_size =
314 per_level_array_size + total_slices * sizeof(enum isl_aux_state);
315
316 void *data = malloc(total_size);
317 if (!data)
318 return NULL;
319
320 enum isl_aux_state **per_level_arr = data;
321 enum isl_aux_state *s = data + per_level_array_size;
322 for (uint32_t level = 0; level < res->surf.levels; level++) {
323 per_level_arr[level] = s;
324 const unsigned level_layers = iris_get_num_logical_layers(res, level);
325 for (uint32_t a = 0; a < level_layers; a++)
326 *(s++) = initial;
327 }
328 assert((void *)s == data + total_size);
329
330 return per_level_arr;
331 }
332
333 /**
334 * Allocate the initial aux surface for a resource based on aux.usage
335 */
336 static bool
337 iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res)
338 {
339 struct isl_device *isl_dev = &screen->isl_dev;
340 enum isl_aux_state initial_state;
341 UNUSED bool ok = false;
342 uint8_t memset_value = 0;
343 uint32_t alloc_flags = 0;
344 const struct gen_device_info *devinfo = &screen->devinfo;
345 const unsigned clear_color_state_size = devinfo->gen >= 10 ?
346 screen->isl_dev.ss.clear_color_state_size :
347 (devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0);
348
349 assert(!res->aux.bo);
350
351 switch (res->aux.usage) {
352 case ISL_AUX_USAGE_NONE:
353 res->aux.surf.size_B = 0;
354 ok = true;
355 break;
356 case ISL_AUX_USAGE_HIZ:
357 initial_state = ISL_AUX_STATE_AUX_INVALID;
358 memset_value = 0;
359 ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf);
360 break;
361 case ISL_AUX_USAGE_MCS:
362 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
363 *
364 * "When MCS buffer is enabled and bound to MSRT, it is required
365 * that it is cleared prior to any rendering."
366 *
367 * Since we only use the MCS buffer for rendering, we just clear it
368 * immediately on allocation. The clear value for MCS buffers is all
369 * 1's, so we simply memset it to 0xff.
370 */
371 initial_state = ISL_AUX_STATE_CLEAR;
372 memset_value = 0xFF;
373 ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf);
374 break;
375 case ISL_AUX_USAGE_CCS_D:
376 case ISL_AUX_USAGE_CCS_E:
377 /* When CCS_E is used, we need to ensure that the CCS starts off in
378 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
379 * Target(s)":
380 *
381 * "If Software wants to enable Color Compression without Fast
382 * clear, Software needs to initialize MCS with zeros."
383 *
384 * A CCS value of 0 indicates that the corresponding block is in the
385 * pass-through state which is what we want.
386 *
387 * For CCS_D, do the same thing. On Gen9+, this avoids having any
388 * undefined bits in the aux buffer.
389 */
390 initial_state = ISL_AUX_STATE_PASS_THROUGH;
391 alloc_flags |= BO_ALLOC_ZEROED;
392 ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0);
393 break;
394 }
395
396 /* We should have a valid aux_surf. */
397 if (!ok)
398 return false;
399
400 /* No work is needed for a zero-sized auxiliary buffer. */
401 if (res->aux.surf.size_B == 0)
402 return true;
403
404 /* Create the aux_state for the auxiliary buffer. */
405 res->aux.state = create_aux_state_map(res, initial_state);
406 if (!res->aux.state)
407 return false;
408
409 uint64_t size = res->aux.surf.size_B;
410
411 /* Allocate space in the buffer for storing the clear color. On modern
412 * platforms (gen > 9), we can read it directly from such buffer.
413 *
414 * On gen <= 9, we are going to store the clear color on the buffer
415 * anyways, and copy it back to the surface state during state emission.
416 */
417 res->aux.clear_color_offset = size;
418 size += clear_color_state_size;
419
420 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
421 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
422 * of bytes instead of trying to recalculate based on different format
423 * block sizes.
424 */
425 res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size,
426 IRIS_MEMZONE_OTHER, I915_TILING_Y,
427 res->aux.surf.row_pitch_B, alloc_flags);
428 if (!res->aux.bo) {
429 return false;
430 }
431
432 if (!(alloc_flags & BO_ALLOC_ZEROED)) {
433 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
434
435 if (!map) {
436 iris_resource_disable_aux(res);
437 return false;
438 }
439
440 if (memset_value != 0)
441 memset(map, memset_value, res->aux.surf.size_B);
442
443 /* Zero the indirect clear color to match ::fast_clear_color. */
444 memset((char *)map + res->aux.clear_color_offset, 0,
445 clear_color_state_size);
446
447 iris_bo_unmap(res->aux.bo);
448 }
449
450 if (clear_color_state_size > 0) {
451 res->aux.clear_color_bo = res->aux.bo;
452 iris_bo_reference(res->aux.clear_color_bo);
453 }
454
455 if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
456 for (unsigned level = 0; level < res->surf.levels; ++level) {
457 uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
458 uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
459
460 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
461 * For LOD == 0, we can grow the dimensions to make it work.
462 */
463 if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
464 res->aux.has_hiz |= 1 << level;
465 }
466 }
467
468 return true;
469 }
470
471 static bool
472 supports_mcs(const struct isl_surf *surf)
473 {
474 /* MCS compression only applies to multisampled resources. */
475 if (surf->samples <= 1)
476 return false;
477
478 /* See isl_surf_get_mcs_surf for details. */
479 if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
480 return false;
481
482 /* Depth and stencil buffers use the IMS (interleaved) layout. */
483 if (isl_surf_usage_is_depth_or_stencil(surf->usage))
484 return false;
485
486 return true;
487 }
488
489 static bool
490 supports_ccs(const struct gen_device_info *devinfo,
491 const struct isl_surf *surf)
492 {
493 /* Gen9+ only supports CCS for Y-tiled buffers. */
494 if (surf->tiling != ISL_TILING_Y0)
495 return false;
496
497 /* CCS only supports singlesampled resources. */
498 if (surf->samples > 1)
499 return false;
500
501 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
502 * work for 3D textures until Gen9 where the layout of 3D textures changes
503 * to match 2D array textures.
504 */
505 if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D)
506 return false;
507
508 /* Note: still need to check the format! */
509
510 return true;
511 }
512
513 static struct pipe_resource *
514 iris_resource_create_for_buffer(struct pipe_screen *pscreen,
515 const struct pipe_resource *templ)
516 {
517 struct iris_screen *screen = (struct iris_screen *)pscreen;
518 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
519
520 assert(templ->target == PIPE_BUFFER);
521 assert(templ->height0 <= 1);
522 assert(templ->depth0 <= 1);
523 assert(templ->format == PIPE_FORMAT_NONE ||
524 util_format_get_blocksize(templ->format) == 1);
525
526 res->internal_format = templ->format;
527 res->surf.tiling = ISL_TILING_LINEAR;
528
529 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
530 const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
531 if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
532 memzone = IRIS_MEMZONE_SHADER;
533 name = "shader kernels";
534 } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
535 memzone = IRIS_MEMZONE_SURFACE;
536 name = "surface state";
537 } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
538 memzone = IRIS_MEMZONE_DYNAMIC;
539 name = "dynamic state";
540 }
541
542 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
543 if (!res->bo) {
544 iris_resource_destroy(pscreen, &res->base);
545 return NULL;
546 }
547
548 return &res->base;
549 }
550
551 static struct pipe_resource *
552 iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
553 const struct pipe_resource *templ,
554 const uint64_t *modifiers,
555 int modifiers_count)
556 {
557 struct iris_screen *screen = (struct iris_screen *)pscreen;
558 struct gen_device_info *devinfo = &screen->devinfo;
559 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
560
561 if (!res)
562 return NULL;
563
564 const struct util_format_description *format_desc =
565 util_format_description(templ->format);
566 const bool has_depth = util_format_has_depth(format_desc);
567 uint64_t modifier =
568 select_best_modifier(devinfo, modifiers, modifiers_count);
569
570 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
571
572 if (modifier != DRM_FORMAT_MOD_INVALID) {
573 res->mod_info = isl_drm_modifier_get_info(modifier);
574
575 tiling_flags = 1 << res->mod_info->tiling;
576 } else {
577 if (modifiers_count > 0) {
578 fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
579 return NULL;
580 }
581
582 /* No modifiers - we can select our own tiling. */
583
584 if (has_depth) {
585 /* Depth must be Y-tiled */
586 tiling_flags = ISL_TILING_Y0_BIT;
587 } else if (templ->format == PIPE_FORMAT_S8_UINT) {
588 /* Stencil must be W-tiled */
589 tiling_flags = ISL_TILING_W_BIT;
590 } else if (templ->target == PIPE_BUFFER ||
591 templ->target == PIPE_TEXTURE_1D ||
592 templ->target == PIPE_TEXTURE_1D_ARRAY) {
593 /* Use linear for buffers and 1D textures */
594 tiling_flags = ISL_TILING_LINEAR_BIT;
595 }
596
597 /* Use linear for staging buffers */
598 if (templ->usage == PIPE_USAGE_STAGING ||
599 templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
600 tiling_flags = ISL_TILING_LINEAR_BIT;
601 }
602
603 isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
604
605 if (templ->target == PIPE_TEXTURE_CUBE ||
606 templ->target == PIPE_TEXTURE_CUBE_ARRAY)
607 usage |= ISL_SURF_USAGE_CUBE_BIT;
608
609 if (templ->usage != PIPE_USAGE_STAGING) {
610 if (templ->format == PIPE_FORMAT_S8_UINT)
611 usage |= ISL_SURF_USAGE_STENCIL_BIT;
612 else if (has_depth)
613 usage |= ISL_SURF_USAGE_DEPTH_BIT;
614 }
615
616 enum pipe_format pfmt = templ->format;
617 res->internal_format = pfmt;
618
619 /* Should be handled by u_transfer_helper */
620 assert(!util_format_is_depth_and_stencil(pfmt));
621
622 struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
623 assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
624
625 UNUSED const bool isl_surf_created_successfully =
626 isl_surf_init(&screen->isl_dev, &res->surf,
627 .dim = target_to_isl_surf_dim(templ->target),
628 .format = fmt.fmt,
629 .width = templ->width0,
630 .height = templ->height0,
631 .depth = templ->depth0,
632 .levels = templ->last_level + 1,
633 .array_len = templ->array_size,
634 .samples = MAX2(templ->nr_samples, 1),
635 .min_alignment_B = 0,
636 .row_pitch_B = 0,
637 .usage = usage,
638 .tiling_flags = tiling_flags);
639 assert(isl_surf_created_successfully);
640
641 if (res->mod_info) {
642 res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
643 } else if (supports_mcs(&res->surf)) {
644 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS;
645 } else if (has_depth) {
646 if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ)))
647 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
648 } else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) &&
649 supports_ccs(devinfo, &res->surf)) {
650 if (isl_format_supports_ccs_e(devinfo, res->surf.format))
651 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
652
653 if (isl_format_supports_ccs_d(devinfo, res->surf.format))
654 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
655 }
656
657 res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
658
659 res->aux.sampler_usages = res->aux.possible_usages;
660
661 /* We don't always support sampling with hiz. But when we do, it must be
662 * single sampled.
663 */
664 if (!devinfo->has_sample_with_hiz || res->surf.samples > 1) {
665 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
666 }
667
668 const char *name = "miptree";
669 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
670
671 unsigned int flags = 0;
672 if (templ->usage == PIPE_USAGE_STAGING)
673 flags |= BO_ALLOC_COHERENT;
674
675 /* These are for u_upload_mgr buffers only */
676 assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
677 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
678 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
679
680 res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B,
681 memzone,
682 isl_tiling_to_i915_tiling(res->surf.tiling),
683 res->surf.row_pitch_B, flags);
684
685 if (!res->bo)
686 goto fail;
687
688 if (!iris_resource_alloc_aux(screen, res))
689 iris_resource_disable_aux(res);
690
691 return &res->base;
692
693 fail:
694 fprintf(stderr, "XXX: resource creation failed\n");
695 iris_resource_destroy(pscreen, &res->base);
696 return NULL;
697
698 }
699
700 static struct pipe_resource *
701 iris_resource_create(struct pipe_screen *pscreen,
702 const struct pipe_resource *templ)
703 {
704 if (templ->target == PIPE_BUFFER)
705 return iris_resource_create_for_buffer(pscreen, templ);
706 else
707 return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
708 }
709
710 static uint64_t
711 tiling_to_modifier(uint32_t tiling)
712 {
713 static const uint64_t map[] = {
714 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
715 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
716 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
717 };
718
719 assert(tiling < ARRAY_SIZE(map));
720
721 return map[tiling];
722 }
723
724 static struct pipe_resource *
725 iris_resource_from_user_memory(struct pipe_screen *pscreen,
726 const struct pipe_resource *templ,
727 void *user_memory)
728 {
729 struct iris_screen *screen = (struct iris_screen *)pscreen;
730 struct iris_bufmgr *bufmgr = screen->bufmgr;
731 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
732 if (!res)
733 return NULL;
734
735 assert(templ->target == PIPE_BUFFER);
736
737 res->internal_format = templ->format;
738 res->bo = iris_bo_create_userptr(bufmgr, "user",
739 user_memory, templ->width0,
740 IRIS_MEMZONE_OTHER);
741 if (!res->bo) {
742 free(res);
743 return NULL;
744 }
745
746 util_range_add(&res->valid_buffer_range, 0, templ->width0);
747
748 return &res->base;
749 }
750
751 static struct pipe_resource *
752 iris_resource_from_handle(struct pipe_screen *pscreen,
753 const struct pipe_resource *templ,
754 struct winsys_handle *whandle,
755 unsigned usage)
756 {
757 struct iris_screen *screen = (struct iris_screen *)pscreen;
758 struct gen_device_info *devinfo = &screen->devinfo;
759 struct iris_bufmgr *bufmgr = screen->bufmgr;
760 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
761 if (!res)
762 return NULL;
763
764 switch (whandle->type) {
765 case WINSYS_HANDLE_TYPE_FD:
766 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
767 break;
768 case WINSYS_HANDLE_TYPE_SHARED:
769 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
770 whandle->handle);
771 break;
772 default:
773 unreachable("invalid winsys handle type");
774 }
775 if (!res->bo)
776 return NULL;
777
778 res->offset = whandle->offset;
779
780 uint64_t modifier = whandle->modifier;
781 if (modifier == DRM_FORMAT_MOD_INVALID) {
782 modifier = tiling_to_modifier(res->bo->tiling_mode);
783 }
784 res->mod_info = isl_drm_modifier_get_info(modifier);
785 assert(res->mod_info);
786
787 isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
788
789 const struct iris_format_info fmt =
790 iris_format_for_usage(devinfo, templ->format, isl_usage);
791 res->internal_format = templ->format;
792
793 if (templ->target == PIPE_BUFFER) {
794 res->surf.tiling = ISL_TILING_LINEAR;
795 } else {
796 isl_surf_init(&screen->isl_dev, &res->surf,
797 .dim = target_to_isl_surf_dim(templ->target),
798 .format = fmt.fmt,
799 .width = templ->width0,
800 .height = templ->height0,
801 .depth = templ->depth0,
802 .levels = templ->last_level + 1,
803 .array_len = templ->array_size,
804 .samples = MAX2(templ->nr_samples, 1),
805 .min_alignment_B = 0,
806 .row_pitch_B = whandle->stride,
807 .usage = isl_usage,
808 .tiling_flags = 1 << res->mod_info->tiling);
809
810 assert(res->bo->tiling_mode ==
811 isl_tiling_to_i915_tiling(res->surf.tiling));
812
813 // XXX: create_ccs_buf_for_image?
814 if (!iris_resource_alloc_aux(screen, res))
815 goto fail;
816 }
817
818 return &res->base;
819
820 fail:
821 iris_resource_destroy(pscreen, &res->base);
822 return NULL;
823 }
824
825 static void
826 iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
827 {
828 struct iris_context *ice = (struct iris_context *)ctx;
829 struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
830 struct iris_resource *res = (void *) resource;
831 const struct isl_drm_modifier_info *mod = res->mod_info;
832
833 iris_resource_prepare_access(ice, render_batch, res,
834 0, INTEL_REMAINING_LEVELS,
835 0, INTEL_REMAINING_LAYERS,
836 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
837 mod ? mod->supports_clear_color : false);
838 }
839
840 static boolean
841 iris_resource_get_handle(struct pipe_screen *pscreen,
842 struct pipe_context *ctx,
843 struct pipe_resource *resource,
844 struct winsys_handle *whandle,
845 unsigned usage)
846 {
847 struct iris_resource *res = (struct iris_resource *)resource;
848
849 /* Disable aux usage if explicit flush not set and this is the
850 * first time we are dealing with this resource.
851 */
852 if ((!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0)) {
853 if (p_atomic_read(&resource->reference.count) == 1)
854 iris_resource_disable_aux(res);
855 }
856
857 /* If this is a buffer, stride should be 0 - no need to special case */
858 whandle->stride = res->surf.row_pitch_B;
859 whandle->modifier =
860 res->mod_info ? res->mod_info->modifier
861 : tiling_to_modifier(res->bo->tiling_mode);
862
863 #ifndef NDEBUG
864 enum isl_aux_usage allowed_usage =
865 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
866
867 if (res->aux.usage != allowed_usage) {
868 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
869 assert(aux_state == ISL_AUX_STATE_RESOLVED ||
870 aux_state == ISL_AUX_STATE_PASS_THROUGH);
871 }
872 #endif
873
874 switch (whandle->type) {
875 case WINSYS_HANDLE_TYPE_SHARED:
876 return iris_bo_flink(res->bo, &whandle->handle) == 0;
877 case WINSYS_HANDLE_TYPE_KMS:
878 whandle->handle = iris_bo_export_gem_handle(res->bo);
879 return true;
880 case WINSYS_HANDLE_TYPE_FD:
881 return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0;
882 }
883
884 return false;
885 }
886
887 static bool
888 resource_is_busy(struct iris_context *ice,
889 struct iris_resource *res)
890 {
891 bool busy = iris_bo_busy(res->bo);
892
893 for (int i = 0; i < IRIS_BATCH_COUNT; i++)
894 busy |= iris_batch_references(&ice->batches[i], res->bo);
895
896 return busy;
897 }
898
899 static void
900 iris_invalidate_resource(struct pipe_context *ctx,
901 struct pipe_resource *resource)
902 {
903 struct iris_screen *screen = (void *) ctx->screen;
904 struct iris_context *ice = (void *) ctx;
905 struct iris_resource *res = (void *) resource;
906
907 if (resource->target != PIPE_BUFFER)
908 return;
909
910 if (!resource_is_busy(ice, res)) {
911 /* The resource is idle, so just mark that it contains no data and
912 * keep using the same underlying buffer object.
913 */
914 util_range_set_empty(&res->valid_buffer_range);
915 return;
916 }
917
918 /* Otherwise, try and replace the backing storage with a new BO. */
919
920 /* We can't reallocate memory we didn't allocate in the first place. */
921 if (res->bo->userptr)
922 return;
923
924 // XXX: We should support this.
925 if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
926 return;
927
928 struct iris_bo *old_bo = res->bo;
929 struct iris_bo *new_bo =
930 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
931 iris_memzone_for_address(old_bo->gtt_offset));
932 if (!new_bo)
933 return;
934
935 /* Swap out the backing storage */
936 res->bo = new_bo;
937
938 /* Rebind the buffer, replacing any state referring to the old BO's
939 * address, and marking state dirty so it's reemitted.
940 */
941 ice->vtbl.rebind_buffer(ice, res, old_bo->gtt_offset);
942
943 util_range_set_empty(&res->valid_buffer_range);
944
945 iris_bo_unreference(old_bo);
946 }
947
948 static void
949 iris_flush_staging_region(struct pipe_transfer *xfer,
950 const struct pipe_box *flush_box)
951 {
952 if (!(xfer->usage & PIPE_TRANSFER_WRITE))
953 return;
954
955 struct iris_transfer *map = (void *) xfer;
956
957 struct pipe_box src_box = *flush_box;
958
959 /* Account for extra alignment padding in staging buffer */
960 if (xfer->resource->target == PIPE_BUFFER)
961 src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
962
963 struct pipe_box dst_box = (struct pipe_box) {
964 .x = xfer->box.x + flush_box->x,
965 .y = xfer->box.y + flush_box->y,
966 .z = xfer->box.z + flush_box->z,
967 .width = flush_box->width,
968 .height = flush_box->height,
969 .depth = flush_box->depth,
970 };
971
972 iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
973 dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
974 &src_box);
975 }
976
977 static void
978 iris_unmap_copy_region(struct iris_transfer *map)
979 {
980 iris_resource_destroy(map->staging->screen, map->staging);
981
982 map->ptr = NULL;
983 }
984
985 static void
986 iris_map_copy_region(struct iris_transfer *map)
987 {
988 struct pipe_screen *pscreen = &map->batch->screen->base;
989 struct pipe_transfer *xfer = &map->base;
990 struct pipe_box *box = &xfer->box;
991 struct iris_resource *res = (void *) xfer->resource;
992
993 unsigned extra = xfer->resource->target == PIPE_BUFFER ?
994 box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
995
996 struct pipe_resource templ = (struct pipe_resource) {
997 .usage = PIPE_USAGE_STAGING,
998 .width0 = box->width + extra,
999 .height0 = box->height,
1000 .depth0 = 1,
1001 .nr_samples = xfer->resource->nr_samples,
1002 .nr_storage_samples = xfer->resource->nr_storage_samples,
1003 .array_size = box->depth,
1004 };
1005
1006 if (xfer->resource->target == PIPE_BUFFER)
1007 templ.target = PIPE_BUFFER;
1008 else if (templ.array_size > 1)
1009 templ.target = PIPE_TEXTURE_2D_ARRAY;
1010 else
1011 templ.target = PIPE_TEXTURE_2D;
1012
1013 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
1014 * xfer->resource->format directly. Pick a bpb compatible format so
1015 * resource creation will succeed; blorp_copy will override it anyway.
1016 */
1017 switch (util_format_get_blocksizebits(res->internal_format)) {
1018 case 8: templ.format = PIPE_FORMAT_R8_UINT; break;
1019 case 16: templ.format = PIPE_FORMAT_R8G8_UINT; break;
1020 case 24: templ.format = PIPE_FORMAT_R8G8B8_UINT; break;
1021 case 32: templ.format = PIPE_FORMAT_R8G8B8A8_UINT; break;
1022 case 48: templ.format = PIPE_FORMAT_R16G16B16_UINT; break;
1023 case 64: templ.format = PIPE_FORMAT_R16G16B16A16_UINT; break;
1024 case 96: templ.format = PIPE_FORMAT_R32G32B32_UINT; break;
1025 case 128: templ.format = PIPE_FORMAT_R32G32B32A32_UINT; break;
1026 default: unreachable("Invalid bpb");
1027 }
1028
1029 map->staging = iris_resource_create(pscreen, &templ);
1030 assert(map->staging);
1031
1032 if (templ.target != PIPE_BUFFER) {
1033 struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
1034 xfer->stride = isl_surf_get_row_pitch_B(surf);
1035 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1036 }
1037
1038 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1039 iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
1040 xfer->resource, xfer->level, box);
1041 /* Ensure writes to the staging BO land before we map it below. */
1042 iris_emit_pipe_control_flush(map->batch,
1043 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1044 PIPE_CONTROL_CS_STALL);
1045 }
1046
1047 struct iris_bo *staging_bo = iris_resource_bo(map->staging);
1048
1049 if (iris_batch_references(map->batch, staging_bo))
1050 iris_batch_flush(map->batch);
1051
1052 map->ptr =
1053 iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
1054
1055 map->unmap = iris_unmap_copy_region;
1056 }
1057
1058 static void
1059 get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z,
1060 unsigned *out_x0_el, unsigned *out_y0_el)
1061 {
1062 if (surf->dim == ISL_SURF_DIM_3D) {
1063 isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
1064 } else {
1065 isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
1066 }
1067 }
1068
1069 /**
1070 * Get pointer offset into stencil buffer.
1071 *
1072 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1073 * must decode the tile's layout in software.
1074 *
1075 * See
1076 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1077 * Format.
1078 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1079 *
1080 * Even though the returned offset is always positive, the return type is
1081 * signed due to
1082 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1083 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1084 */
1085 static intptr_t
1086 s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
1087 {
1088 uint32_t tile_size = 4096;
1089 uint32_t tile_width = 64;
1090 uint32_t tile_height = 64;
1091 uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
1092
1093 uint32_t tile_x = x / tile_width;
1094 uint32_t tile_y = y / tile_height;
1095
1096 /* The byte's address relative to the tile's base addres. */
1097 uint32_t byte_x = x % tile_width;
1098 uint32_t byte_y = y % tile_height;
1099
1100 uintptr_t u = tile_y * row_size
1101 + tile_x * tile_size
1102 + 512 * (byte_x / 8)
1103 + 64 * (byte_y / 8)
1104 + 32 * ((byte_y / 4) % 2)
1105 + 16 * ((byte_x / 4) % 2)
1106 + 8 * ((byte_y / 2) % 2)
1107 + 4 * ((byte_x / 2) % 2)
1108 + 2 * (byte_y % 2)
1109 + 1 * (byte_x % 2);
1110
1111 if (swizzled) {
1112 /* adjust for bit6 swizzling */
1113 if (((byte_x / 8) % 2) == 1) {
1114 if (((byte_y / 8) % 2) == 0) {
1115 u += 64;
1116 } else {
1117 u -= 64;
1118 }
1119 }
1120 }
1121
1122 return u;
1123 }
1124
1125 static void
1126 iris_unmap_s8(struct iris_transfer *map)
1127 {
1128 struct pipe_transfer *xfer = &map->base;
1129 const struct pipe_box *box = &xfer->box;
1130 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1131 struct isl_surf *surf = &res->surf;
1132 const bool has_swizzling = false;
1133
1134 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1135 uint8_t *untiled_s8_map = map->ptr;
1136 uint8_t *tiled_s8_map =
1137 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1138
1139 for (int s = 0; s < box->depth; s++) {
1140 unsigned x0_el, y0_el;
1141 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1142
1143 for (uint32_t y = 0; y < box->height; y++) {
1144 for (uint32_t x = 0; x < box->width; x++) {
1145 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1146 x0_el + box->x + x,
1147 y0_el + box->y + y,
1148 has_swizzling);
1149 tiled_s8_map[offset] =
1150 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
1151 }
1152 }
1153 }
1154 }
1155
1156 free(map->buffer);
1157 }
1158
1159 static void
1160 iris_map_s8(struct iris_transfer *map)
1161 {
1162 struct pipe_transfer *xfer = &map->base;
1163 const struct pipe_box *box = &xfer->box;
1164 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1165 struct isl_surf *surf = &res->surf;
1166
1167 xfer->stride = surf->row_pitch_B;
1168 xfer->layer_stride = xfer->stride * box->height;
1169
1170 /* The tiling and detiling functions require that the linear buffer has
1171 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1172 * over-allocate the linear buffer to get the proper alignment.
1173 */
1174 map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
1175 assert(map->buffer);
1176
1177 const bool has_swizzling = false;
1178
1179 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1180 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1181 * invalidate is set, since we'll be writing the whole rectangle from our
1182 * temporary buffer back out.
1183 */
1184 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1185 uint8_t *untiled_s8_map = map->ptr;
1186 uint8_t *tiled_s8_map =
1187 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1188
1189 for (int s = 0; s < box->depth; s++) {
1190 unsigned x0_el, y0_el;
1191 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1192
1193 for (uint32_t y = 0; y < box->height; y++) {
1194 for (uint32_t x = 0; x < box->width; x++) {
1195 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1196 x0_el + box->x + x,
1197 y0_el + box->y + y,
1198 has_swizzling);
1199 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
1200 tiled_s8_map[offset];
1201 }
1202 }
1203 }
1204 }
1205
1206 map->unmap = iris_unmap_s8;
1207 }
1208
1209 /* Compute extent parameters for use with tiled_memcpy functions.
1210 * xs are in units of bytes and ys are in units of strides.
1211 */
1212 static inline void
1213 tile_extents(const struct isl_surf *surf,
1214 const struct pipe_box *box,
1215 unsigned level, int z,
1216 unsigned *x1_B, unsigned *x2_B,
1217 unsigned *y1_el, unsigned *y2_el)
1218 {
1219 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1220 const unsigned cpp = fmtl->bpb / 8;
1221
1222 assert(box->x % fmtl->bw == 0);
1223 assert(box->y % fmtl->bh == 0);
1224
1225 unsigned x0_el, y0_el;
1226 get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
1227
1228 *x1_B = (box->x / fmtl->bw + x0_el) * cpp;
1229 *y1_el = box->y / fmtl->bh + y0_el;
1230 *x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
1231 *y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
1232 }
1233
1234 static void
1235 iris_unmap_tiled_memcpy(struct iris_transfer *map)
1236 {
1237 struct pipe_transfer *xfer = &map->base;
1238 const struct pipe_box *box = &xfer->box;
1239 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1240 struct isl_surf *surf = &res->surf;
1241
1242 const bool has_swizzling = false;
1243
1244 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1245 char *dst =
1246 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1247
1248 for (int s = 0; s < box->depth; s++) {
1249 unsigned x1, x2, y1, y2;
1250 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1251
1252 void *ptr = map->ptr + s * xfer->layer_stride;
1253
1254 isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
1255 surf->row_pitch_B, xfer->stride,
1256 has_swizzling, surf->tiling, ISL_MEMCPY);
1257 }
1258 }
1259 os_free_aligned(map->buffer);
1260 map->buffer = map->ptr = NULL;
1261 }
1262
1263 static void
1264 iris_map_tiled_memcpy(struct iris_transfer *map)
1265 {
1266 struct pipe_transfer *xfer = &map->base;
1267 const struct pipe_box *box = &xfer->box;
1268 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1269 struct isl_surf *surf = &res->surf;
1270
1271 xfer->stride = ALIGN(surf->row_pitch_B, 16);
1272 xfer->layer_stride = xfer->stride * box->height;
1273
1274 unsigned x1, x2, y1, y2;
1275 tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
1276
1277 /* The tiling and detiling functions require that the linear buffer has
1278 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1279 * over-allocate the linear buffer to get the proper alignment.
1280 */
1281 map->buffer =
1282 os_malloc_aligned(xfer->layer_stride * box->depth, 16);
1283 assert(map->buffer);
1284 map->ptr = (char *)map->buffer + (x1 & 0xf);
1285
1286 const bool has_swizzling = false;
1287
1288 // XXX: PIPE_TRANSFER_READ?
1289 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1290 char *src =
1291 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1292
1293 for (int s = 0; s < box->depth; s++) {
1294 unsigned x1, x2, y1, y2;
1295 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1296
1297 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1298 void *ptr = map->ptr + s * xfer->layer_stride;
1299
1300 isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
1301 surf->row_pitch_B, has_swizzling,
1302 surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
1303 }
1304 }
1305
1306 map->unmap = iris_unmap_tiled_memcpy;
1307 }
1308
1309 static void
1310 iris_map_direct(struct iris_transfer *map)
1311 {
1312 struct pipe_transfer *xfer = &map->base;
1313 struct pipe_box *box = &xfer->box;
1314 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1315
1316 void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
1317
1318 if (res->base.target == PIPE_BUFFER) {
1319 xfer->stride = 0;
1320 xfer->layer_stride = 0;
1321
1322 map->ptr = ptr + box->x;
1323 } else {
1324 struct isl_surf *surf = &res->surf;
1325 const struct isl_format_layout *fmtl =
1326 isl_format_get_layout(surf->format);
1327 const unsigned cpp = fmtl->bpb / 8;
1328 unsigned x0_el, y0_el;
1329
1330 get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
1331
1332 xfer->stride = isl_surf_get_row_pitch_B(surf);
1333 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1334
1335 map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
1336 }
1337 }
1338
1339 static bool
1340 can_promote_to_async(const struct iris_resource *res,
1341 const struct pipe_box *box,
1342 enum pipe_transfer_usage usage)
1343 {
1344 /* If we're writing to a section of the buffer that hasn't even been
1345 * initialized with useful data, then we can safely promote this write
1346 * to be unsynchronized. This helps the common pattern of appending data.
1347 */
1348 return res->base.target == PIPE_BUFFER && (usage & PIPE_TRANSFER_WRITE) &&
1349 !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
1350 !util_ranges_intersect(&res->valid_buffer_range, box->x,
1351 box->x + box->width);
1352 }
1353
1354 static void *
1355 iris_transfer_map(struct pipe_context *ctx,
1356 struct pipe_resource *resource,
1357 unsigned level,
1358 enum pipe_transfer_usage usage,
1359 const struct pipe_box *box,
1360 struct pipe_transfer **ptransfer)
1361 {
1362 struct iris_context *ice = (struct iris_context *)ctx;
1363 struct iris_resource *res = (struct iris_resource *)resource;
1364 struct isl_surf *surf = &res->surf;
1365
1366 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
1367 /* Replace the backing storage with a fresh buffer for non-async maps */
1368 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
1369 TC_TRANSFER_MAP_NO_INVALIDATE)))
1370 iris_invalidate_resource(ctx, resource);
1371
1372 /* If we can discard the whole resource, we can discard the range. */
1373 usage |= PIPE_TRANSFER_DISCARD_RANGE;
1374 }
1375
1376 bool map_would_stall = false;
1377
1378 if (resource->target != PIPE_BUFFER) {
1379 iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res,
1380 level, box->z, box->depth,
1381 usage & PIPE_TRANSFER_WRITE);
1382 }
1383
1384 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
1385 can_promote_to_async(res, box, usage)) {
1386 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1387 }
1388
1389 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1390 map_would_stall = resource_is_busy(ice, res);
1391
1392 if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
1393 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1394 return NULL;
1395 }
1396
1397 if (surf->tiling != ISL_TILING_LINEAR &&
1398 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1399 return NULL;
1400
1401 struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
1402 struct pipe_transfer *xfer = &map->base;
1403
1404 if (!map)
1405 return NULL;
1406
1407 memset(map, 0, sizeof(*map));
1408 map->dbg = &ice->dbg;
1409
1410 pipe_resource_reference(&xfer->resource, resource);
1411 xfer->level = level;
1412 xfer->usage = usage;
1413 xfer->box = *box;
1414 *ptransfer = xfer;
1415
1416 if (usage & PIPE_TRANSFER_WRITE)
1417 util_range_add(&res->valid_buffer_range, box->x, box->x + box->width);
1418
1419 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1420 * there is to access them simultaneously on the CPU & GPU. This also
1421 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1422 * contain state we're constructing for a GPU draw call, which would
1423 * kill us with infinite stack recursion.
1424 */
1425 bool no_gpu = usage & (PIPE_TRANSFER_PERSISTENT |
1426 PIPE_TRANSFER_COHERENT |
1427 PIPE_TRANSFER_MAP_DIRECTLY);
1428
1429 /* GPU copies are not useful for buffer reads. Instead of stalling to
1430 * read from the original buffer, we'd simply copy it to a temporary...
1431 * then stall (a bit longer) to read from that buffer.
1432 *
1433 * Images are less clear-cut. Color resolves are destructive, removing
1434 * the underlying compression, so we'd rather blit the data to a linear
1435 * temporary and map that, to avoid the resolve. (It might be better to
1436 * a tiled temporary and use the tiled_memcpy paths...)
1437 */
1438 if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) &&
1439 res->aux.usage != ISL_AUX_USAGE_CCS_E &&
1440 res->aux.usage != ISL_AUX_USAGE_CCS_D) {
1441 no_gpu = true;
1442 }
1443
1444 if ((map_would_stall || res->aux.usage == ISL_AUX_USAGE_CCS_E) && !no_gpu) {
1445 /* If we need a synchronous mapping and the resource is busy,
1446 * we copy to/from a linear temporary buffer using the GPU.
1447 */
1448 map->batch = &ice->batches[IRIS_BATCH_RENDER];
1449 map->blorp = &ice->blorp;
1450 iris_map_copy_region(map);
1451 } else {
1452 /* Otherwise we're free to map on the CPU. Flush if needed. */
1453 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1454 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1455 if (iris_batch_references(&ice->batches[i], res->bo))
1456 iris_batch_flush(&ice->batches[i]);
1457 }
1458 }
1459
1460 if (surf->tiling == ISL_TILING_W) {
1461 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1462 iris_map_s8(map);
1463 } else if (surf->tiling != ISL_TILING_LINEAR) {
1464 iris_map_tiled_memcpy(map);
1465 } else {
1466 iris_map_direct(map);
1467 }
1468 }
1469
1470 return map->ptr;
1471 }
1472
1473 static void
1474 iris_transfer_flush_region(struct pipe_context *ctx,
1475 struct pipe_transfer *xfer,
1476 const struct pipe_box *box)
1477 {
1478 struct iris_context *ice = (struct iris_context *)ctx;
1479 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1480 struct iris_transfer *map = (void *) xfer;
1481
1482 if (map->staging)
1483 iris_flush_staging_region(xfer, box);
1484
1485 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1486 if (ice->batches[i].contains_draw ||
1487 ice->batches[i].cache.render->entries) {
1488 iris_batch_maybe_flush(&ice->batches[i], 24);
1489 iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
1490 }
1491 }
1492
1493 /* Make sure we flag constants dirty even if there's no need to emit
1494 * any PIPE_CONTROLs to a batch.
1495 */
1496 iris_dirty_for_history(ice, res);
1497 }
1498
1499 static void
1500 iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
1501 {
1502 struct iris_context *ice = (struct iris_context *)ctx;
1503 struct iris_transfer *map = (void *) xfer;
1504
1505 if (!(xfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) {
1506 struct pipe_box flush_box = {
1507 .x = 0, .y = 0, .z = 0,
1508 .width = xfer->box.width,
1509 .height = xfer->box.height,
1510 .depth = xfer->box.depth,
1511 };
1512 iris_transfer_flush_region(ctx, xfer, &flush_box);
1513 }
1514
1515 if (map->unmap)
1516 map->unmap(map);
1517
1518 pipe_resource_reference(&xfer->resource, NULL);
1519 slab_free(&ice->transfer_pool, map);
1520 }
1521
1522 /**
1523 * Mark state dirty that needs to be re-emitted when a resource is written.
1524 */
1525 void
1526 iris_dirty_for_history(struct iris_context *ice,
1527 struct iris_resource *res)
1528 {
1529 uint64_t dirty = 0ull;
1530
1531 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1532 dirty |= IRIS_DIRTY_CONSTANTS_VS |
1533 IRIS_DIRTY_CONSTANTS_TCS |
1534 IRIS_DIRTY_CONSTANTS_TES |
1535 IRIS_DIRTY_CONSTANTS_GS |
1536 IRIS_DIRTY_CONSTANTS_FS |
1537 IRIS_DIRTY_CONSTANTS_CS |
1538 IRIS_ALL_DIRTY_BINDINGS;
1539 }
1540
1541 ice->state.dirty |= dirty;
1542 }
1543
1544 /**
1545 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1546 * resource becomes visible, and any stale read cache data is invalidated.
1547 */
1548 uint32_t
1549 iris_flush_bits_for_history(struct iris_resource *res)
1550 {
1551 uint32_t flush = PIPE_CONTROL_CS_STALL;
1552
1553 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1554 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
1555 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1556 }
1557
1558 if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
1559 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1560
1561 if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
1562 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1563
1564 if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
1565 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
1566
1567 return flush;
1568 }
1569
1570 void
1571 iris_flush_and_dirty_for_history(struct iris_context *ice,
1572 struct iris_batch *batch,
1573 struct iris_resource *res)
1574 {
1575 if (res->base.target != PIPE_BUFFER)
1576 return;
1577
1578 uint32_t flush = iris_flush_bits_for_history(res);
1579
1580 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1581 * surface. Flush the render cache so the data actually lands.
1582 */
1583 if (batch->name != IRIS_BATCH_COMPUTE)
1584 flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
1585
1586 iris_emit_pipe_control_flush(batch, flush);
1587 }
1588
1589 bool
1590 iris_resource_set_clear_color(struct iris_context *ice,
1591 struct iris_resource *res,
1592 union isl_color_value color)
1593 {
1594 if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
1595 res->aux.clear_color = color;
1596 return true;
1597 }
1598
1599 return false;
1600 }
1601
1602 union isl_color_value
1603 iris_resource_get_clear_color(const struct iris_resource *res,
1604 struct iris_bo **clear_color_bo,
1605 uint64_t *clear_color_offset)
1606 {
1607 assert(res->aux.bo);
1608
1609 if (clear_color_bo)
1610 *clear_color_bo = res->aux.clear_color_bo;
1611 if (clear_color_offset)
1612 *clear_color_offset = res->aux.clear_color_offset;
1613 return res->aux.clear_color;
1614 }
1615
1616 static enum pipe_format
1617 iris_resource_get_internal_format(struct pipe_resource *p_res)
1618 {
1619 struct iris_resource *res = (void *) p_res;
1620 return res->internal_format;
1621 }
1622
1623 static const struct u_transfer_vtbl transfer_vtbl = {
1624 .resource_create = iris_resource_create,
1625 .resource_destroy = iris_resource_destroy,
1626 .transfer_map = iris_transfer_map,
1627 .transfer_unmap = iris_transfer_unmap,
1628 .transfer_flush_region = iris_transfer_flush_region,
1629 .get_internal_format = iris_resource_get_internal_format,
1630 .set_stencil = iris_resource_set_separate_stencil,
1631 .get_stencil = iris_resource_get_separate_stencil,
1632 };
1633
1634 void
1635 iris_init_screen_resource_functions(struct pipe_screen *pscreen)
1636 {
1637 pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
1638 pscreen->resource_create_with_modifiers =
1639 iris_resource_create_with_modifiers;
1640 pscreen->resource_create = u_transfer_helper_resource_create;
1641 pscreen->resource_from_user_memory = iris_resource_from_user_memory;
1642 pscreen->resource_from_handle = iris_resource_from_handle;
1643 pscreen->resource_get_handle = iris_resource_get_handle;
1644 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
1645 pscreen->transfer_helper =
1646 u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
1647 }
1648
1649 void
1650 iris_init_resource_functions(struct pipe_context *ctx)
1651 {
1652 ctx->flush_resource = iris_flush_resource;
1653 ctx->invalidate_resource = iris_invalidate_resource;
1654 ctx->transfer_map = u_transfer_helper_transfer_map;
1655 ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
1656 ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
1657 ctx->buffer_subdata = u_default_buffer_subdata;
1658 ctx->texture_subdata = u_default_texture_subdata;
1659 }