2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
91 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
93 case I915_FORMAT_MOD_Y_TILED
:
94 case I915_FORMAT_MOD_X_TILED
:
95 case DRM_FORMAT_MOD_LINEAR
:
97 case DRM_FORMAT_MOD_INVALID
:
104 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
105 const uint64_t *modifiers
,
108 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
110 for (int i
= 0; i
< count
; i
++) {
111 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
114 switch (modifiers
[i
]) {
115 case I915_FORMAT_MOD_Y_TILED_CCS
:
116 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
118 case I915_FORMAT_MOD_Y_TILED
:
119 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
121 case I915_FORMAT_MOD_X_TILED
:
122 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
124 case DRM_FORMAT_MOD_LINEAR
:
125 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
127 case DRM_FORMAT_MOD_INVALID
:
133 return priority_to_modifier
[prio
];
137 target_to_isl_surf_dim(enum pipe_texture_target target
)
141 case PIPE_TEXTURE_1D
:
142 case PIPE_TEXTURE_1D_ARRAY
:
143 return ISL_SURF_DIM_1D
;
144 case PIPE_TEXTURE_2D
:
145 case PIPE_TEXTURE_CUBE
:
146 case PIPE_TEXTURE_RECT
:
147 case PIPE_TEXTURE_2D_ARRAY
:
148 case PIPE_TEXTURE_CUBE_ARRAY
:
149 return ISL_SURF_DIM_2D
;
150 case PIPE_TEXTURE_3D
:
151 return ISL_SURF_DIM_3D
;
152 case PIPE_MAX_TEXTURE_TYPES
:
155 unreachable("invalid texture type");
159 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
160 enum pipe_format pfmt
,
163 unsigned int *external_only
,
166 struct iris_screen
*screen
= (void *) pscreen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 uint64_t all_modifiers
[] = {
170 DRM_FORMAT_MOD_LINEAR
,
171 I915_FORMAT_MOD_X_TILED
,
172 I915_FORMAT_MOD_Y_TILED
,
173 I915_FORMAT_MOD_Y_TILED_CCS
,
176 int supported_mods
= 0;
178 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
179 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
182 if (supported_mods
< max
) {
184 modifiers
[supported_mods
] = all_modifiers
[i
];
187 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
193 *count
= supported_mods
;
196 static isl_surf_usage_flags_t
197 pipe_bind_to_isl_usage(unsigned bindings
)
199 isl_surf_usage_flags_t usage
= 0;
201 if (bindings
& PIPE_BIND_RENDER_TARGET
)
202 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
204 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
205 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
207 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
208 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
210 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
211 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
216 struct pipe_resource
*
217 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
219 /* For packed depth-stencil, we treat depth as the primary resource
220 * and store S8 as the "second plane" resource.
222 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
230 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
231 struct pipe_resource
*stencil
)
233 assert(util_format_has_depth(util_format_description(p_res
->format
)));
234 pipe_resource_reference(&p_res
->next
, stencil
);
238 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
239 struct iris_resource
**out_z
,
240 struct iris_resource
**out_s
)
248 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
249 *out_z
= (void *) res
;
250 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
253 *out_s
= (void *) res
;
258 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
259 enum isl_tiling tiling
,
260 enum pipe_texture_target target
)
263 case PIPE_TEXTURE_1D
:
264 case PIPE_TEXTURE_1D_ARRAY
:
265 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
266 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
268 case PIPE_TEXTURE_2D
:
269 case PIPE_TEXTURE_2D_ARRAY
:
270 case PIPE_TEXTURE_RECT
:
271 case PIPE_TEXTURE_CUBE
:
272 case PIPE_TEXTURE_CUBE_ARRAY
:
273 return ISL_DIM_LAYOUT_GEN4_2D
;
275 case PIPE_TEXTURE_3D
:
276 return (devinfo
->gen
>= 9 ?
277 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
279 case PIPE_MAX_TEXTURE_TYPES
:
283 unreachable("invalid texture type");
287 iris_resource_disable_aux(struct iris_resource
*res
)
289 iris_bo_unreference(res
->aux
.bo
);
290 iris_bo_unreference(res
->aux
.clear_color_bo
);
291 free(res
->aux
.state
);
293 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
294 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
295 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
296 res
->aux
.has_hiz
= 0;
297 res
->aux
.surf
.size_B
= 0;
299 res
->aux
.extra_aux
.surf
.size_B
= 0;
300 res
->aux
.clear_color_bo
= NULL
;
301 res
->aux
.state
= NULL
;
305 iris_resource_destroy(struct pipe_screen
*screen
,
306 struct pipe_resource
*resource
)
308 struct iris_resource
*res
= (struct iris_resource
*)resource
;
310 if (resource
->target
== PIPE_BUFFER
)
311 util_range_destroy(&res
->valid_buffer_range
);
313 iris_resource_disable_aux(res
);
315 iris_bo_unreference(res
->bo
);
319 static struct iris_resource
*
320 iris_alloc_resource(struct pipe_screen
*pscreen
,
321 const struct pipe_resource
*templ
)
323 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
328 res
->base
.screen
= pscreen
;
329 pipe_reference_init(&res
->base
.reference
, 1);
331 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
332 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
334 if (templ
->target
== PIPE_BUFFER
)
335 util_range_init(&res
->valid_buffer_range
);
341 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
343 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
344 return minify(res
->surf
.logical_level0_px
.depth
, level
);
346 return res
->surf
.logical_level0_px
.array_len
;
349 static enum isl_aux_state
**
350 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
352 assert(res
->aux
.state
== NULL
);
354 uint32_t total_slices
= 0;
355 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
356 total_slices
+= iris_get_num_logical_layers(res
, level
);
358 const size_t per_level_array_size
=
359 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
361 /* We're going to allocate a single chunk of data for both the per-level
362 * reference array and the arrays of aux_state. This makes cleanup
363 * significantly easier.
365 const size_t total_size
=
366 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
368 void *data
= malloc(total_size
);
372 enum isl_aux_state
**per_level_arr
= data
;
373 enum isl_aux_state
*s
= data
+ per_level_array_size
;
374 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
375 per_level_arr
[level
] = s
;
376 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
377 for (uint32_t a
= 0; a
< level_layers
; a
++)
380 assert((void *)s
== data
+ total_size
);
382 return per_level_arr
;
386 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
388 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
389 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
393 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
395 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
396 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
397 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
399 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
400 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
401 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
402 res
->aux
.bo
->gtt_offset
+ aux_offset
);
403 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
408 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
409 enum isl_format format
)
411 if (!isl_format_supports_ccs_e(devinfo
, format
))
414 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
416 /* CCS_E seems to significantly hurt performance with 32-bit floating
417 * point formats. For example, Paraview's "Wavelet Volume" case uses
418 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
419 * formats causes a 62% FPS drop.
421 * However, many benchmarks seem to use 16-bit float with no issues.
423 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
430 * Configure aux for the resource, but don't allocate it. For images which
431 * might be shared with modifiers, we must allocate the image and aux data in
434 * Returns false on unexpected error (e.g. allocation failed, or invalid
435 * configuration result).
438 iris_resource_configure_aux(struct iris_screen
*screen
,
439 struct iris_resource
*res
, bool imported
,
440 uint64_t *aux_size_B
,
441 uint32_t *alloc_flags
)
443 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
445 /* Try to create the auxiliary surfaces allowed by the modifier or by
446 * the user if no modifier is specified.
448 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
449 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
451 const bool has_mcs
= !res
->mod_info
&&
452 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
454 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
455 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
458 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
459 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
460 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
461 &res
->aux
.extra_aux
.surf
, 0);
463 /* Having both HIZ and MCS is impossible. */
464 assert(!has_mcs
|| !has_hiz
);
466 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
467 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
468 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
469 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
470 assert(res
->aux
.surf
.size_B
> 0 &&
471 res
->aux
.surf
.usage
&
472 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
475 if (res
->mod_info
&& has_ccs
) {
476 /* Only allow a CCS modifier if the aux was created successfully. */
477 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
478 } else if (has_mcs
) {
479 res
->aux
.possible_usages
|=
480 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
481 } else if (has_hiz
) {
482 res
->aux
.possible_usages
|=
483 1 << (has_ccs
? ISL_AUX_USAGE_HIZ_CCS
: ISL_AUX_USAGE_HIZ
);
484 } else if (has_ccs
) {
485 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
486 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
488 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
489 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
492 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
494 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
496 /* We don't always support sampling with hiz. But when we do, it must be
499 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
500 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
502 /* We don't always support sampling with HIZ_CCS. But when we do, treat it
504 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
505 if (isl_surf_supports_hiz_ccs_wt(devinfo
, &res
->surf
, res
->aux
.usage
))
506 res
->aux
.sampler_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
508 enum isl_aux_state initial_state
;
511 assert(!res
->aux
.bo
);
513 switch (res
->aux
.usage
) {
514 case ISL_AUX_USAGE_NONE
:
515 /* Having no aux buffer is only okay if there's no modifier with aux. */
516 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
517 case ISL_AUX_USAGE_HIZ
:
518 case ISL_AUX_USAGE_HIZ_CCS
:
519 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
521 case ISL_AUX_USAGE_MCS
:
522 case ISL_AUX_USAGE_MCS_CCS
:
523 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
525 * "When MCS buffer is enabled and bound to MSRT, it is required
526 * that it is cleared prior to any rendering."
528 * Since we only use the MCS buffer for rendering, we just clear it
529 * immediately on allocation. The clear value for MCS buffers is all
530 * 1's, so we simply memset it to 0xff.
532 initial_state
= ISL_AUX_STATE_CLEAR
;
534 case ISL_AUX_USAGE_CCS_D
:
535 case ISL_AUX_USAGE_CCS_E
:
536 /* When CCS_E is used, we need to ensure that the CCS starts off in
537 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
540 * "If Software wants to enable Color Compression without Fast
541 * clear, Software needs to initialize MCS with zeros."
543 * A CCS value of 0 indicates that the corresponding block is in the
544 * pass-through state which is what we want.
546 * For CCS_D, do the same thing. On Gen9+, this avoids having any
547 * undefined bits in the aux buffer.
551 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
553 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
554 *alloc_flags
|= BO_ALLOC_ZEROED
;
558 /* Create the aux_state for the auxiliary buffer. */
559 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
563 /* Increase the aux offset if the main and aux surfaces will share a BO. */
565 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
566 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
567 uint64_t size
= res
->aux
.surf
.size_B
;
569 /* Allocate space in the buffer for storing the CCS. */
570 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
571 const uint64_t padded_aux_size
=
572 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
573 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
574 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
577 /* Allocate space in the buffer for storing the clear color. On modern
578 * platforms (gen > 9), we can read it directly from such buffer.
580 * On gen <= 9, we are going to store the clear color on the buffer
581 * anyways, and copy it back to the surface state during state emission.
583 * Also add some padding to make sure the fast clear color state buffer
584 * starts at a 4K alignment. We believe that 256B might be enough, but due
585 * to lack of testing we will leave this as 4K for now.
587 size
= ALIGN(size
, 4096);
588 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
589 size
+= iris_get_aux_clear_color_state_size(screen
);
592 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
593 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
594 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
595 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
597 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
598 * For LOD == 0, we can grow the dimensions to make it work.
600 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
601 res
->aux
.has_hiz
|= 1 << level
;
609 * Initialize the aux buffer contents.
611 * Returns false on unexpected error (e.g. mapping a BO failed).
614 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
615 unsigned clear_color_state_size
)
617 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
618 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
623 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
624 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
625 memset((char*)map
+ res
->aux
.offset
, memset_value
,
626 res
->aux
.surf
.size_B
);
629 /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
630 * - If Software wants to enable Color Compression without Fast clear,
631 * Software needs to initialize MCS with zeros.
632 * - Lossless compression and CCS initialized to all F (using HW Fast
633 * Clear or SW direct Clear)
635 * We think, the first bullet point above is referring to CCS aux
636 * surface. Since we initialize the MCS in the clear state, we also
637 * initialize the CCS in the clear state (via SW direct clear) to keep
640 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
641 isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0,
642 res
->aux
.extra_aux
.surf
.size_B
);
644 /* Zero the indirect clear color to match ::fast_clear_color. */
645 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
646 clear_color_state_size
);
648 iris_bo_unmap(res
->aux
.bo
);
651 if (clear_color_state_size
> 0) {
652 res
->aux
.clear_color_bo
= res
->aux
.bo
;
653 iris_bo_reference(res
->aux
.clear_color_bo
);
660 * Allocate the initial aux surface for a resource based on aux.usage
662 * Returns false on unexpected error (e.g. allocation failed, or invalid
663 * configuration result).
666 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
667 struct iris_resource
*res
)
669 uint32_t alloc_flags
;
671 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
677 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
678 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
679 * of bytes instead of trying to recalculate based on different format
682 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
684 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
685 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
690 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
691 iris_get_aux_clear_color_state_size(screen
)))
694 map_aux_addresses(screen
, res
);
700 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
701 struct iris_resource
*res
)
703 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
704 assert(iris_resource_unfinished_aux_import(res
));
705 assert(!res
->mod_info
->supports_clear_color
);
707 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
708 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
711 assert(res
->bo
== aux_res
->aux
.bo
);
712 iris_bo_reference(aux_res
->aux
.bo
);
713 res
->aux
.bo
= aux_res
->aux
.bo
;
715 res
->aux
.offset
= aux_res
->aux
.offset
;
717 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
718 assert(res
->aux
.clear_color_bo
== NULL
);
719 res
->aux
.clear_color_offset
= 0;
721 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
723 unsigned clear_color_state_size
=
724 iris_get_aux_clear_color_state_size(screen
);
726 if (clear_color_state_size
> 0) {
727 res
->aux
.clear_color_bo
=
728 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
729 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
730 res
->aux
.clear_color_offset
= 0;
733 iris_resource_destroy(&screen
->base
, res
->base
.next
);
734 res
->base
.next
= NULL
;
737 static struct pipe_resource
*
738 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
739 const struct pipe_resource
*templ
)
741 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
742 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
744 assert(templ
->target
== PIPE_BUFFER
);
745 assert(templ
->height0
<= 1);
746 assert(templ
->depth0
<= 1);
747 assert(templ
->format
== PIPE_FORMAT_NONE
||
748 util_format_get_blocksize(templ
->format
) == 1);
750 res
->internal_format
= templ
->format
;
751 res
->surf
.tiling
= ISL_TILING_LINEAR
;
753 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
754 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
755 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
756 memzone
= IRIS_MEMZONE_SHADER
;
757 name
= "shader kernels";
758 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
759 memzone
= IRIS_MEMZONE_SURFACE
;
760 name
= "surface state";
761 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
762 memzone
= IRIS_MEMZONE_DYNAMIC
;
763 name
= "dynamic state";
766 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
768 iris_resource_destroy(pscreen
, &res
->base
);
775 static struct pipe_resource
*
776 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
777 const struct pipe_resource
*templ
,
778 const uint64_t *modifiers
,
781 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
782 struct gen_device_info
*devinfo
= &screen
->devinfo
;
783 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
788 const struct util_format_description
*format_desc
=
789 util_format_description(templ
->format
);
790 const bool has_depth
= util_format_has_depth(format_desc
);
792 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
794 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
796 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
797 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
799 tiling_flags
= 1 << res
->mod_info
->tiling
;
801 if (modifiers_count
> 0) {
802 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
806 /* Use linear for staging buffers */
807 if (templ
->usage
== PIPE_USAGE_STAGING
||
808 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
809 tiling_flags
= ISL_TILING_LINEAR_BIT
;
812 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
814 if (templ
->target
== PIPE_TEXTURE_CUBE
||
815 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
816 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
818 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
819 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
820 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
822 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
825 enum pipe_format pfmt
= templ
->format
;
826 res
->internal_format
= pfmt
;
828 /* Should be handled by u_transfer_helper */
829 assert(!util_format_is_depth_and_stencil(pfmt
));
831 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
832 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
834 UNUSED
const bool isl_surf_created_successfully
=
835 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
836 .dim
= target_to_isl_surf_dim(templ
->target
),
838 .width
= templ
->width0
,
839 .height
= templ
->height0
,
840 .depth
= templ
->depth0
,
841 .levels
= templ
->last_level
+ 1,
842 .array_len
= templ
->array_size
,
843 .samples
= MAX2(templ
->nr_samples
, 1),
844 .min_alignment_B
= 0,
847 .tiling_flags
= tiling_flags
);
848 assert(isl_surf_created_successfully
);
850 const char *name
= "miptree";
851 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
853 unsigned int flags
= 0;
854 if (templ
->usage
== PIPE_USAGE_STAGING
)
855 flags
|= BO_ALLOC_COHERENT
;
857 /* These are for u_upload_mgr buffers only */
858 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
859 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
860 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
862 uint32_t aux_preferred_alloc_flags
;
863 uint64_t aux_size
= 0;
864 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
865 &aux_preferred_alloc_flags
)) {
869 /* Modifiers require the aux data to be in the same buffer as the main
870 * surface, but we combine them even when a modifiers is not being used.
872 const uint64_t bo_size
=
873 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
874 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
875 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
877 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
878 res
->surf
.row_pitch_B
, flags
);
884 res
->aux
.bo
= res
->bo
;
885 iris_bo_reference(res
->aux
.bo
);
886 unsigned clear_color_state_size
=
887 iris_get_aux_clear_color_state_size(screen
);
888 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
890 map_aux_addresses(screen
, res
);
896 fprintf(stderr
, "XXX: resource creation failed\n");
897 iris_resource_destroy(pscreen
, &res
->base
);
902 static struct pipe_resource
*
903 iris_resource_create(struct pipe_screen
*pscreen
,
904 const struct pipe_resource
*templ
)
906 if (templ
->target
== PIPE_BUFFER
)
907 return iris_resource_create_for_buffer(pscreen
, templ
);
909 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
913 tiling_to_modifier(uint32_t tiling
)
915 static const uint64_t map
[] = {
916 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
917 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
918 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
921 assert(tiling
< ARRAY_SIZE(map
));
926 static struct pipe_resource
*
927 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
928 const struct pipe_resource
*templ
,
931 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
932 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
933 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
937 assert(templ
->target
== PIPE_BUFFER
);
939 res
->internal_format
= templ
->format
;
940 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
941 user_memory
, templ
->width0
,
948 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
953 static struct pipe_resource
*
954 iris_resource_from_handle(struct pipe_screen
*pscreen
,
955 const struct pipe_resource
*templ
,
956 struct winsys_handle
*whandle
,
959 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
960 struct gen_device_info
*devinfo
= &screen
->devinfo
;
961 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
962 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
963 const struct isl_drm_modifier_info
*mod_inf
=
964 isl_drm_modifier_get_info(whandle
->modifier
);
970 switch (whandle
->type
) {
971 case WINSYS_HANDLE_TYPE_FD
:
973 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
975 tiling
= I915_TILING_LAST
+ 1;
976 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
977 tiling
, whandle
->stride
);
979 case WINSYS_HANDLE_TYPE_SHARED
:
980 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
984 unreachable("invalid winsys handle type");
989 res
->offset
= whandle
->offset
;
991 if (mod_inf
== NULL
) {
993 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
997 res
->mod_info
= mod_inf
;
999 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1001 const struct iris_format_info fmt
=
1002 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1003 res
->internal_format
= templ
->format
;
1005 if (templ
->target
== PIPE_BUFFER
) {
1006 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1008 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
1009 UNUSED
const bool isl_surf_created_successfully
=
1010 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1011 .dim
= target_to_isl_surf_dim(templ
->target
),
1013 .width
= templ
->width0
,
1014 .height
= templ
->height0
,
1015 .depth
= templ
->depth0
,
1016 .levels
= templ
->last_level
+ 1,
1017 .array_len
= templ
->array_size
,
1018 .samples
= MAX2(templ
->nr_samples
, 1),
1019 .min_alignment_B
= 0,
1020 .row_pitch_B
= whandle
->stride
,
1022 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1023 assert(isl_surf_created_successfully
);
1024 assert(res
->bo
->tiling_mode
==
1025 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1027 // XXX: create_ccs_buf_for_image?
1028 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1029 if (!iris_resource_alloc_separate_aux(screen
, res
))
1032 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1033 uint32_t alloc_flags
;
1035 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1038 /* The gallium dri layer will create a separate plane resource
1039 * for the aux image. iris_resource_finish_aux_import will
1040 * merge the separate aux parameters back into a single
1046 /* Save modifier import information to reconstruct later. After
1047 * import, this will be available under a second image accessible
1048 * from the main image with res->base.next. See
1049 * iris_resource_finish_aux_import.
1051 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1052 res
->aux
.offset
= whandle
->offset
;
1053 res
->aux
.bo
= res
->bo
;
1061 iris_resource_destroy(pscreen
, &res
->base
);
1066 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1068 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1069 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1070 struct iris_resource
*res
= (void *) resource
;
1071 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1073 iris_resource_prepare_access(ice
, render_batch
, res
,
1074 0, INTEL_REMAINING_LEVELS
,
1075 0, INTEL_REMAINING_LAYERS
,
1076 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1077 mod
? mod
->supports_clear_color
: false);
1081 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1084 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1086 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1088 /* Disable aux usage if explicit flush not set and this is the first time
1089 * we are dealing with this resource and the resource was not created with
1090 * a modifier with aux.
1092 if (!mod_with_aux
&&
1093 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1094 p_atomic_read(&resource
->reference
.count
) == 1) {
1095 iris_resource_disable_aux(res
);
1100 iris_resource_get_param(struct pipe_screen
*screen
,
1101 struct pipe_context
*context
,
1102 struct pipe_resource
*resource
,
1105 enum pipe_resource_param param
,
1106 unsigned handle_usage
,
1109 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1111 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1112 bool wants_aux
= mod_with_aux
&& plane
> 0;
1116 if (iris_resource_unfinished_aux_import(res
))
1117 iris_resource_finish_aux_import(screen
, res
);
1119 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1121 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1124 case PIPE_RESOURCE_PARAM_NPLANES
:
1129 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1134 case PIPE_RESOURCE_PARAM_STRIDE
:
1135 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1137 case PIPE_RESOURCE_PARAM_OFFSET
:
1138 *value
= wants_aux
? res
->aux
.offset
: 0;
1140 case PIPE_RESOURCE_PARAM_MODIFIER
:
1141 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1142 tiling_to_modifier(res
->bo
->tiling_mode
);
1144 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1145 result
= iris_bo_flink(bo
, &handle
) == 0;
1149 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1150 *value
= iris_bo_export_gem_handle(bo
);
1152 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1153 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1163 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1164 struct pipe_context
*ctx
,
1165 struct pipe_resource
*resource
,
1166 struct winsys_handle
*whandle
,
1169 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1171 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1173 iris_resource_disable_aux_on_first_query(resource
, usage
);
1176 if (mod_with_aux
&& whandle
->plane
> 0) {
1177 assert(res
->aux
.bo
);
1179 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1180 whandle
->offset
= res
->aux
.offset
;
1182 /* If this is a buffer, stride should be 0 - no need to special case */
1183 whandle
->stride
= res
->surf
.row_pitch_B
;
1187 res
->mod_info
? res
->mod_info
->modifier
1188 : tiling_to_modifier(res
->bo
->tiling_mode
);
1191 enum isl_aux_usage allowed_usage
=
1192 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1194 if (res
->aux
.usage
!= allowed_usage
) {
1195 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1196 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1197 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1201 switch (whandle
->type
) {
1202 case WINSYS_HANDLE_TYPE_SHARED
:
1203 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1204 case WINSYS_HANDLE_TYPE_KMS
:
1205 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1207 case WINSYS_HANDLE_TYPE_FD
:
1208 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1215 resource_is_busy(struct iris_context
*ice
,
1216 struct iris_resource
*res
)
1218 bool busy
= iris_bo_busy(res
->bo
);
1220 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1221 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1227 iris_invalidate_resource(struct pipe_context
*ctx
,
1228 struct pipe_resource
*resource
)
1230 struct iris_screen
*screen
= (void *) ctx
->screen
;
1231 struct iris_context
*ice
= (void *) ctx
;
1232 struct iris_resource
*res
= (void *) resource
;
1234 if (resource
->target
!= PIPE_BUFFER
)
1237 if (!resource_is_busy(ice
, res
)) {
1238 /* The resource is idle, so just mark that it contains no data and
1239 * keep using the same underlying buffer object.
1241 util_range_set_empty(&res
->valid_buffer_range
);
1245 /* Otherwise, try and replace the backing storage with a new BO. */
1247 /* We can't reallocate memory we didn't allocate in the first place. */
1248 if (res
->bo
->userptr
)
1251 // XXX: We should support this.
1252 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1255 struct iris_bo
*old_bo
= res
->bo
;
1256 struct iris_bo
*new_bo
=
1257 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1258 iris_memzone_for_address(old_bo
->gtt_offset
));
1262 /* Swap out the backing storage */
1265 /* Rebind the buffer, replacing any state referring to the old BO's
1266 * address, and marking state dirty so it's reemitted.
1268 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1270 util_range_set_empty(&res
->valid_buffer_range
);
1272 iris_bo_unreference(old_bo
);
1276 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1277 const struct pipe_box
*flush_box
)
1279 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1282 struct iris_transfer
*map
= (void *) xfer
;
1284 struct pipe_box src_box
= *flush_box
;
1286 /* Account for extra alignment padding in staging buffer */
1287 if (xfer
->resource
->target
== PIPE_BUFFER
)
1288 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1290 struct pipe_box dst_box
= (struct pipe_box
) {
1291 .x
= xfer
->box
.x
+ flush_box
->x
,
1292 .y
= xfer
->box
.y
+ flush_box
->y
,
1293 .z
= xfer
->box
.z
+ flush_box
->z
,
1294 .width
= flush_box
->width
,
1295 .height
= flush_box
->height
,
1296 .depth
= flush_box
->depth
,
1299 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1300 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1305 iris_unmap_copy_region(struct iris_transfer
*map
)
1307 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1313 iris_map_copy_region(struct iris_transfer
*map
)
1315 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1316 struct pipe_transfer
*xfer
= &map
->base
;
1317 struct pipe_box
*box
= &xfer
->box
;
1318 struct iris_resource
*res
= (void *) xfer
->resource
;
1320 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1321 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1323 struct pipe_resource templ
= (struct pipe_resource
) {
1324 .usage
= PIPE_USAGE_STAGING
,
1325 .width0
= box
->width
+ extra
,
1326 .height0
= box
->height
,
1328 .nr_samples
= xfer
->resource
->nr_samples
,
1329 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1330 .array_size
= box
->depth
,
1331 .format
= res
->internal_format
,
1334 if (xfer
->resource
->target
== PIPE_BUFFER
)
1335 templ
.target
= PIPE_BUFFER
;
1336 else if (templ
.array_size
> 1)
1337 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1339 templ
.target
= PIPE_TEXTURE_2D
;
1341 map
->staging
= iris_resource_create(pscreen
, &templ
);
1342 assert(map
->staging
);
1344 if (templ
.target
!= PIPE_BUFFER
) {
1345 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1346 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1347 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1350 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1351 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1352 xfer
->resource
, xfer
->level
, box
);
1353 /* Ensure writes to the staging BO land before we map it below. */
1354 iris_emit_pipe_control_flush(map
->batch
,
1355 "transfer read: flush before mapping",
1356 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1357 PIPE_CONTROL_CS_STALL
);
1360 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1362 if (iris_batch_references(map
->batch
, staging_bo
))
1363 iris_batch_flush(map
->batch
);
1366 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1368 map
->unmap
= iris_unmap_copy_region
;
1372 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1373 unsigned *out_x0_el
, unsigned *out_y0_el
)
1375 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1376 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1378 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1383 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1384 * different tiling patterns.
1387 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1388 uint32_t *tile_w
, uint32_t *tile_h
)
1399 case ISL_TILING_LINEAR
:
1404 unreachable("not reached");
1410 * This function computes masks that may be used to select the bits of the X
1411 * and Y coordinates that indicate the offset within a tile. If the BO is
1412 * untiled, the masks are set to 0.
1415 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1416 uint32_t *mask_x
, uint32_t *mask_y
)
1418 uint32_t tile_w_bytes
, tile_h
;
1420 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1422 *mask_x
= tile_w_bytes
/ cpp
- 1;
1423 *mask_y
= tile_h
- 1;
1427 * Compute the offset (in bytes) from the start of the BO to the given x
1428 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1429 * multiples of the tile size.
1432 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1433 uint32_t x
, uint32_t y
)
1435 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1436 unsigned cpp
= fmtl
->bpb
/ 8;
1437 uint32_t pitch
= res
->surf
.row_pitch_B
;
1439 switch (res
->surf
.tiling
) {
1441 unreachable("not reached");
1442 case ISL_TILING_LINEAR
:
1443 return y
* pitch
+ x
* cpp
;
1445 assert((x
% (512 / cpp
)) == 0);
1446 assert((y
% 8) == 0);
1447 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1449 assert((x
% (128 / cpp
)) == 0);
1450 assert((y
% 32) == 0);
1451 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1456 * Rendering with tiled buffers requires that the base address of the buffer
1457 * be aligned to a page boundary. For renderbuffers, and sometimes with
1458 * textures, we may want the surface to point at a texture image level that
1459 * isn't at a page boundary.
1461 * This function returns an appropriately-aligned base offset
1462 * according to the tiling restrictions, plus any required x/y offset
1466 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1467 uint32_t level
, uint32_t z
,
1468 uint32_t *tile_x
, uint32_t *tile_y
)
1471 uint32_t mask_x
, mask_y
;
1473 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1474 const unsigned cpp
= fmtl
->bpb
/ 8;
1476 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1477 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1479 *tile_x
= x
& mask_x
;
1480 *tile_y
= y
& mask_y
;
1482 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1486 * Get pointer offset into stencil buffer.
1488 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1489 * must decode the tile's layout in software.
1492 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1494 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1496 * Even though the returned offset is always positive, the return type is
1498 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1499 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1502 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1504 uint32_t tile_size
= 4096;
1505 uint32_t tile_width
= 64;
1506 uint32_t tile_height
= 64;
1507 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1509 uint32_t tile_x
= x
/ tile_width
;
1510 uint32_t tile_y
= y
/ tile_height
;
1512 /* The byte's address relative to the tile's base addres. */
1513 uint32_t byte_x
= x
% tile_width
;
1514 uint32_t byte_y
= y
% tile_height
;
1516 uintptr_t u
= tile_y
* row_size
1517 + tile_x
* tile_size
1518 + 512 * (byte_x
/ 8)
1520 + 32 * ((byte_y
/ 4) % 2)
1521 + 16 * ((byte_x
/ 4) % 2)
1522 + 8 * ((byte_y
/ 2) % 2)
1523 + 4 * ((byte_x
/ 2) % 2)
1531 iris_unmap_s8(struct iris_transfer
*map
)
1533 struct pipe_transfer
*xfer
= &map
->base
;
1534 const struct pipe_box
*box
= &xfer
->box
;
1535 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1536 struct isl_surf
*surf
= &res
->surf
;
1538 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1539 uint8_t *untiled_s8_map
= map
->ptr
;
1540 uint8_t *tiled_s8_map
=
1541 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1543 for (int s
= 0; s
< box
->depth
; s
++) {
1544 unsigned x0_el
, y0_el
;
1545 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1547 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1548 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1549 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1551 y0_el
+ box
->y
+ y
);
1552 tiled_s8_map
[offset
] =
1553 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1563 iris_map_s8(struct iris_transfer
*map
)
1565 struct pipe_transfer
*xfer
= &map
->base
;
1566 const struct pipe_box
*box
= &xfer
->box
;
1567 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1568 struct isl_surf
*surf
= &res
->surf
;
1570 xfer
->stride
= surf
->row_pitch_B
;
1571 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1573 /* The tiling and detiling functions require that the linear buffer has
1574 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1575 * over-allocate the linear buffer to get the proper alignment.
1577 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1578 assert(map
->buffer
);
1580 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1581 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1582 * invalidate is set, since we'll be writing the whole rectangle from our
1583 * temporary buffer back out.
1585 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1586 uint8_t *untiled_s8_map
= map
->ptr
;
1587 uint8_t *tiled_s8_map
=
1588 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1590 for (int s
= 0; s
< box
->depth
; s
++) {
1591 unsigned x0_el
, y0_el
;
1592 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1594 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1595 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1596 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1598 y0_el
+ box
->y
+ y
);
1599 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1600 tiled_s8_map
[offset
];
1606 map
->unmap
= iris_unmap_s8
;
1609 /* Compute extent parameters for use with tiled_memcpy functions.
1610 * xs are in units of bytes and ys are in units of strides.
1613 tile_extents(const struct isl_surf
*surf
,
1614 const struct pipe_box
*box
,
1615 unsigned level
, int z
,
1616 unsigned *x1_B
, unsigned *x2_B
,
1617 unsigned *y1_el
, unsigned *y2_el
)
1619 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1620 const unsigned cpp
= fmtl
->bpb
/ 8;
1622 assert(box
->x
% fmtl
->bw
== 0);
1623 assert(box
->y
% fmtl
->bh
== 0);
1625 unsigned x0_el
, y0_el
;
1626 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1628 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1629 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1630 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1631 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1635 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1637 struct pipe_transfer
*xfer
= &map
->base
;
1638 const struct pipe_box
*box
= &xfer
->box
;
1639 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1640 struct isl_surf
*surf
= &res
->surf
;
1642 const bool has_swizzling
= false;
1644 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1646 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1648 for (int s
= 0; s
< box
->depth
; s
++) {
1649 unsigned x1
, x2
, y1
, y2
;
1650 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1652 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1654 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1655 surf
->row_pitch_B
, xfer
->stride
,
1656 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1659 os_free_aligned(map
->buffer
);
1660 map
->buffer
= map
->ptr
= NULL
;
1664 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1666 struct pipe_transfer
*xfer
= &map
->base
;
1667 const struct pipe_box
*box
= &xfer
->box
;
1668 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1669 struct isl_surf
*surf
= &res
->surf
;
1671 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1672 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1674 unsigned x1
, x2
, y1
, y2
;
1675 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1677 /* The tiling and detiling functions require that the linear buffer has
1678 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1679 * over-allocate the linear buffer to get the proper alignment.
1682 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1683 assert(map
->buffer
);
1684 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1686 const bool has_swizzling
= false;
1688 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1690 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1692 for (int s
= 0; s
< box
->depth
; s
++) {
1693 unsigned x1
, x2
, y1
, y2
;
1694 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1696 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1697 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1699 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1700 surf
->row_pitch_B
, has_swizzling
,
1701 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1705 map
->unmap
= iris_unmap_tiled_memcpy
;
1709 iris_map_direct(struct iris_transfer
*map
)
1711 struct pipe_transfer
*xfer
= &map
->base
;
1712 struct pipe_box
*box
= &xfer
->box
;
1713 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1715 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1717 if (res
->base
.target
== PIPE_BUFFER
) {
1719 xfer
->layer_stride
= 0;
1721 map
->ptr
= ptr
+ box
->x
;
1723 struct isl_surf
*surf
= &res
->surf
;
1724 const struct isl_format_layout
*fmtl
=
1725 isl_format_get_layout(surf
->format
);
1726 const unsigned cpp
= fmtl
->bpb
/ 8;
1727 unsigned x0_el
, y0_el
;
1729 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1731 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1732 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1734 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1739 can_promote_to_async(const struct iris_resource
*res
,
1740 const struct pipe_box
*box
,
1741 enum pipe_transfer_usage usage
)
1743 /* If we're writing to a section of the buffer that hasn't even been
1744 * initialized with useful data, then we can safely promote this write
1745 * to be unsynchronized. This helps the common pattern of appending data.
1747 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1748 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1749 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1750 box
->x
+ box
->width
);
1754 iris_transfer_map(struct pipe_context
*ctx
,
1755 struct pipe_resource
*resource
,
1757 enum pipe_transfer_usage usage
,
1758 const struct pipe_box
*box
,
1759 struct pipe_transfer
**ptransfer
)
1761 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1762 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1763 struct isl_surf
*surf
= &res
->surf
;
1765 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1766 /* Replace the backing storage with a fresh buffer for non-async maps */
1767 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1768 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1769 iris_invalidate_resource(ctx
, resource
);
1771 /* If we can discard the whole resource, we can discard the range. */
1772 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1775 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1776 can_promote_to_async(res
, box
, usage
)) {
1777 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1780 bool need_resolve
= false;
1781 bool need_color_resolve
= false;
1783 if (resource
->target
!= PIPE_BUFFER
) {
1784 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1786 need_color_resolve
=
1787 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1788 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1789 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1791 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1794 bool map_would_stall
= false;
1796 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1797 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1799 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1800 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1804 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1805 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1808 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1809 struct pipe_transfer
*xfer
= &map
->base
;
1814 memset(map
, 0, sizeof(*map
));
1815 map
->dbg
= &ice
->dbg
;
1817 pipe_resource_reference(&xfer
->resource
, resource
);
1818 xfer
->level
= level
;
1819 xfer
->usage
= usage
;
1823 map
->dest_had_defined_contents
=
1824 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1825 box
->x
+ box
->width
);
1827 if (usage
& PIPE_TRANSFER_WRITE
)
1828 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1830 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1831 * there is to access them simultaneously on the CPU & GPU. This also
1832 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1833 * contain state we're constructing for a GPU draw call, which would
1834 * kill us with infinite stack recursion.
1836 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1837 PIPE_TRANSFER_COHERENT
|
1838 PIPE_TRANSFER_MAP_DIRECTLY
);
1840 /* GPU copies are not useful for buffer reads. Instead of stalling to
1841 * read from the original buffer, we'd simply copy it to a temporary...
1842 * then stall (a bit longer) to read from that buffer.
1844 * Images are less clear-cut. Color resolves are destructive, removing
1845 * the underlying compression, so we'd rather blit the data to a linear
1846 * temporary and map that, to avoid the resolve. (It might be better to
1847 * a tiled temporary and use the tiled_memcpy paths...)
1849 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1852 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1853 if (fmtl
->txc
== ISL_TXC_ASTC
)
1856 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1857 /* If we need a synchronous mapping and the resource is busy, or needs
1858 * resolving, we copy to/from a linear temporary buffer using the GPU.
1860 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1861 map
->blorp
= &ice
->blorp
;
1862 iris_map_copy_region(map
);
1864 /* Otherwise we're free to map on the CPU. */
1867 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1868 level
, box
->z
, box
->depth
,
1869 usage
& PIPE_TRANSFER_WRITE
);
1872 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1873 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1874 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1875 iris_batch_flush(&ice
->batches
[i
]);
1879 if (surf
->tiling
== ISL_TILING_W
) {
1880 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1882 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1883 iris_map_tiled_memcpy(map
);
1885 iris_map_direct(map
);
1893 iris_transfer_flush_region(struct pipe_context
*ctx
,
1894 struct pipe_transfer
*xfer
,
1895 const struct pipe_box
*box
)
1897 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1898 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1899 struct iris_transfer
*map
= (void *) xfer
;
1902 iris_flush_staging_region(xfer
, box
);
1904 uint32_t history_flush
= 0;
1906 if (res
->base
.target
== PIPE_BUFFER
) {
1908 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1910 if (map
->dest_had_defined_contents
)
1911 history_flush
|= iris_flush_bits_for_history(res
);
1913 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1916 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1917 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1918 struct iris_batch
*batch
= &ice
->batches
[i
];
1919 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1920 iris_batch_maybe_flush(batch
, 24);
1921 iris_emit_pipe_control_flush(batch
,
1922 "cache history: transfer flush",
1928 /* Make sure we flag constants dirty even if there's no need to emit
1929 * any PIPE_CONTROLs to a batch.
1931 iris_dirty_for_history(ice
, res
);
1935 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1937 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1938 struct iris_transfer
*map
= (void *) xfer
;
1940 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1941 PIPE_TRANSFER_COHERENT
))) {
1942 struct pipe_box flush_box
= {
1943 .x
= 0, .y
= 0, .z
= 0,
1944 .width
= xfer
->box
.width
,
1945 .height
= xfer
->box
.height
,
1946 .depth
= xfer
->box
.depth
,
1948 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1954 pipe_resource_reference(&xfer
->resource
, NULL
);
1955 slab_free(&ice
->transfer_pool
, map
);
1959 * Mark state dirty that needs to be re-emitted when a resource is written.
1962 iris_dirty_for_history(struct iris_context
*ice
,
1963 struct iris_resource
*res
)
1965 uint64_t dirty
= 0ull;
1967 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1968 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
1971 ice
->state
.dirty
|= dirty
;
1975 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1976 * resource becomes visible, and any stale read cache data is invalidated.
1979 iris_flush_bits_for_history(struct iris_resource
*res
)
1981 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1983 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1984 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1985 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1988 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1989 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1991 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1992 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1994 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1995 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2001 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2002 struct iris_batch
*batch
,
2003 struct iris_resource
*res
,
2004 uint32_t extra_flags
,
2007 if (res
->base
.target
!= PIPE_BUFFER
)
2010 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2012 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2014 iris_dirty_for_history(ice
, res
);
2018 iris_resource_set_clear_color(struct iris_context
*ice
,
2019 struct iris_resource
*res
,
2020 union isl_color_value color
)
2022 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2023 res
->aux
.clear_color
= color
;
2030 union isl_color_value
2031 iris_resource_get_clear_color(const struct iris_resource
*res
,
2032 struct iris_bo
**clear_color_bo
,
2033 uint64_t *clear_color_offset
)
2035 assert(res
->aux
.bo
);
2038 *clear_color_bo
= res
->aux
.clear_color_bo
;
2039 if (clear_color_offset
)
2040 *clear_color_offset
= res
->aux
.clear_color_offset
;
2041 return res
->aux
.clear_color
;
2044 static enum pipe_format
2045 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2047 struct iris_resource
*res
= (void *) p_res
;
2048 return res
->internal_format
;
2051 static const struct u_transfer_vtbl transfer_vtbl
= {
2052 .resource_create
= iris_resource_create
,
2053 .resource_destroy
= iris_resource_destroy
,
2054 .transfer_map
= iris_transfer_map
,
2055 .transfer_unmap
= iris_transfer_unmap
,
2056 .transfer_flush_region
= iris_transfer_flush_region
,
2057 .get_internal_format
= iris_resource_get_internal_format
,
2058 .set_stencil
= iris_resource_set_separate_stencil
,
2059 .get_stencil
= iris_resource_get_separate_stencil
,
2063 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2065 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2066 pscreen
->resource_create_with_modifiers
=
2067 iris_resource_create_with_modifiers
;
2068 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2069 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2070 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2071 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2072 pscreen
->resource_get_param
= iris_resource_get_param
;
2073 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2074 pscreen
->transfer_helper
=
2075 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2079 iris_init_resource_functions(struct pipe_context
*ctx
)
2081 ctx
->flush_resource
= iris_flush_resource
;
2082 ctx
->invalidate_resource
= iris_invalidate_resource
;
2083 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2084 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2085 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2086 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2087 ctx
->texture_subdata
= u_default_texture_subdata
;