2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (linear_format
== ISL_FORMAT_UNSUPPORTED
||
89 !isl_format_supports_ccs_e(devinfo
, linear_format
))
92 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
94 case I915_FORMAT_MOD_Y_TILED
:
95 case I915_FORMAT_MOD_X_TILED
:
96 case DRM_FORMAT_MOD_LINEAR
:
98 case DRM_FORMAT_MOD_INVALID
:
105 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
106 const uint64_t *modifiers
,
109 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
111 for (int i
= 0; i
< count
; i
++) {
112 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
115 switch (modifiers
[i
]) {
116 case I915_FORMAT_MOD_Y_TILED_CCS
:
117 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
119 case I915_FORMAT_MOD_Y_TILED
:
120 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
122 case I915_FORMAT_MOD_X_TILED
:
123 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
125 case DRM_FORMAT_MOD_LINEAR
:
126 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
128 case DRM_FORMAT_MOD_INVALID
:
134 return priority_to_modifier
[prio
];
138 target_to_isl_surf_dim(enum pipe_texture_target target
)
142 case PIPE_TEXTURE_1D
:
143 case PIPE_TEXTURE_1D_ARRAY
:
144 return ISL_SURF_DIM_1D
;
145 case PIPE_TEXTURE_2D
:
146 case PIPE_TEXTURE_CUBE
:
147 case PIPE_TEXTURE_RECT
:
148 case PIPE_TEXTURE_2D_ARRAY
:
149 case PIPE_TEXTURE_CUBE_ARRAY
:
150 return ISL_SURF_DIM_2D
;
151 case PIPE_TEXTURE_3D
:
152 return ISL_SURF_DIM_3D
;
153 case PIPE_MAX_TEXTURE_TYPES
:
156 unreachable("invalid texture type");
160 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
161 enum pipe_format pfmt
,
164 unsigned int *external_only
,
167 struct iris_screen
*screen
= (void *) pscreen
;
168 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
170 uint64_t all_modifiers
[] = {
171 DRM_FORMAT_MOD_LINEAR
,
172 I915_FORMAT_MOD_X_TILED
,
173 I915_FORMAT_MOD_Y_TILED
,
174 I915_FORMAT_MOD_Y_TILED_CCS
,
177 int supported_mods
= 0;
179 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
180 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
183 if (supported_mods
< max
) {
185 modifiers
[supported_mods
] = all_modifiers
[i
];
188 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
194 *count
= supported_mods
;
197 static isl_surf_usage_flags_t
198 pipe_bind_to_isl_usage(unsigned bindings
)
200 isl_surf_usage_flags_t usage
= 0;
202 if (bindings
& PIPE_BIND_RENDER_TARGET
)
203 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
205 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
206 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
208 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
209 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
211 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
212 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
218 iris_image_view_get_format(struct iris_context
*ice
,
219 const struct pipe_image_view
*img
)
221 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
222 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
224 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
225 enum isl_format isl_fmt
=
226 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
228 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
229 /* On Gen8, try to use typed surfaces reads (which support a
230 * limited number of formats), and if not possible, fall back
233 if (devinfo
->gen
== 8 &&
234 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
235 return ISL_FORMAT_RAW
;
237 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
243 struct pipe_resource
*
244 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
246 /* For packed depth-stencil, we treat depth as the primary resource
247 * and store S8 as the "second plane" resource.
249 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
257 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
258 struct pipe_resource
*stencil
)
260 assert(util_format_has_depth(util_format_description(p_res
->format
)));
261 pipe_resource_reference(&p_res
->next
, stencil
);
265 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
266 struct iris_resource
**out_z
,
267 struct iris_resource
**out_s
)
275 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
276 *out_z
= (void *) res
;
277 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
280 *out_s
= (void *) res
;
285 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
286 enum isl_tiling tiling
,
287 enum pipe_texture_target target
)
290 case PIPE_TEXTURE_1D
:
291 case PIPE_TEXTURE_1D_ARRAY
:
292 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
293 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
295 case PIPE_TEXTURE_2D
:
296 case PIPE_TEXTURE_2D_ARRAY
:
297 case PIPE_TEXTURE_RECT
:
298 case PIPE_TEXTURE_CUBE
:
299 case PIPE_TEXTURE_CUBE_ARRAY
:
300 return ISL_DIM_LAYOUT_GEN4_2D
;
302 case PIPE_TEXTURE_3D
:
303 return (devinfo
->gen
>= 9 ?
304 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
306 case PIPE_MAX_TEXTURE_TYPES
:
310 unreachable("invalid texture type");
314 iris_resource_disable_aux(struct iris_resource
*res
)
316 iris_bo_unreference(res
->aux
.bo
);
317 iris_bo_unreference(res
->aux
.clear_color_bo
);
318 free(res
->aux
.state
);
320 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
321 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
322 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
323 res
->aux
.has_hiz
= 0;
324 res
->aux
.surf
.size_B
= 0;
326 res
->aux
.extra_aux
.surf
.size_B
= 0;
327 res
->aux
.clear_color_bo
= NULL
;
328 res
->aux
.state
= NULL
;
332 iris_resource_destroy(struct pipe_screen
*screen
,
333 struct pipe_resource
*resource
)
335 struct iris_resource
*res
= (struct iris_resource
*)resource
;
337 if (resource
->target
== PIPE_BUFFER
)
338 util_range_destroy(&res
->valid_buffer_range
);
340 iris_resource_disable_aux(res
);
342 iris_bo_unreference(res
->bo
);
346 static struct iris_resource
*
347 iris_alloc_resource(struct pipe_screen
*pscreen
,
348 const struct pipe_resource
*templ
)
350 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
355 res
->base
.screen
= pscreen
;
356 pipe_reference_init(&res
->base
.reference
, 1);
358 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
359 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
361 if (templ
->target
== PIPE_BUFFER
)
362 util_range_init(&res
->valid_buffer_range
);
368 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
370 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
371 return minify(res
->surf
.logical_level0_px
.depth
, level
);
373 return res
->surf
.logical_level0_px
.array_len
;
376 static enum isl_aux_state
**
377 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
379 assert(res
->aux
.state
== NULL
);
381 uint32_t total_slices
= 0;
382 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
383 total_slices
+= iris_get_num_logical_layers(res
, level
);
385 const size_t per_level_array_size
=
386 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
388 /* We're going to allocate a single chunk of data for both the per-level
389 * reference array and the arrays of aux_state. This makes cleanup
390 * significantly easier.
392 const size_t total_size
=
393 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
395 void *data
= malloc(total_size
);
399 enum isl_aux_state
**per_level_arr
= data
;
400 enum isl_aux_state
*s
= data
+ per_level_array_size
;
401 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
402 per_level_arr
[level
] = s
;
403 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
404 for (uint32_t a
= 0; a
< level_layers
; a
++)
407 assert((void *)s
== data
+ total_size
);
409 return per_level_arr
;
413 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
416 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
420 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
422 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
423 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
424 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
426 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
427 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
428 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
429 res
->aux
.bo
->gtt_offset
+ aux_offset
);
430 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
435 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
436 enum isl_format format
)
438 if (!isl_format_supports_ccs_e(devinfo
, format
))
441 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
443 /* CCS_E seems to significantly hurt performance with 32-bit floating
444 * point formats. For example, Paraview's "Wavelet Volume" case uses
445 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
446 * formats causes a 62% FPS drop.
448 * However, many benchmarks seem to use 16-bit float with no issues.
450 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
457 * Configure aux for the resource, but don't allocate it. For images which
458 * might be shared with modifiers, we must allocate the image and aux data in
461 * Returns false on unexpected error (e.g. allocation failed, or invalid
462 * configuration result).
465 iris_resource_configure_aux(struct iris_screen
*screen
,
466 struct iris_resource
*res
, bool imported
,
467 uint64_t *aux_size_B
,
468 uint32_t *alloc_flags
)
470 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
472 /* Try to create the auxiliary surfaces allowed by the modifier or by
473 * the user if no modifier is specified.
475 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
476 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
478 const bool has_mcs
= !res
->mod_info
&&
479 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
481 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
482 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
485 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
486 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
487 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
488 &res
->aux
.extra_aux
.surf
, 0);
490 /* Having both HIZ and MCS is impossible. */
491 assert(!has_mcs
|| !has_hiz
);
493 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
494 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
495 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
496 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
497 assert(res
->aux
.surf
.size_B
> 0 &&
498 res
->aux
.surf
.usage
&
499 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
502 if (res
->mod_info
&& has_ccs
) {
503 /* Only allow a CCS modifier if the aux was created successfully. */
504 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
505 } else if (has_mcs
) {
506 res
->aux
.possible_usages
|=
507 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
508 } else if (has_hiz
) {
510 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
511 } else if (res
->surf
.samples
== 1 &&
512 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
513 /* If this resource is single-sampled and will be used as a texture,
514 * put the HiZ surface in write-through mode so that we can sample
517 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
519 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
521 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
522 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
523 } else if (has_ccs
) {
524 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
525 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
527 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
528 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
531 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
533 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
535 /* We don't always support sampling with hiz. But when we do, it must be
538 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
539 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
541 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
542 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
544 enum isl_aux_state initial_state
;
547 assert(!res
->aux
.bo
);
549 switch (res
->aux
.usage
) {
550 case ISL_AUX_USAGE_NONE
:
551 /* Having no aux buffer is only okay if there's no modifier with aux. */
552 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
553 case ISL_AUX_USAGE_HIZ
:
554 case ISL_AUX_USAGE_HIZ_CCS
:
555 case ISL_AUX_USAGE_HIZ_CCS_WT
:
556 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
558 case ISL_AUX_USAGE_MCS
:
559 case ISL_AUX_USAGE_MCS_CCS
:
560 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
562 * "When MCS buffer is enabled and bound to MSRT, it is required
563 * that it is cleared prior to any rendering."
565 * Since we only use the MCS buffer for rendering, we just clear it
566 * immediately on allocation. The clear value for MCS buffers is all
567 * 1's, so we simply memset it to 0xff.
569 initial_state
= ISL_AUX_STATE_CLEAR
;
571 case ISL_AUX_USAGE_CCS_D
:
572 case ISL_AUX_USAGE_CCS_E
:
573 case ISL_AUX_USAGE_STC_CCS
:
574 /* When CCS_E is used, we need to ensure that the CCS starts off in
575 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
578 * "If Software wants to enable Color Compression without Fast
579 * clear, Software needs to initialize MCS with zeros."
581 * A CCS value of 0 indicates that the corresponding block is in the
582 * pass-through state which is what we want.
584 * For CCS_D, do the same thing. On Gen9+, this avoids having any
585 * undefined bits in the aux buffer.
588 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
590 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
592 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
594 *alloc_flags
|= BO_ALLOC_ZEROED
;
596 case ISL_AUX_USAGE_MC
:
597 unreachable("Unsupported aux mode");
600 /* Create the aux_state for the auxiliary buffer. */
601 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
605 /* Increase the aux offset if the main and aux surfaces will share a BO. */
607 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
608 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
609 uint64_t size
= res
->aux
.surf
.size_B
;
611 /* Allocate space in the buffer for storing the CCS. */
612 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
613 const uint64_t padded_aux_size
=
614 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
615 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
616 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
619 /* Allocate space in the buffer for storing the clear color. On modern
620 * platforms (gen > 9), we can read it directly from such buffer.
622 * On gen <= 9, we are going to store the clear color on the buffer
623 * anyways, and copy it back to the surface state during state emission.
625 * Also add some padding to make sure the fast clear color state buffer
626 * starts at a 4K alignment. We believe that 256B might be enough, but due
627 * to lack of testing we will leave this as 4K for now.
629 size
= ALIGN(size
, 4096);
630 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
631 size
+= iris_get_aux_clear_color_state_size(screen
);
634 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
635 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
636 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
637 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
639 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
640 * For LOD == 0, we can grow the dimensions to make it work.
642 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
643 res
->aux
.has_hiz
|= 1 << level
;
651 * Initialize the aux buffer contents.
653 * Returns false on unexpected error (e.g. mapping a BO failed).
656 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
657 unsigned clear_color_state_size
)
659 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
660 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
665 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
666 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
667 memset((char*)map
+ res
->aux
.offset
, memset_value
,
668 res
->aux
.surf
.size_B
);
671 /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
672 * - If Software wants to enable Color Compression without Fast clear,
673 * Software needs to initialize MCS with zeros.
674 * - Lossless compression and CCS initialized to all F (using HW Fast
675 * Clear or SW direct Clear)
677 * We think, the first bullet point above is referring to CCS aux
678 * surface. Since we initialize the MCS in the clear state, we also
679 * initialize the CCS in the clear state (via SW direct clear) to keep
682 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
683 isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0,
684 res
->aux
.extra_aux
.surf
.size_B
);
686 /* Zero the indirect clear color to match ::fast_clear_color. */
687 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
688 clear_color_state_size
);
690 iris_bo_unmap(res
->aux
.bo
);
693 if (clear_color_state_size
> 0) {
694 res
->aux
.clear_color_bo
= res
->aux
.bo
;
695 iris_bo_reference(res
->aux
.clear_color_bo
);
702 * Allocate the initial aux surface for a resource based on aux.usage
704 * Returns false on unexpected error (e.g. allocation failed, or invalid
705 * configuration result).
708 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
709 struct iris_resource
*res
)
711 uint32_t alloc_flags
;
713 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
719 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
720 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
721 * of bytes instead of trying to recalculate based on different format
724 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
726 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
727 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
732 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
733 iris_get_aux_clear_color_state_size(screen
)))
736 map_aux_addresses(screen
, res
);
742 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
743 struct iris_resource
*res
)
745 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
746 assert(iris_resource_unfinished_aux_import(res
));
747 assert(!res
->mod_info
->supports_clear_color
);
749 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
750 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
753 assert(res
->bo
== aux_res
->aux
.bo
);
754 iris_bo_reference(aux_res
->aux
.bo
);
755 res
->aux
.bo
= aux_res
->aux
.bo
;
757 res
->aux
.offset
= aux_res
->aux
.offset
;
759 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
760 assert(res
->aux
.clear_color_bo
== NULL
);
761 res
->aux
.clear_color_offset
= 0;
763 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
765 unsigned clear_color_state_size
=
766 iris_get_aux_clear_color_state_size(screen
);
768 if (clear_color_state_size
> 0) {
769 res
->aux
.clear_color_bo
=
770 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
771 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
772 res
->aux
.clear_color_offset
= 0;
775 iris_resource_destroy(&screen
->base
, res
->base
.next
);
776 res
->base
.next
= NULL
;
779 static struct pipe_resource
*
780 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
781 const struct pipe_resource
*templ
)
783 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
784 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
786 assert(templ
->target
== PIPE_BUFFER
);
787 assert(templ
->height0
<= 1);
788 assert(templ
->depth0
<= 1);
789 assert(templ
->format
== PIPE_FORMAT_NONE
||
790 util_format_get_blocksize(templ
->format
) == 1);
792 res
->internal_format
= templ
->format
;
793 res
->surf
.tiling
= ISL_TILING_LINEAR
;
795 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
796 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
797 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
798 memzone
= IRIS_MEMZONE_SHADER
;
799 name
= "shader kernels";
800 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
801 memzone
= IRIS_MEMZONE_SURFACE
;
802 name
= "surface state";
803 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
804 memzone
= IRIS_MEMZONE_DYNAMIC
;
805 name
= "dynamic state";
808 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
810 iris_resource_destroy(pscreen
, &res
->base
);
817 static struct pipe_resource
*
818 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
819 const struct pipe_resource
*templ
,
820 const uint64_t *modifiers
,
823 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
824 struct gen_device_info
*devinfo
= &screen
->devinfo
;
825 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
830 const struct util_format_description
*format_desc
=
831 util_format_description(templ
->format
);
832 const bool has_depth
= util_format_has_depth(format_desc
);
834 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
836 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
838 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
839 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
841 tiling_flags
= 1 << res
->mod_info
->tiling
;
843 if (modifiers_count
> 0) {
844 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
848 /* Use linear for staging buffers */
849 if (templ
->usage
== PIPE_USAGE_STAGING
||
850 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
851 tiling_flags
= ISL_TILING_LINEAR_BIT
;
852 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
853 tiling_flags
= ISL_TILING_X_BIT
;
856 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
858 if (templ
->target
== PIPE_TEXTURE_CUBE
||
859 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
860 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
862 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
863 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
864 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
866 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
869 enum pipe_format pfmt
= templ
->format
;
870 res
->internal_format
= pfmt
;
872 /* Should be handled by u_transfer_helper */
873 assert(!util_format_is_depth_and_stencil(pfmt
));
875 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
876 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
878 UNUSED
const bool isl_surf_created_successfully
=
879 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
880 .dim
= target_to_isl_surf_dim(templ
->target
),
882 .width
= templ
->width0
,
883 .height
= templ
->height0
,
884 .depth
= templ
->depth0
,
885 .levels
= templ
->last_level
+ 1,
886 .array_len
= templ
->array_size
,
887 .samples
= MAX2(templ
->nr_samples
, 1),
888 .min_alignment_B
= 0,
891 .tiling_flags
= tiling_flags
);
892 assert(isl_surf_created_successfully
);
894 const char *name
= "miptree";
895 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
897 unsigned int flags
= 0;
898 if (templ
->usage
== PIPE_USAGE_STAGING
)
899 flags
|= BO_ALLOC_COHERENT
;
901 /* These are for u_upload_mgr buffers only */
902 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
903 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
904 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
906 uint32_t aux_preferred_alloc_flags
;
907 uint64_t aux_size
= 0;
908 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
909 &aux_preferred_alloc_flags
)) {
913 /* Modifiers require the aux data to be in the same buffer as the main
914 * surface, but we combine them even when a modifiers is not being used.
916 const uint64_t bo_size
=
917 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
918 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
919 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
921 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
922 res
->surf
.row_pitch_B
, flags
);
928 res
->aux
.bo
= res
->bo
;
929 iris_bo_reference(res
->aux
.bo
);
930 unsigned clear_color_state_size
=
931 iris_get_aux_clear_color_state_size(screen
);
932 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
934 map_aux_addresses(screen
, res
);
940 fprintf(stderr
, "XXX: resource creation failed\n");
941 iris_resource_destroy(pscreen
, &res
->base
);
946 static struct pipe_resource
*
947 iris_resource_create(struct pipe_screen
*pscreen
,
948 const struct pipe_resource
*templ
)
950 if (templ
->target
== PIPE_BUFFER
)
951 return iris_resource_create_for_buffer(pscreen
, templ
);
953 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
957 tiling_to_modifier(uint32_t tiling
)
959 static const uint64_t map
[] = {
960 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
961 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
962 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
965 assert(tiling
< ARRAY_SIZE(map
));
970 static struct pipe_resource
*
971 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
972 const struct pipe_resource
*templ
,
975 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
976 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
977 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
981 assert(templ
->target
== PIPE_BUFFER
);
983 res
->internal_format
= templ
->format
;
984 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
985 user_memory
, templ
->width0
,
992 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
997 static struct pipe_resource
*
998 iris_resource_from_handle(struct pipe_screen
*pscreen
,
999 const struct pipe_resource
*templ
,
1000 struct winsys_handle
*whandle
,
1003 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1004 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1005 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1006 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1007 const struct isl_drm_modifier_info
*mod_inf
=
1008 isl_drm_modifier_get_info(whandle
->modifier
);
1014 switch (whandle
->type
) {
1015 case WINSYS_HANDLE_TYPE_FD
:
1017 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1019 tiling
= I915_TILING_LAST
+ 1;
1020 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1021 tiling
, whandle
->stride
);
1023 case WINSYS_HANDLE_TYPE_SHARED
:
1024 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1028 unreachable("invalid winsys handle type");
1033 res
->offset
= whandle
->offset
;
1035 if (mod_inf
== NULL
) {
1037 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1041 res
->external_format
= whandle
->format
;
1042 res
->mod_info
= mod_inf
;
1044 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1046 const struct iris_format_info fmt
=
1047 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1048 res
->internal_format
= templ
->format
;
1050 if (templ
->target
== PIPE_BUFFER
) {
1051 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1053 /* Create a surface for each plane specified by the external format. */
1054 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1055 UNUSED
const bool isl_surf_created_successfully
=
1056 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1057 .dim
= target_to_isl_surf_dim(templ
->target
),
1059 .width
= templ
->width0
,
1060 .height
= templ
->height0
,
1061 .depth
= templ
->depth0
,
1062 .levels
= templ
->last_level
+ 1,
1063 .array_len
= templ
->array_size
,
1064 .samples
= MAX2(templ
->nr_samples
, 1),
1065 .min_alignment_B
= 0,
1066 .row_pitch_B
= whandle
->stride
,
1068 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1069 assert(isl_surf_created_successfully
);
1070 assert(res
->bo
->tiling_mode
==
1071 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1073 // XXX: create_ccs_buf_for_image?
1074 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1075 if (!iris_resource_alloc_separate_aux(screen
, res
))
1078 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1079 uint32_t alloc_flags
;
1081 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1084 /* The gallium dri layer will create a separate plane resource
1085 * for the aux image. iris_resource_finish_aux_import will
1086 * merge the separate aux parameters back into a single
1092 /* Save modifier import information to reconstruct later. After
1093 * import, this will be available under a second image accessible
1094 * from the main image with res->base.next. See
1095 * iris_resource_finish_aux_import.
1097 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1098 res
->aux
.offset
= whandle
->offset
;
1099 res
->aux
.bo
= res
->bo
;
1107 iris_resource_destroy(pscreen
, &res
->base
);
1112 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1114 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1115 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1116 struct iris_resource
*res
= (void *) resource
;
1117 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1119 iris_resource_prepare_access(ice
, render_batch
, res
,
1120 0, INTEL_REMAINING_LEVELS
,
1121 0, INTEL_REMAINING_LAYERS
,
1122 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1123 mod
? mod
->supports_clear_color
: false);
1127 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1130 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1132 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1134 /* Disable aux usage if explicit flush not set and this is the first time
1135 * we are dealing with this resource and the resource was not created with
1136 * a modifier with aux.
1138 if (!mod_with_aux
&&
1139 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1140 p_atomic_read(&resource
->reference
.count
) == 1) {
1141 iris_resource_disable_aux(res
);
1146 iris_resource_get_param(struct pipe_screen
*screen
,
1147 struct pipe_context
*context
,
1148 struct pipe_resource
*resource
,
1151 enum pipe_resource_param param
,
1152 unsigned handle_usage
,
1155 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1157 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1158 bool wants_aux
= mod_with_aux
&& plane
> 0;
1162 if (iris_resource_unfinished_aux_import(res
))
1163 iris_resource_finish_aux_import(screen
, res
);
1165 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1167 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1170 case PIPE_RESOURCE_PARAM_NPLANES
:
1175 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1180 case PIPE_RESOURCE_PARAM_STRIDE
:
1181 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1183 case PIPE_RESOURCE_PARAM_OFFSET
:
1184 *value
= wants_aux
? res
->aux
.offset
: 0;
1186 case PIPE_RESOURCE_PARAM_MODIFIER
:
1187 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1188 tiling_to_modifier(res
->bo
->tiling_mode
);
1190 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1191 result
= iris_bo_flink(bo
, &handle
) == 0;
1195 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1196 *value
= iris_bo_export_gem_handle(bo
);
1198 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1199 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1209 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1210 struct pipe_context
*ctx
,
1211 struct pipe_resource
*resource
,
1212 struct winsys_handle
*whandle
,
1215 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1217 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1219 iris_resource_disable_aux_on_first_query(resource
, usage
);
1222 if (mod_with_aux
&& whandle
->plane
> 0) {
1223 assert(res
->aux
.bo
);
1225 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1226 whandle
->offset
= res
->aux
.offset
;
1228 /* If this is a buffer, stride should be 0 - no need to special case */
1229 whandle
->stride
= res
->surf
.row_pitch_B
;
1233 whandle
->format
= res
->external_format
;
1235 res
->mod_info
? res
->mod_info
->modifier
1236 : tiling_to_modifier(res
->bo
->tiling_mode
);
1239 enum isl_aux_usage allowed_usage
=
1240 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1242 if (res
->aux
.usage
!= allowed_usage
) {
1243 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1244 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1245 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1249 switch (whandle
->type
) {
1250 case WINSYS_HANDLE_TYPE_SHARED
:
1251 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1252 case WINSYS_HANDLE_TYPE_KMS
:
1253 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1255 case WINSYS_HANDLE_TYPE_FD
:
1256 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1263 resource_is_busy(struct iris_context
*ice
,
1264 struct iris_resource
*res
)
1266 bool busy
= iris_bo_busy(res
->bo
);
1268 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1269 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1275 iris_invalidate_resource(struct pipe_context
*ctx
,
1276 struct pipe_resource
*resource
)
1278 struct iris_screen
*screen
= (void *) ctx
->screen
;
1279 struct iris_context
*ice
= (void *) ctx
;
1280 struct iris_resource
*res
= (void *) resource
;
1282 if (resource
->target
!= PIPE_BUFFER
)
1285 /* If it's already invalidated, don't bother doing anything. */
1286 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1289 if (!resource_is_busy(ice
, res
)) {
1290 /* The resource is idle, so just mark that it contains no data and
1291 * keep using the same underlying buffer object.
1293 util_range_set_empty(&res
->valid_buffer_range
);
1297 /* Otherwise, try and replace the backing storage with a new BO. */
1299 /* We can't reallocate memory we didn't allocate in the first place. */
1300 if (res
->bo
->userptr
)
1303 // XXX: We should support this.
1304 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1307 struct iris_bo
*old_bo
= res
->bo
;
1308 struct iris_bo
*new_bo
=
1309 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1310 iris_memzone_for_address(old_bo
->gtt_offset
));
1314 /* Swap out the backing storage */
1317 /* Rebind the buffer, replacing any state referring to the old BO's
1318 * address, and marking state dirty so it's reemitted.
1320 ice
->vtbl
.rebind_buffer(ice
, res
);
1322 util_range_set_empty(&res
->valid_buffer_range
);
1324 iris_bo_unreference(old_bo
);
1328 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1329 const struct pipe_box
*flush_box
)
1331 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1334 struct iris_transfer
*map
= (void *) xfer
;
1336 struct pipe_box src_box
= *flush_box
;
1338 /* Account for extra alignment padding in staging buffer */
1339 if (xfer
->resource
->target
== PIPE_BUFFER
)
1340 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1342 struct pipe_box dst_box
= (struct pipe_box
) {
1343 .x
= xfer
->box
.x
+ flush_box
->x
,
1344 .y
= xfer
->box
.y
+ flush_box
->y
,
1345 .z
= xfer
->box
.z
+ flush_box
->z
,
1346 .width
= flush_box
->width
,
1347 .height
= flush_box
->height
,
1348 .depth
= flush_box
->depth
,
1351 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1352 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1357 iris_unmap_copy_region(struct iris_transfer
*map
)
1359 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1365 iris_map_copy_region(struct iris_transfer
*map
)
1367 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1368 struct pipe_transfer
*xfer
= &map
->base
;
1369 struct pipe_box
*box
= &xfer
->box
;
1370 struct iris_resource
*res
= (void *) xfer
->resource
;
1372 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1373 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1375 struct pipe_resource templ
= (struct pipe_resource
) {
1376 .usage
= PIPE_USAGE_STAGING
,
1377 .width0
= box
->width
+ extra
,
1378 .height0
= box
->height
,
1380 .nr_samples
= xfer
->resource
->nr_samples
,
1381 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1382 .array_size
= box
->depth
,
1383 .format
= res
->internal_format
,
1386 if (xfer
->resource
->target
== PIPE_BUFFER
)
1387 templ
.target
= PIPE_BUFFER
;
1388 else if (templ
.array_size
> 1)
1389 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1391 templ
.target
= PIPE_TEXTURE_2D
;
1393 map
->staging
= iris_resource_create(pscreen
, &templ
);
1394 assert(map
->staging
);
1396 if (templ
.target
!= PIPE_BUFFER
) {
1397 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1398 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1399 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1402 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1403 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1404 xfer
->resource
, xfer
->level
, box
);
1405 /* Ensure writes to the staging BO land before we map it below. */
1406 iris_emit_pipe_control_flush(map
->batch
,
1407 "transfer read: flush before mapping",
1408 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1409 PIPE_CONTROL_CS_STALL
);
1412 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1414 if (iris_batch_references(map
->batch
, staging_bo
))
1415 iris_batch_flush(map
->batch
);
1418 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1420 map
->unmap
= iris_unmap_copy_region
;
1424 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1425 unsigned *out_x0_el
, unsigned *out_y0_el
)
1427 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1428 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1430 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1435 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1436 * different tiling patterns.
1439 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1440 uint32_t *tile_w
, uint32_t *tile_h
)
1451 case ISL_TILING_LINEAR
:
1456 unreachable("not reached");
1462 * This function computes masks that may be used to select the bits of the X
1463 * and Y coordinates that indicate the offset within a tile. If the BO is
1464 * untiled, the masks are set to 0.
1467 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1468 uint32_t *mask_x
, uint32_t *mask_y
)
1470 uint32_t tile_w_bytes
, tile_h
;
1472 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1474 *mask_x
= tile_w_bytes
/ cpp
- 1;
1475 *mask_y
= tile_h
- 1;
1479 * Compute the offset (in bytes) from the start of the BO to the given x
1480 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1481 * multiples of the tile size.
1484 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1485 uint32_t x
, uint32_t y
)
1487 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1488 unsigned cpp
= fmtl
->bpb
/ 8;
1489 uint32_t pitch
= res
->surf
.row_pitch_B
;
1491 switch (res
->surf
.tiling
) {
1493 unreachable("not reached");
1494 case ISL_TILING_LINEAR
:
1495 return y
* pitch
+ x
* cpp
;
1497 assert((x
% (512 / cpp
)) == 0);
1498 assert((y
% 8) == 0);
1499 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1501 assert((x
% (128 / cpp
)) == 0);
1502 assert((y
% 32) == 0);
1503 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1508 * Rendering with tiled buffers requires that the base address of the buffer
1509 * be aligned to a page boundary. For renderbuffers, and sometimes with
1510 * textures, we may want the surface to point at a texture image level that
1511 * isn't at a page boundary.
1513 * This function returns an appropriately-aligned base offset
1514 * according to the tiling restrictions, plus any required x/y offset
1518 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1519 uint32_t level
, uint32_t z
,
1520 uint32_t *tile_x
, uint32_t *tile_y
)
1523 uint32_t mask_x
, mask_y
;
1525 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1526 const unsigned cpp
= fmtl
->bpb
/ 8;
1528 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1529 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1531 *tile_x
= x
& mask_x
;
1532 *tile_y
= y
& mask_y
;
1534 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1538 * Get pointer offset into stencil buffer.
1540 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1541 * must decode the tile's layout in software.
1544 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1546 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1548 * Even though the returned offset is always positive, the return type is
1550 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1551 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1554 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1556 uint32_t tile_size
= 4096;
1557 uint32_t tile_width
= 64;
1558 uint32_t tile_height
= 64;
1559 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1561 uint32_t tile_x
= x
/ tile_width
;
1562 uint32_t tile_y
= y
/ tile_height
;
1564 /* The byte's address relative to the tile's base addres. */
1565 uint32_t byte_x
= x
% tile_width
;
1566 uint32_t byte_y
= y
% tile_height
;
1568 uintptr_t u
= tile_y
* row_size
1569 + tile_x
* tile_size
1570 + 512 * (byte_x
/ 8)
1572 + 32 * ((byte_y
/ 4) % 2)
1573 + 16 * ((byte_x
/ 4) % 2)
1574 + 8 * ((byte_y
/ 2) % 2)
1575 + 4 * ((byte_x
/ 2) % 2)
1583 iris_unmap_s8(struct iris_transfer
*map
)
1585 struct pipe_transfer
*xfer
= &map
->base
;
1586 const struct pipe_box
*box
= &xfer
->box
;
1587 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1588 struct isl_surf
*surf
= &res
->surf
;
1590 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1591 uint8_t *untiled_s8_map
= map
->ptr
;
1592 uint8_t *tiled_s8_map
=
1593 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1595 for (int s
= 0; s
< box
->depth
; s
++) {
1596 unsigned x0_el
, y0_el
;
1597 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1599 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1600 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1601 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1603 y0_el
+ box
->y
+ y
);
1604 tiled_s8_map
[offset
] =
1605 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1615 iris_map_s8(struct iris_transfer
*map
)
1617 struct pipe_transfer
*xfer
= &map
->base
;
1618 const struct pipe_box
*box
= &xfer
->box
;
1619 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1620 struct isl_surf
*surf
= &res
->surf
;
1622 xfer
->stride
= surf
->row_pitch_B
;
1623 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1625 /* The tiling and detiling functions require that the linear buffer has
1626 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1627 * over-allocate the linear buffer to get the proper alignment.
1629 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1630 assert(map
->buffer
);
1632 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1633 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1634 * invalidate is set, since we'll be writing the whole rectangle from our
1635 * temporary buffer back out.
1637 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1638 uint8_t *untiled_s8_map
= map
->ptr
;
1639 uint8_t *tiled_s8_map
=
1640 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1642 for (int s
= 0; s
< box
->depth
; s
++) {
1643 unsigned x0_el
, y0_el
;
1644 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1646 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1647 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1648 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1650 y0_el
+ box
->y
+ y
);
1651 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1652 tiled_s8_map
[offset
];
1658 map
->unmap
= iris_unmap_s8
;
1661 /* Compute extent parameters for use with tiled_memcpy functions.
1662 * xs are in units of bytes and ys are in units of strides.
1665 tile_extents(const struct isl_surf
*surf
,
1666 const struct pipe_box
*box
,
1667 unsigned level
, int z
,
1668 unsigned *x1_B
, unsigned *x2_B
,
1669 unsigned *y1_el
, unsigned *y2_el
)
1671 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1672 const unsigned cpp
= fmtl
->bpb
/ 8;
1674 assert(box
->x
% fmtl
->bw
== 0);
1675 assert(box
->y
% fmtl
->bh
== 0);
1677 unsigned x0_el
, y0_el
;
1678 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1680 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1681 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1682 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1683 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1687 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1689 struct pipe_transfer
*xfer
= &map
->base
;
1690 const struct pipe_box
*box
= &xfer
->box
;
1691 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1692 struct isl_surf
*surf
= &res
->surf
;
1694 const bool has_swizzling
= false;
1696 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1698 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1700 for (int s
= 0; s
< box
->depth
; s
++) {
1701 unsigned x1
, x2
, y1
, y2
;
1702 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1704 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1706 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1707 surf
->row_pitch_B
, xfer
->stride
,
1708 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1711 os_free_aligned(map
->buffer
);
1712 map
->buffer
= map
->ptr
= NULL
;
1716 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1718 struct pipe_transfer
*xfer
= &map
->base
;
1719 const struct pipe_box
*box
= &xfer
->box
;
1720 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1721 struct isl_surf
*surf
= &res
->surf
;
1723 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1724 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1726 unsigned x1
, x2
, y1
, y2
;
1727 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1729 /* The tiling and detiling functions require that the linear buffer has
1730 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1731 * over-allocate the linear buffer to get the proper alignment.
1734 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1735 assert(map
->buffer
);
1736 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1738 const bool has_swizzling
= false;
1740 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1742 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1744 for (int s
= 0; s
< box
->depth
; s
++) {
1745 unsigned x1
, x2
, y1
, y2
;
1746 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1748 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1749 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1751 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1752 surf
->row_pitch_B
, has_swizzling
,
1753 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1757 map
->unmap
= iris_unmap_tiled_memcpy
;
1761 iris_map_direct(struct iris_transfer
*map
)
1763 struct pipe_transfer
*xfer
= &map
->base
;
1764 struct pipe_box
*box
= &xfer
->box
;
1765 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1767 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1769 if (res
->base
.target
== PIPE_BUFFER
) {
1771 xfer
->layer_stride
= 0;
1773 map
->ptr
= ptr
+ box
->x
;
1775 struct isl_surf
*surf
= &res
->surf
;
1776 const struct isl_format_layout
*fmtl
=
1777 isl_format_get_layout(surf
->format
);
1778 const unsigned cpp
= fmtl
->bpb
/ 8;
1779 unsigned x0_el
, y0_el
;
1781 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1783 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1784 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1786 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1791 can_promote_to_async(const struct iris_resource
*res
,
1792 const struct pipe_box
*box
,
1793 enum pipe_transfer_usage usage
)
1795 /* If we're writing to a section of the buffer that hasn't even been
1796 * initialized with useful data, then we can safely promote this write
1797 * to be unsynchronized. This helps the common pattern of appending data.
1799 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1800 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1801 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1802 box
->x
+ box
->width
);
1806 iris_transfer_map(struct pipe_context
*ctx
,
1807 struct pipe_resource
*resource
,
1809 enum pipe_transfer_usage usage
,
1810 const struct pipe_box
*box
,
1811 struct pipe_transfer
**ptransfer
)
1813 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1814 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1815 struct isl_surf
*surf
= &res
->surf
;
1817 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1818 /* Replace the backing storage with a fresh buffer for non-async maps */
1819 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1820 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1821 iris_invalidate_resource(ctx
, resource
);
1823 /* If we can discard the whole resource, we can discard the range. */
1824 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1827 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1828 can_promote_to_async(res
, box
, usage
)) {
1829 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1832 bool need_resolve
= false;
1833 bool need_color_resolve
= false;
1835 if (resource
->target
!= PIPE_BUFFER
) {
1836 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1837 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1839 need_color_resolve
=
1840 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1841 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1842 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1844 need_resolve
= need_color_resolve
||
1846 need_stencil_resolve
;
1849 bool map_would_stall
= false;
1851 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1852 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1854 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1855 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1859 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1860 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1863 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1864 struct pipe_transfer
*xfer
= &map
->base
;
1869 memset(map
, 0, sizeof(*map
));
1870 map
->dbg
= &ice
->dbg
;
1872 pipe_resource_reference(&xfer
->resource
, resource
);
1873 xfer
->level
= level
;
1874 xfer
->usage
= usage
;
1878 map
->dest_had_defined_contents
=
1879 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1880 box
->x
+ box
->width
);
1882 if (usage
& PIPE_TRANSFER_WRITE
)
1883 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1885 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1886 * there is to access them simultaneously on the CPU & GPU. This also
1887 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1888 * contain state we're constructing for a GPU draw call, which would
1889 * kill us with infinite stack recursion.
1891 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1892 PIPE_TRANSFER_COHERENT
|
1893 PIPE_TRANSFER_MAP_DIRECTLY
);
1895 /* GPU copies are not useful for buffer reads. Instead of stalling to
1896 * read from the original buffer, we'd simply copy it to a temporary...
1897 * then stall (a bit longer) to read from that buffer.
1899 * Images are less clear-cut. Color resolves are destructive, removing
1900 * the underlying compression, so we'd rather blit the data to a linear
1901 * temporary and map that, to avoid the resolve. (It might be better to
1902 * a tiled temporary and use the tiled_memcpy paths...)
1904 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1907 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1908 if (fmtl
->txc
== ISL_TXC_ASTC
)
1911 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1912 /* If we need a synchronous mapping and the resource is busy, or needs
1913 * resolving, we copy to/from a linear temporary buffer using the GPU.
1915 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1916 map
->blorp
= &ice
->blorp
;
1917 iris_map_copy_region(map
);
1919 /* Otherwise we're free to map on the CPU. */
1922 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1923 level
, box
->z
, box
->depth
,
1924 usage
& PIPE_TRANSFER_WRITE
);
1927 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1928 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1929 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1930 iris_batch_flush(&ice
->batches
[i
]);
1934 if (surf
->tiling
== ISL_TILING_W
) {
1935 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1937 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1938 iris_map_tiled_memcpy(map
);
1940 iris_map_direct(map
);
1948 iris_transfer_flush_region(struct pipe_context
*ctx
,
1949 struct pipe_transfer
*xfer
,
1950 const struct pipe_box
*box
)
1952 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1953 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1954 struct iris_transfer
*map
= (void *) xfer
;
1957 iris_flush_staging_region(xfer
, box
);
1959 uint32_t history_flush
= 0;
1961 if (res
->base
.target
== PIPE_BUFFER
) {
1963 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1965 if (map
->dest_had_defined_contents
)
1966 history_flush
|= iris_flush_bits_for_history(res
);
1968 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1971 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1972 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1973 struct iris_batch
*batch
= &ice
->batches
[i
];
1974 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1975 iris_batch_maybe_flush(batch
, 24);
1976 iris_emit_pipe_control_flush(batch
,
1977 "cache history: transfer flush",
1983 /* Make sure we flag constants dirty even if there's no need to emit
1984 * any PIPE_CONTROLs to a batch.
1986 iris_dirty_for_history(ice
, res
);
1990 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1992 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1993 struct iris_transfer
*map
= (void *) xfer
;
1995 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1996 PIPE_TRANSFER_COHERENT
))) {
1997 struct pipe_box flush_box
= {
1998 .x
= 0, .y
= 0, .z
= 0,
1999 .width
= xfer
->box
.width
,
2000 .height
= xfer
->box
.height
,
2001 .depth
= xfer
->box
.depth
,
2003 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2009 pipe_resource_reference(&xfer
->resource
, NULL
);
2010 slab_free(&ice
->transfer_pool
, map
);
2014 * Mark state dirty that needs to be re-emitted when a resource is written.
2017 iris_dirty_for_history(struct iris_context
*ice
,
2018 struct iris_resource
*res
)
2020 uint64_t dirty
= 0ull;
2022 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2023 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
2026 ice
->state
.dirty
|= dirty
;
2030 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2031 * resource becomes visible, and any stale read cache data is invalidated.
2034 iris_flush_bits_for_history(struct iris_resource
*res
)
2036 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2038 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2039 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2040 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2043 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2044 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2046 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2047 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2049 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2050 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2056 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2057 struct iris_batch
*batch
,
2058 struct iris_resource
*res
,
2059 uint32_t extra_flags
,
2062 if (res
->base
.target
!= PIPE_BUFFER
)
2065 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2067 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2069 iris_dirty_for_history(ice
, res
);
2073 iris_resource_set_clear_color(struct iris_context
*ice
,
2074 struct iris_resource
*res
,
2075 union isl_color_value color
)
2077 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2078 res
->aux
.clear_color
= color
;
2085 union isl_color_value
2086 iris_resource_get_clear_color(const struct iris_resource
*res
,
2087 struct iris_bo
**clear_color_bo
,
2088 uint64_t *clear_color_offset
)
2090 assert(res
->aux
.bo
);
2093 *clear_color_bo
= res
->aux
.clear_color_bo
;
2094 if (clear_color_offset
)
2095 *clear_color_offset
= res
->aux
.clear_color_offset
;
2096 return res
->aux
.clear_color
;
2099 static enum pipe_format
2100 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2102 struct iris_resource
*res
= (void *) p_res
;
2103 return res
->internal_format
;
2106 static const struct u_transfer_vtbl transfer_vtbl
= {
2107 .resource_create
= iris_resource_create
,
2108 .resource_destroy
= iris_resource_destroy
,
2109 .transfer_map
= iris_transfer_map
,
2110 .transfer_unmap
= iris_transfer_unmap
,
2111 .transfer_flush_region
= iris_transfer_flush_region
,
2112 .get_internal_format
= iris_resource_get_internal_format
,
2113 .set_stencil
= iris_resource_set_separate_stencil
,
2114 .get_stencil
= iris_resource_get_separate_stencil
,
2118 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2120 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2121 pscreen
->resource_create_with_modifiers
=
2122 iris_resource_create_with_modifiers
;
2123 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2124 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2125 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2126 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2127 pscreen
->resource_get_param
= iris_resource_get_param
;
2128 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2129 pscreen
->transfer_helper
=
2130 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2134 iris_init_resource_functions(struct pipe_context
*ctx
)
2136 ctx
->flush_resource
= iris_flush_resource
;
2137 ctx
->invalidate_resource
= iris_invalidate_resource
;
2138 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2139 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2140 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2141 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2142 ctx
->texture_subdata
= u_default_texture_subdata
;