2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
73 enum pipe_format pfmt
, uint64_t modifier
)
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED_CCS
: {
78 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
81 enum isl_format rt_format
=
82 iris_format_for_usage(devinfo
, pfmt
,
83 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
85 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
87 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
92 case I915_FORMAT_MOD_Y_TILED
:
93 case I915_FORMAT_MOD_X_TILED
:
94 case DRM_FORMAT_MOD_LINEAR
:
96 case DRM_FORMAT_MOD_INVALID
:
103 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
104 const uint64_t *modifiers
,
107 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
109 for (int i
= 0; i
< count
; i
++) {
110 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
113 switch (modifiers
[i
]) {
114 case I915_FORMAT_MOD_Y_TILED_CCS
:
115 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
117 case I915_FORMAT_MOD_Y_TILED
:
118 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
120 case I915_FORMAT_MOD_X_TILED
:
121 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
123 case DRM_FORMAT_MOD_LINEAR
:
124 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
126 case DRM_FORMAT_MOD_INVALID
:
132 return priority_to_modifier
[prio
];
136 target_to_isl_surf_dim(enum pipe_texture_target target
)
140 case PIPE_TEXTURE_1D
:
141 case PIPE_TEXTURE_1D_ARRAY
:
142 return ISL_SURF_DIM_1D
;
143 case PIPE_TEXTURE_2D
:
144 case PIPE_TEXTURE_CUBE
:
145 case PIPE_TEXTURE_RECT
:
146 case PIPE_TEXTURE_2D_ARRAY
:
147 case PIPE_TEXTURE_CUBE_ARRAY
:
148 return ISL_SURF_DIM_2D
;
149 case PIPE_TEXTURE_3D
:
150 return ISL_SURF_DIM_3D
;
151 case PIPE_MAX_TEXTURE_TYPES
:
154 unreachable("invalid texture type");
158 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
159 enum pipe_format pfmt
,
162 unsigned int *external_only
,
165 struct iris_screen
*screen
= (void *) pscreen
;
166 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
168 uint64_t all_modifiers
[] = {
169 DRM_FORMAT_MOD_LINEAR
,
170 I915_FORMAT_MOD_X_TILED
,
171 I915_FORMAT_MOD_Y_TILED
,
172 I915_FORMAT_MOD_Y_TILED_CCS
,
175 int supported_mods
= 0;
177 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
178 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
181 if (supported_mods
< max
) {
183 modifiers
[supported_mods
] = all_modifiers
[i
];
186 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
192 *count
= supported_mods
;
195 static isl_surf_usage_flags_t
196 pipe_bind_to_isl_usage(unsigned bindings
)
198 isl_surf_usage_flags_t usage
= 0;
200 if (bindings
& PIPE_BIND_RENDER_TARGET
)
201 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
203 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
204 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
206 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
207 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
209 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
210 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
215 struct pipe_resource
*
216 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
218 /* For packed depth-stencil, we treat depth as the primary resource
219 * and store S8 as the "second plane" resource.
221 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
229 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
230 struct pipe_resource
*stencil
)
232 assert(util_format_has_depth(util_format_description(p_res
->format
)));
233 pipe_resource_reference(&p_res
->next
, stencil
);
237 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
238 struct iris_resource
**out_z
,
239 struct iris_resource
**out_s
)
247 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
248 *out_z
= (void *) res
;
249 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
252 *out_s
= (void *) res
;
257 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
258 enum isl_tiling tiling
,
259 enum pipe_texture_target target
)
262 case PIPE_TEXTURE_1D
:
263 case PIPE_TEXTURE_1D_ARRAY
:
264 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
265 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
267 case PIPE_TEXTURE_2D
:
268 case PIPE_TEXTURE_2D_ARRAY
:
269 case PIPE_TEXTURE_RECT
:
270 case PIPE_TEXTURE_CUBE
:
271 case PIPE_TEXTURE_CUBE_ARRAY
:
272 return ISL_DIM_LAYOUT_GEN4_2D
;
274 case PIPE_TEXTURE_3D
:
275 return (devinfo
->gen
>= 9 ?
276 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
278 case PIPE_MAX_TEXTURE_TYPES
:
282 unreachable("invalid texture type");
286 iris_resource_disable_aux(struct iris_resource
*res
)
288 iris_bo_unreference(res
->aux
.bo
);
289 iris_bo_unreference(res
->aux
.clear_color_bo
);
290 free(res
->aux
.state
);
292 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
293 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
294 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
295 res
->aux
.surf
.size_B
= 0;
297 res
->aux
.clear_color_bo
= NULL
;
298 res
->aux
.state
= NULL
;
302 iris_resource_destroy(struct pipe_screen
*screen
,
303 struct pipe_resource
*resource
)
305 struct iris_resource
*res
= (struct iris_resource
*)resource
;
307 if (resource
->target
== PIPE_BUFFER
)
308 util_range_destroy(&res
->valid_buffer_range
);
310 iris_resource_disable_aux(res
);
312 iris_bo_unreference(res
->bo
);
316 static struct iris_resource
*
317 iris_alloc_resource(struct pipe_screen
*pscreen
,
318 const struct pipe_resource
*templ
)
320 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
325 res
->base
.screen
= pscreen
;
326 pipe_reference_init(&res
->base
.reference
, 1);
328 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
329 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
331 if (templ
->target
== PIPE_BUFFER
)
332 util_range_init(&res
->valid_buffer_range
);
338 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
340 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
341 return minify(res
->surf
.logical_level0_px
.depth
, level
);
343 return res
->surf
.logical_level0_px
.array_len
;
346 static enum isl_aux_state
**
347 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
349 uint32_t total_slices
= 0;
350 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
351 total_slices
+= iris_get_num_logical_layers(res
, level
);
353 const size_t per_level_array_size
=
354 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
356 /* We're going to allocate a single chunk of data for both the per-level
357 * reference array and the arrays of aux_state. This makes cleanup
358 * significantly easier.
360 const size_t total_size
=
361 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
363 void *data
= malloc(total_size
);
367 enum isl_aux_state
**per_level_arr
= data
;
368 enum isl_aux_state
*s
= data
+ per_level_array_size
;
369 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
370 per_level_arr
[level
] = s
;
371 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
372 for (uint32_t a
= 0; a
< level_layers
; a
++)
375 assert((void *)s
== data
+ total_size
);
377 return per_level_arr
;
381 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
383 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
384 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
388 * Configure aux for the resource, but don't allocate it. For images which
389 * might be shared with modifiers, we must allocate the image and aux data in
393 iris_resource_configure_aux(struct iris_screen
*screen
,
394 struct iris_resource
*res
, bool imported
,
395 uint64_t *aux_size_B
,
396 uint32_t *alloc_flags
)
398 struct isl_device
*isl_dev
= &screen
->isl_dev
;
399 enum isl_aux_state initial_state
;
400 UNUSED
bool ok
= false;
404 assert(!res
->aux
.bo
);
406 switch (res
->aux
.usage
) {
407 case ISL_AUX_USAGE_NONE
:
408 res
->aux
.surf
.size_B
= 0;
411 case ISL_AUX_USAGE_HIZ
:
412 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
413 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
415 case ISL_AUX_USAGE_MCS
:
416 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
418 * "When MCS buffer is enabled and bound to MSRT, it is required
419 * that it is cleared prior to any rendering."
421 * Since we only use the MCS buffer for rendering, we just clear it
422 * immediately on allocation. The clear value for MCS buffers is all
423 * 1's, so we simply memset it to 0xff.
425 initial_state
= ISL_AUX_STATE_CLEAR
;
426 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
428 case ISL_AUX_USAGE_CCS_D
:
429 case ISL_AUX_USAGE_CCS_E
:
430 /* When CCS_E is used, we need to ensure that the CCS starts off in
431 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
434 * "If Software wants to enable Color Compression without Fast
435 * clear, Software needs to initialize MCS with zeros."
437 * A CCS value of 0 indicates that the corresponding block is in the
438 * pass-through state which is what we want.
440 * For CCS_D, do the same thing. On Gen9+, this avoids having any
441 * undefined bits in the aux buffer.
445 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
447 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
448 *alloc_flags
|= BO_ALLOC_ZEROED
;
449 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
453 /* We should have a valid aux_surf. */
457 /* No work is needed for a zero-sized auxiliary buffer. */
458 if (res
->aux
.surf
.size_B
== 0)
461 if (!res
->aux
.state
) {
462 /* Create the aux_state for the auxiliary buffer. */
463 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
468 uint64_t size
= res
->aux
.surf
.size_B
;
470 /* Allocate space in the buffer for storing the clear color. On modern
471 * platforms (gen > 9), we can read it directly from such buffer.
473 * On gen <= 9, we are going to store the clear color on the buffer
474 * anyways, and copy it back to the surface state during state emission.
476 res
->aux
.clear_color_offset
= size
;
477 size
+= iris_get_aux_clear_color_state_size(screen
);
480 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
481 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
482 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
483 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
485 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
486 * For LOD == 0, we can grow the dimensions to make it work.
488 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
489 res
->aux
.has_hiz
|= 1 << level
;
497 * Initialize the aux buffer contents.
500 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
501 unsigned clear_color_state_size
)
503 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
504 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
507 iris_resource_disable_aux(res
);
511 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
512 uint8_t memset_value
= res
->aux
.usage
== ISL_AUX_USAGE_MCS
? 0xFF : 0;
513 memset((char*)map
+ res
->aux
.offset
, memset_value
,
514 res
->aux
.surf
.size_B
);
517 /* Zero the indirect clear color to match ::fast_clear_color. */
518 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
519 clear_color_state_size
);
521 iris_bo_unmap(res
->aux
.bo
);
524 if (clear_color_state_size
> 0) {
525 res
->aux
.clear_color_bo
= res
->aux
.bo
;
526 iris_bo_reference(res
->aux
.clear_color_bo
);
533 * Allocate the initial aux surface for a resource based on aux.usage
536 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
537 struct iris_resource
*res
)
539 uint32_t alloc_flags
;
541 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
547 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
548 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
549 * of bytes instead of trying to recalculate based on different format
552 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
553 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
554 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
559 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
560 iris_get_aux_clear_color_state_size(screen
)))
567 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
568 struct iris_resource
*res
)
570 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
571 assert(iris_resource_unfinished_aux_import(res
));
572 assert(!res
->mod_info
->supports_clear_color
);
574 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
575 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
578 assert(res
->bo
== aux_res
->aux
.bo
);
579 iris_bo_reference(aux_res
->aux
.bo
);
580 res
->aux
.bo
= aux_res
->aux
.bo
;
582 res
->aux
.offset
= aux_res
->aux
.offset
;
584 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
585 assert(res
->aux
.clear_color_bo
== NULL
);
586 res
->aux
.clear_color_offset
= 0;
588 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
590 unsigned clear_color_state_size
=
591 iris_get_aux_clear_color_state_size(screen
);
593 if (clear_color_state_size
> 0) {
594 res
->aux
.clear_color_bo
=
595 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
596 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
597 res
->aux
.clear_color_offset
= 0;
600 iris_resource_destroy(&screen
->base
, res
->base
.next
);
601 res
->base
.next
= NULL
;
605 supports_mcs(const struct isl_surf
*surf
)
607 /* MCS compression only applies to multisampled resources. */
608 if (surf
->samples
<= 1)
611 /* Depth and stencil buffers use the IMS (interleaved) layout. */
612 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
619 supports_ccs(const struct gen_device_info
*devinfo
,
620 const struct isl_surf
*surf
)
622 /* CCS only supports singlesampled resources. */
623 if (surf
->samples
> 1)
626 /* Note: still need to check the format! */
632 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
633 enum isl_format format
)
635 if (!isl_format_supports_ccs_e(devinfo
, format
))
638 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
640 /* CCS_E seems to significantly hurt performance with 32-bit floating
641 * point formats. For example, Paraview's "Wavelet Volume" case uses
642 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
643 * formats causes a 62% FPS drop.
645 * However, many benchmarks seem to use 16-bit float with no issues.
647 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
653 static struct pipe_resource
*
654 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
655 const struct pipe_resource
*templ
)
657 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
658 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
660 assert(templ
->target
== PIPE_BUFFER
);
661 assert(templ
->height0
<= 1);
662 assert(templ
->depth0
<= 1);
663 assert(templ
->format
== PIPE_FORMAT_NONE
||
664 util_format_get_blocksize(templ
->format
) == 1);
666 res
->internal_format
= templ
->format
;
667 res
->surf
.tiling
= ISL_TILING_LINEAR
;
669 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
670 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
671 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
672 memzone
= IRIS_MEMZONE_SHADER
;
673 name
= "shader kernels";
674 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
675 memzone
= IRIS_MEMZONE_SURFACE
;
676 name
= "surface state";
677 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
678 memzone
= IRIS_MEMZONE_DYNAMIC
;
679 name
= "dynamic state";
682 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
684 iris_resource_destroy(pscreen
, &res
->base
);
691 static struct pipe_resource
*
692 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
693 const struct pipe_resource
*templ
,
694 const uint64_t *modifiers
,
697 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
698 struct gen_device_info
*devinfo
= &screen
->devinfo
;
699 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
704 const struct util_format_description
*format_desc
=
705 util_format_description(templ
->format
);
706 const bool has_depth
= util_format_has_depth(format_desc
);
708 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
710 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
712 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
713 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
715 tiling_flags
= 1 << res
->mod_info
->tiling
;
717 if (modifiers_count
> 0) {
718 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
722 /* Use linear for staging buffers */
723 if (templ
->usage
== PIPE_USAGE_STAGING
||
724 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
725 tiling_flags
= ISL_TILING_LINEAR_BIT
;
728 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
730 if (templ
->target
== PIPE_TEXTURE_CUBE
||
731 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
732 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
734 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
735 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
736 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
738 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
741 enum pipe_format pfmt
= templ
->format
;
742 res
->internal_format
= pfmt
;
744 /* Should be handled by u_transfer_helper */
745 assert(!util_format_is_depth_and_stencil(pfmt
));
747 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
748 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
750 UNUSED
const bool isl_surf_created_successfully
=
751 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
752 .dim
= target_to_isl_surf_dim(templ
->target
),
754 .width
= templ
->width0
,
755 .height
= templ
->height0
,
756 .depth
= templ
->depth0
,
757 .levels
= templ
->last_level
+ 1,
758 .array_len
= templ
->array_size
,
759 .samples
= MAX2(templ
->nr_samples
, 1),
760 .min_alignment_B
= 0,
763 .tiling_flags
= tiling_flags
);
764 assert(isl_surf_created_successfully
);
767 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
768 } else if (supports_mcs(&res
->surf
)) {
769 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
770 } else if (has_depth
) {
771 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
772 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
773 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
774 supports_ccs(devinfo
, &res
->surf
)) {
775 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
776 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
778 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
779 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
782 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
784 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
786 /* We don't always support sampling with hiz. But when we do, it must be
789 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
790 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
793 const char *name
= "miptree";
794 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
796 unsigned int flags
= 0;
797 if (templ
->usage
== PIPE_USAGE_STAGING
)
798 flags
|= BO_ALLOC_COHERENT
;
800 /* These are for u_upload_mgr buffers only */
801 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
802 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
803 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
805 uint32_t aux_preferred_alloc_flags
;
806 uint64_t aux_size
= 0;
808 iris_resource_configure_aux(screen
, res
, false, &aux_size
,
809 &aux_preferred_alloc_flags
);
810 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
811 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
815 if (aux_enabled
&& !separate_aux
) {
816 /* Allocate aux data with main surface. This is required for modifiers
817 * with aux data (ccs).
819 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
820 bo_size
= aux_offset
+ aux_size
;
823 bo_size
= res
->surf
.size_B
;
826 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, 4096, memzone
,
827 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
828 res
->surf
.row_pitch_B
, flags
);
835 if (!iris_resource_alloc_separate_aux(screen
, res
))
838 res
->aux
.bo
= res
->bo
;
839 iris_bo_reference(res
->aux
.bo
);
840 res
->aux
.offset
+= aux_offset
;
841 unsigned clear_color_state_size
=
842 iris_get_aux_clear_color_state_size(screen
);
843 if (clear_color_state_size
> 0)
844 res
->aux
.clear_color_offset
+= aux_offset
;
845 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
851 iris_resource_disable_aux(res
);
856 fprintf(stderr
, "XXX: resource creation failed\n");
857 iris_resource_destroy(pscreen
, &res
->base
);
862 static struct pipe_resource
*
863 iris_resource_create(struct pipe_screen
*pscreen
,
864 const struct pipe_resource
*templ
)
866 if (templ
->target
== PIPE_BUFFER
)
867 return iris_resource_create_for_buffer(pscreen
, templ
);
869 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
873 tiling_to_modifier(uint32_t tiling
)
875 static const uint64_t map
[] = {
876 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
877 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
878 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
881 assert(tiling
< ARRAY_SIZE(map
));
886 static struct pipe_resource
*
887 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
888 const struct pipe_resource
*templ
,
891 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
892 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
893 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
897 assert(templ
->target
== PIPE_BUFFER
);
899 res
->internal_format
= templ
->format
;
900 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
901 user_memory
, templ
->width0
,
908 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
913 static struct pipe_resource
*
914 iris_resource_from_handle(struct pipe_screen
*pscreen
,
915 const struct pipe_resource
*templ
,
916 struct winsys_handle
*whandle
,
919 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
920 struct gen_device_info
*devinfo
= &screen
->devinfo
;
921 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
922 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
926 switch (whandle
->type
) {
927 case WINSYS_HANDLE_TYPE_FD
:
928 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
930 case WINSYS_HANDLE_TYPE_SHARED
:
931 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
935 unreachable("invalid winsys handle type");
940 res
->offset
= whandle
->offset
;
942 uint64_t modifier
= whandle
->modifier
;
943 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
944 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
946 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
947 assert(res
->mod_info
);
949 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
951 const struct iris_format_info fmt
=
952 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
953 res
->internal_format
= templ
->format
;
955 if (templ
->target
== PIPE_BUFFER
) {
956 res
->surf
.tiling
= ISL_TILING_LINEAR
;
958 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
959 UNUSED
const bool isl_surf_created_successfully
=
960 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
961 .dim
= target_to_isl_surf_dim(templ
->target
),
963 .width
= templ
->width0
,
964 .height
= templ
->height0
,
965 .depth
= templ
->depth0
,
966 .levels
= templ
->last_level
+ 1,
967 .array_len
= templ
->array_size
,
968 .samples
= MAX2(templ
->nr_samples
, 1),
969 .min_alignment_B
= 0,
970 .row_pitch_B
= whandle
->stride
,
972 .tiling_flags
= 1 << res
->mod_info
->tiling
);
973 assert(isl_surf_created_successfully
);
974 assert(res
->bo
->tiling_mode
==
975 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
977 // XXX: create_ccs_buf_for_image?
978 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
979 if (!iris_resource_alloc_separate_aux(screen
, res
))
982 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
983 uint32_t alloc_flags
;
985 res
->aux
.usage
= res
->mod_info
->aux_usage
;
986 res
->aux
.possible_usages
= 1 << res
->mod_info
->aux_usage
;
987 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
988 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
991 /* The gallium dri layer will create a separate plane resource
992 * for the aux image. iris_resource_finish_aux_import will
993 * merge the separate aux parameters back into a single
999 /* Save modifier import information to reconstruct later. After
1000 * import, this will be available under a second image accessible
1001 * from the main image with res->base.next. See
1002 * iris_resource_finish_aux_import.
1004 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1005 res
->aux
.offset
= whandle
->offset
;
1006 res
->aux
.bo
= res
->bo
;
1014 iris_resource_destroy(pscreen
, &res
->base
);
1019 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1021 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1022 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1023 struct iris_resource
*res
= (void *) resource
;
1024 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1026 iris_resource_prepare_access(ice
, render_batch
, res
,
1027 0, INTEL_REMAINING_LEVELS
,
1028 0, INTEL_REMAINING_LAYERS
,
1029 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1030 mod
? mod
->supports_clear_color
: false);
1034 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1037 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1039 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1041 /* Disable aux usage if explicit flush not set and this is the first time
1042 * we are dealing with this resource and the resource was not created with
1043 * a modifier with aux.
1045 if (!mod_with_aux
&&
1046 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1047 p_atomic_read(&resource
->reference
.count
) == 1) {
1048 iris_resource_disable_aux(res
);
1053 iris_resource_get_param(struct pipe_screen
*screen
,
1054 struct pipe_context
*context
,
1055 struct pipe_resource
*resource
,
1058 enum pipe_resource_param param
,
1059 unsigned handle_usage
,
1062 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1064 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1065 bool wants_aux
= mod_with_aux
&& plane
> 0;
1069 if (iris_resource_unfinished_aux_import(res
))
1070 iris_resource_finish_aux_import(screen
, res
);
1072 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1074 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1077 case PIPE_RESOURCE_PARAM_NPLANES
:
1082 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1087 case PIPE_RESOURCE_PARAM_STRIDE
:
1088 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1090 case PIPE_RESOURCE_PARAM_OFFSET
:
1091 *value
= wants_aux
? res
->aux
.offset
: 0;
1093 case PIPE_RESOURCE_PARAM_MODIFIER
:
1094 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1095 tiling_to_modifier(res
->bo
->tiling_mode
);
1097 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1098 result
= iris_bo_flink(bo
, &handle
) == 0;
1102 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1103 *value
= iris_bo_export_gem_handle(bo
);
1105 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1106 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1116 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1117 struct pipe_context
*ctx
,
1118 struct pipe_resource
*resource
,
1119 struct winsys_handle
*whandle
,
1122 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1124 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1126 iris_resource_disable_aux_on_first_query(resource
, usage
);
1129 if (mod_with_aux
&& whandle
->plane
> 0) {
1130 assert(res
->aux
.bo
);
1132 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1133 whandle
->offset
= res
->aux
.offset
;
1135 /* If this is a buffer, stride should be 0 - no need to special case */
1136 whandle
->stride
= res
->surf
.row_pitch_B
;
1140 res
->mod_info
? res
->mod_info
->modifier
1141 : tiling_to_modifier(res
->bo
->tiling_mode
);
1144 enum isl_aux_usage allowed_usage
=
1145 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1147 if (res
->aux
.usage
!= allowed_usage
) {
1148 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1149 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1150 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1154 switch (whandle
->type
) {
1155 case WINSYS_HANDLE_TYPE_SHARED
:
1156 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1157 case WINSYS_HANDLE_TYPE_KMS
:
1158 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1160 case WINSYS_HANDLE_TYPE_FD
:
1161 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1168 resource_is_busy(struct iris_context
*ice
,
1169 struct iris_resource
*res
)
1171 bool busy
= iris_bo_busy(res
->bo
);
1173 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1174 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1180 iris_invalidate_resource(struct pipe_context
*ctx
,
1181 struct pipe_resource
*resource
)
1183 struct iris_screen
*screen
= (void *) ctx
->screen
;
1184 struct iris_context
*ice
= (void *) ctx
;
1185 struct iris_resource
*res
= (void *) resource
;
1187 if (resource
->target
!= PIPE_BUFFER
)
1190 if (!resource_is_busy(ice
, res
)) {
1191 /* The resource is idle, so just mark that it contains no data and
1192 * keep using the same underlying buffer object.
1194 util_range_set_empty(&res
->valid_buffer_range
);
1198 /* Otherwise, try and replace the backing storage with a new BO. */
1200 /* We can't reallocate memory we didn't allocate in the first place. */
1201 if (res
->bo
->userptr
)
1204 // XXX: We should support this.
1205 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1208 struct iris_bo
*old_bo
= res
->bo
;
1209 struct iris_bo
*new_bo
=
1210 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1211 iris_memzone_for_address(old_bo
->gtt_offset
));
1215 /* Swap out the backing storage */
1218 /* Rebind the buffer, replacing any state referring to the old BO's
1219 * address, and marking state dirty so it's reemitted.
1221 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1223 util_range_set_empty(&res
->valid_buffer_range
);
1225 iris_bo_unreference(old_bo
);
1229 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1230 const struct pipe_box
*flush_box
)
1232 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1235 struct iris_transfer
*map
= (void *) xfer
;
1237 struct pipe_box src_box
= *flush_box
;
1239 /* Account for extra alignment padding in staging buffer */
1240 if (xfer
->resource
->target
== PIPE_BUFFER
)
1241 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1243 struct pipe_box dst_box
= (struct pipe_box
) {
1244 .x
= xfer
->box
.x
+ flush_box
->x
,
1245 .y
= xfer
->box
.y
+ flush_box
->y
,
1246 .z
= xfer
->box
.z
+ flush_box
->z
,
1247 .width
= flush_box
->width
,
1248 .height
= flush_box
->height
,
1249 .depth
= flush_box
->depth
,
1252 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1253 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1258 iris_unmap_copy_region(struct iris_transfer
*map
)
1260 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1266 iris_map_copy_region(struct iris_transfer
*map
)
1268 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1269 struct pipe_transfer
*xfer
= &map
->base
;
1270 struct pipe_box
*box
= &xfer
->box
;
1271 struct iris_resource
*res
= (void *) xfer
->resource
;
1273 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1274 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1276 struct pipe_resource templ
= (struct pipe_resource
) {
1277 .usage
= PIPE_USAGE_STAGING
,
1278 .width0
= box
->width
+ extra
,
1279 .height0
= box
->height
,
1281 .nr_samples
= xfer
->resource
->nr_samples
,
1282 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1283 .array_size
= box
->depth
,
1284 .format
= res
->internal_format
,
1287 if (xfer
->resource
->target
== PIPE_BUFFER
)
1288 templ
.target
= PIPE_BUFFER
;
1289 else if (templ
.array_size
> 1)
1290 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1292 templ
.target
= PIPE_TEXTURE_2D
;
1294 map
->staging
= iris_resource_create(pscreen
, &templ
);
1295 assert(map
->staging
);
1297 if (templ
.target
!= PIPE_BUFFER
) {
1298 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1299 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1300 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1303 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1304 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1305 xfer
->resource
, xfer
->level
, box
);
1306 /* Ensure writes to the staging BO land before we map it below. */
1307 iris_emit_pipe_control_flush(map
->batch
,
1308 "transfer read: flush before mapping",
1309 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1310 PIPE_CONTROL_CS_STALL
);
1313 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1315 if (iris_batch_references(map
->batch
, staging_bo
))
1316 iris_batch_flush(map
->batch
);
1319 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1321 map
->unmap
= iris_unmap_copy_region
;
1325 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1326 unsigned *out_x0_el
, unsigned *out_y0_el
)
1328 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1329 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1331 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1336 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1337 * different tiling patterns.
1340 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1341 uint32_t *tile_w
, uint32_t *tile_h
)
1352 case ISL_TILING_LINEAR
:
1357 unreachable("not reached");
1363 * This function computes masks that may be used to select the bits of the X
1364 * and Y coordinates that indicate the offset within a tile. If the BO is
1365 * untiled, the masks are set to 0.
1368 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1369 uint32_t *mask_x
, uint32_t *mask_y
)
1371 uint32_t tile_w_bytes
, tile_h
;
1373 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1375 *mask_x
= tile_w_bytes
/ cpp
- 1;
1376 *mask_y
= tile_h
- 1;
1380 * Compute the offset (in bytes) from the start of the BO to the given x
1381 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1382 * multiples of the tile size.
1385 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1386 uint32_t x
, uint32_t y
)
1388 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1389 unsigned cpp
= fmtl
->bpb
/ 8;
1390 uint32_t pitch
= res
->surf
.row_pitch_B
;
1392 switch (res
->surf
.tiling
) {
1394 unreachable("not reached");
1395 case ISL_TILING_LINEAR
:
1396 return y
* pitch
+ x
* cpp
;
1398 assert((x
% (512 / cpp
)) == 0);
1399 assert((y
% 8) == 0);
1400 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1402 assert((x
% (128 / cpp
)) == 0);
1403 assert((y
% 32) == 0);
1404 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1409 * Rendering with tiled buffers requires that the base address of the buffer
1410 * be aligned to a page boundary. For renderbuffers, and sometimes with
1411 * textures, we may want the surface to point at a texture image level that
1412 * isn't at a page boundary.
1414 * This function returns an appropriately-aligned base offset
1415 * according to the tiling restrictions, plus any required x/y offset
1419 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1420 uint32_t level
, uint32_t z
,
1421 uint32_t *tile_x
, uint32_t *tile_y
)
1424 uint32_t mask_x
, mask_y
;
1426 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1427 const unsigned cpp
= fmtl
->bpb
/ 8;
1429 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1430 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1432 *tile_x
= x
& mask_x
;
1433 *tile_y
= y
& mask_y
;
1435 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1439 * Get pointer offset into stencil buffer.
1441 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1442 * must decode the tile's layout in software.
1445 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1447 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1449 * Even though the returned offset is always positive, the return type is
1451 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1452 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1455 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1457 uint32_t tile_size
= 4096;
1458 uint32_t tile_width
= 64;
1459 uint32_t tile_height
= 64;
1460 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1462 uint32_t tile_x
= x
/ tile_width
;
1463 uint32_t tile_y
= y
/ tile_height
;
1465 /* The byte's address relative to the tile's base addres. */
1466 uint32_t byte_x
= x
% tile_width
;
1467 uint32_t byte_y
= y
% tile_height
;
1469 uintptr_t u
= tile_y
* row_size
1470 + tile_x
* tile_size
1471 + 512 * (byte_x
/ 8)
1473 + 32 * ((byte_y
/ 4) % 2)
1474 + 16 * ((byte_x
/ 4) % 2)
1475 + 8 * ((byte_y
/ 2) % 2)
1476 + 4 * ((byte_x
/ 2) % 2)
1484 iris_unmap_s8(struct iris_transfer
*map
)
1486 struct pipe_transfer
*xfer
= &map
->base
;
1487 const struct pipe_box
*box
= &xfer
->box
;
1488 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1489 struct isl_surf
*surf
= &res
->surf
;
1491 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1492 uint8_t *untiled_s8_map
= map
->ptr
;
1493 uint8_t *tiled_s8_map
=
1494 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1496 for (int s
= 0; s
< box
->depth
; s
++) {
1497 unsigned x0_el
, y0_el
;
1498 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1500 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1501 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1502 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1504 y0_el
+ box
->y
+ y
);
1505 tiled_s8_map
[offset
] =
1506 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1516 iris_map_s8(struct iris_transfer
*map
)
1518 struct pipe_transfer
*xfer
= &map
->base
;
1519 const struct pipe_box
*box
= &xfer
->box
;
1520 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1521 struct isl_surf
*surf
= &res
->surf
;
1523 xfer
->stride
= surf
->row_pitch_B
;
1524 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1526 /* The tiling and detiling functions require that the linear buffer has
1527 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1528 * over-allocate the linear buffer to get the proper alignment.
1530 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1531 assert(map
->buffer
);
1533 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1534 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1535 * invalidate is set, since we'll be writing the whole rectangle from our
1536 * temporary buffer back out.
1538 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1539 uint8_t *untiled_s8_map
= map
->ptr
;
1540 uint8_t *tiled_s8_map
=
1541 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1543 for (int s
= 0; s
< box
->depth
; s
++) {
1544 unsigned x0_el
, y0_el
;
1545 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1547 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1548 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1549 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1551 y0_el
+ box
->y
+ y
);
1552 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1553 tiled_s8_map
[offset
];
1559 map
->unmap
= iris_unmap_s8
;
1562 /* Compute extent parameters for use with tiled_memcpy functions.
1563 * xs are in units of bytes and ys are in units of strides.
1566 tile_extents(const struct isl_surf
*surf
,
1567 const struct pipe_box
*box
,
1568 unsigned level
, int z
,
1569 unsigned *x1_B
, unsigned *x2_B
,
1570 unsigned *y1_el
, unsigned *y2_el
)
1572 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1573 const unsigned cpp
= fmtl
->bpb
/ 8;
1575 assert(box
->x
% fmtl
->bw
== 0);
1576 assert(box
->y
% fmtl
->bh
== 0);
1578 unsigned x0_el
, y0_el
;
1579 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1581 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1582 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1583 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1584 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1588 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1590 struct pipe_transfer
*xfer
= &map
->base
;
1591 const struct pipe_box
*box
= &xfer
->box
;
1592 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1593 struct isl_surf
*surf
= &res
->surf
;
1595 const bool has_swizzling
= false;
1597 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1599 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1601 for (int s
= 0; s
< box
->depth
; s
++) {
1602 unsigned x1
, x2
, y1
, y2
;
1603 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1605 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1607 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1608 surf
->row_pitch_B
, xfer
->stride
,
1609 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1612 os_free_aligned(map
->buffer
);
1613 map
->buffer
= map
->ptr
= NULL
;
1617 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1619 struct pipe_transfer
*xfer
= &map
->base
;
1620 const struct pipe_box
*box
= &xfer
->box
;
1621 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1622 struct isl_surf
*surf
= &res
->surf
;
1624 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1625 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1627 unsigned x1
, x2
, y1
, y2
;
1628 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1630 /* The tiling and detiling functions require that the linear buffer has
1631 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1632 * over-allocate the linear buffer to get the proper alignment.
1635 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1636 assert(map
->buffer
);
1637 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1639 const bool has_swizzling
= false;
1641 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1643 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1645 for (int s
= 0; s
< box
->depth
; s
++) {
1646 unsigned x1
, x2
, y1
, y2
;
1647 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1649 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1650 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1652 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1653 surf
->row_pitch_B
, has_swizzling
,
1654 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1658 map
->unmap
= iris_unmap_tiled_memcpy
;
1662 iris_map_direct(struct iris_transfer
*map
)
1664 struct pipe_transfer
*xfer
= &map
->base
;
1665 struct pipe_box
*box
= &xfer
->box
;
1666 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1668 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1670 if (res
->base
.target
== PIPE_BUFFER
) {
1672 xfer
->layer_stride
= 0;
1674 map
->ptr
= ptr
+ box
->x
;
1676 struct isl_surf
*surf
= &res
->surf
;
1677 const struct isl_format_layout
*fmtl
=
1678 isl_format_get_layout(surf
->format
);
1679 const unsigned cpp
= fmtl
->bpb
/ 8;
1680 unsigned x0_el
, y0_el
;
1682 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1684 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1685 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1687 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1692 can_promote_to_async(const struct iris_resource
*res
,
1693 const struct pipe_box
*box
,
1694 enum pipe_transfer_usage usage
)
1696 /* If we're writing to a section of the buffer that hasn't even been
1697 * initialized with useful data, then we can safely promote this write
1698 * to be unsynchronized. This helps the common pattern of appending data.
1700 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1701 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1702 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1703 box
->x
+ box
->width
);
1707 iris_transfer_map(struct pipe_context
*ctx
,
1708 struct pipe_resource
*resource
,
1710 enum pipe_transfer_usage usage
,
1711 const struct pipe_box
*box
,
1712 struct pipe_transfer
**ptransfer
)
1714 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1715 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1716 struct isl_surf
*surf
= &res
->surf
;
1718 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1719 /* Replace the backing storage with a fresh buffer for non-async maps */
1720 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1721 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1722 iris_invalidate_resource(ctx
, resource
);
1724 /* If we can discard the whole resource, we can discard the range. */
1725 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1728 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1729 can_promote_to_async(res
, box
, usage
)) {
1730 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1733 bool need_resolve
= false;
1734 bool need_color_resolve
= false;
1736 if (resource
->target
!= PIPE_BUFFER
) {
1737 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1739 need_color_resolve
=
1740 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1741 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1742 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1744 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1747 bool map_would_stall
= false;
1749 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1750 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1752 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1753 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1757 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1758 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1761 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1762 struct pipe_transfer
*xfer
= &map
->base
;
1767 memset(map
, 0, sizeof(*map
));
1768 map
->dbg
= &ice
->dbg
;
1770 pipe_resource_reference(&xfer
->resource
, resource
);
1771 xfer
->level
= level
;
1772 xfer
->usage
= usage
;
1776 map
->dest_had_defined_contents
=
1777 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1778 box
->x
+ box
->width
);
1780 if (usage
& PIPE_TRANSFER_WRITE
)
1781 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1783 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1784 * there is to access them simultaneously on the CPU & GPU. This also
1785 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1786 * contain state we're constructing for a GPU draw call, which would
1787 * kill us with infinite stack recursion.
1789 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1790 PIPE_TRANSFER_COHERENT
|
1791 PIPE_TRANSFER_MAP_DIRECTLY
);
1793 /* GPU copies are not useful for buffer reads. Instead of stalling to
1794 * read from the original buffer, we'd simply copy it to a temporary...
1795 * then stall (a bit longer) to read from that buffer.
1797 * Images are less clear-cut. Color resolves are destructive, removing
1798 * the underlying compression, so we'd rather blit the data to a linear
1799 * temporary and map that, to avoid the resolve. (It might be better to
1800 * a tiled temporary and use the tiled_memcpy paths...)
1802 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1805 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1806 if (fmtl
->txc
== ISL_TXC_ASTC
)
1809 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1810 /* If we need a synchronous mapping and the resource is busy, or needs
1811 * resolving, we copy to/from a linear temporary buffer using the GPU.
1813 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1814 map
->blorp
= &ice
->blorp
;
1815 iris_map_copy_region(map
);
1817 /* Otherwise we're free to map on the CPU. */
1820 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1821 level
, box
->z
, box
->depth
,
1822 usage
& PIPE_TRANSFER_WRITE
);
1825 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1826 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1827 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1828 iris_batch_flush(&ice
->batches
[i
]);
1832 if (surf
->tiling
== ISL_TILING_W
) {
1833 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1835 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1836 iris_map_tiled_memcpy(map
);
1838 iris_map_direct(map
);
1846 iris_transfer_flush_region(struct pipe_context
*ctx
,
1847 struct pipe_transfer
*xfer
,
1848 const struct pipe_box
*box
)
1850 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1851 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1852 struct iris_transfer
*map
= (void *) xfer
;
1855 iris_flush_staging_region(xfer
, box
);
1857 uint32_t history_flush
= 0;
1859 if (res
->base
.target
== PIPE_BUFFER
) {
1861 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1863 if (map
->dest_had_defined_contents
)
1864 history_flush
|= iris_flush_bits_for_history(res
);
1866 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1869 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1870 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1871 struct iris_batch
*batch
= &ice
->batches
[i
];
1872 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1873 iris_batch_maybe_flush(batch
, 24);
1874 iris_emit_pipe_control_flush(batch
,
1875 "cache history: transfer flush",
1881 /* Make sure we flag constants dirty even if there's no need to emit
1882 * any PIPE_CONTROLs to a batch.
1884 iris_dirty_for_history(ice
, res
);
1888 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1890 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1891 struct iris_transfer
*map
= (void *) xfer
;
1893 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1894 PIPE_TRANSFER_COHERENT
))) {
1895 struct pipe_box flush_box
= {
1896 .x
= 0, .y
= 0, .z
= 0,
1897 .width
= xfer
->box
.width
,
1898 .height
= xfer
->box
.height
,
1899 .depth
= xfer
->box
.depth
,
1901 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1907 pipe_resource_reference(&xfer
->resource
, NULL
);
1908 slab_free(&ice
->transfer_pool
, map
);
1912 * Mark state dirty that needs to be re-emitted when a resource is written.
1915 iris_dirty_for_history(struct iris_context
*ice
,
1916 struct iris_resource
*res
)
1918 uint64_t dirty
= 0ull;
1920 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1921 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
1924 ice
->state
.dirty
|= dirty
;
1928 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1929 * resource becomes visible, and any stale read cache data is invalidated.
1932 iris_flush_bits_for_history(struct iris_resource
*res
)
1934 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1936 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1937 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1938 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1941 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1942 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1944 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1945 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1947 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1948 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1954 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1955 struct iris_batch
*batch
,
1956 struct iris_resource
*res
,
1957 uint32_t extra_flags
,
1960 if (res
->base
.target
!= PIPE_BUFFER
)
1963 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
1965 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1967 iris_dirty_for_history(ice
, res
);
1971 iris_resource_set_clear_color(struct iris_context
*ice
,
1972 struct iris_resource
*res
,
1973 union isl_color_value color
)
1975 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1976 res
->aux
.clear_color
= color
;
1983 union isl_color_value
1984 iris_resource_get_clear_color(const struct iris_resource
*res
,
1985 struct iris_bo
**clear_color_bo
,
1986 uint64_t *clear_color_offset
)
1988 assert(res
->aux
.bo
);
1991 *clear_color_bo
= res
->aux
.clear_color_bo
;
1992 if (clear_color_offset
)
1993 *clear_color_offset
= res
->aux
.clear_color_offset
;
1994 return res
->aux
.clear_color
;
1997 static enum pipe_format
1998 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2000 struct iris_resource
*res
= (void *) p_res
;
2001 return res
->internal_format
;
2004 static const struct u_transfer_vtbl transfer_vtbl
= {
2005 .resource_create
= iris_resource_create
,
2006 .resource_destroy
= iris_resource_destroy
,
2007 .transfer_map
= iris_transfer_map
,
2008 .transfer_unmap
= iris_transfer_unmap
,
2009 .transfer_flush_region
= iris_transfer_flush_region
,
2010 .get_internal_format
= iris_resource_get_internal_format
,
2011 .set_stencil
= iris_resource_set_separate_stencil
,
2012 .get_stencil
= iris_resource_get_separate_stencil
,
2016 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2018 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2019 pscreen
->resource_create_with_modifiers
=
2020 iris_resource_create_with_modifiers
;
2021 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2022 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2023 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2024 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2025 pscreen
->resource_get_param
= iris_resource_get_param
;
2026 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2027 pscreen
->transfer_helper
=
2028 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2032 iris_init_resource_functions(struct pipe_context
*ctx
)
2034 ctx
->flush_resource
= iris_flush_resource
;
2035 ctx
->invalidate_resource
= iris_invalidate_resource
;
2036 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2037 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2038 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2039 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2040 ctx
->texture_subdata
= u_default_texture_subdata
;