2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
88 if (linear_format
== ISL_FORMAT_UNSUPPORTED
||
89 !isl_format_supports_ccs_e(devinfo
, linear_format
))
92 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
94 case I915_FORMAT_MOD_Y_TILED
:
95 case I915_FORMAT_MOD_X_TILED
:
96 case DRM_FORMAT_MOD_LINEAR
:
98 case DRM_FORMAT_MOD_INVALID
:
105 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
106 const uint64_t *modifiers
,
109 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
111 for (int i
= 0; i
< count
; i
++) {
112 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
115 switch (modifiers
[i
]) {
116 case I915_FORMAT_MOD_Y_TILED_CCS
:
117 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
119 case I915_FORMAT_MOD_Y_TILED
:
120 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
122 case I915_FORMAT_MOD_X_TILED
:
123 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
125 case DRM_FORMAT_MOD_LINEAR
:
126 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
128 case DRM_FORMAT_MOD_INVALID
:
134 return priority_to_modifier
[prio
];
138 target_to_isl_surf_dim(enum pipe_texture_target target
)
142 case PIPE_TEXTURE_1D
:
143 case PIPE_TEXTURE_1D_ARRAY
:
144 return ISL_SURF_DIM_1D
;
145 case PIPE_TEXTURE_2D
:
146 case PIPE_TEXTURE_CUBE
:
147 case PIPE_TEXTURE_RECT
:
148 case PIPE_TEXTURE_2D_ARRAY
:
149 case PIPE_TEXTURE_CUBE_ARRAY
:
150 return ISL_SURF_DIM_2D
;
151 case PIPE_TEXTURE_3D
:
152 return ISL_SURF_DIM_3D
;
153 case PIPE_MAX_TEXTURE_TYPES
:
156 unreachable("invalid texture type");
160 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
161 enum pipe_format pfmt
,
164 unsigned int *external_only
,
167 struct iris_screen
*screen
= (void *) pscreen
;
168 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
170 uint64_t all_modifiers
[] = {
171 DRM_FORMAT_MOD_LINEAR
,
172 I915_FORMAT_MOD_X_TILED
,
173 I915_FORMAT_MOD_Y_TILED
,
174 I915_FORMAT_MOD_Y_TILED_CCS
,
177 int supported_mods
= 0;
179 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
180 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
183 if (supported_mods
< max
) {
185 modifiers
[supported_mods
] = all_modifiers
[i
];
188 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
194 *count
= supported_mods
;
197 static isl_surf_usage_flags_t
198 pipe_bind_to_isl_usage(unsigned bindings
)
200 isl_surf_usage_flags_t usage
= 0;
202 if (bindings
& PIPE_BIND_RENDER_TARGET
)
203 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
205 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
206 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
208 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
209 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
211 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
212 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
217 struct pipe_resource
*
218 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
220 /* For packed depth-stencil, we treat depth as the primary resource
221 * and store S8 as the "second plane" resource.
223 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
231 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
232 struct pipe_resource
*stencil
)
234 assert(util_format_has_depth(util_format_description(p_res
->format
)));
235 pipe_resource_reference(&p_res
->next
, stencil
);
239 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
240 struct iris_resource
**out_z
,
241 struct iris_resource
**out_s
)
249 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
250 *out_z
= (void *) res
;
251 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
254 *out_s
= (void *) res
;
259 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
260 enum isl_tiling tiling
,
261 enum pipe_texture_target target
)
264 case PIPE_TEXTURE_1D
:
265 case PIPE_TEXTURE_1D_ARRAY
:
266 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
267 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
269 case PIPE_TEXTURE_2D
:
270 case PIPE_TEXTURE_2D_ARRAY
:
271 case PIPE_TEXTURE_RECT
:
272 case PIPE_TEXTURE_CUBE
:
273 case PIPE_TEXTURE_CUBE_ARRAY
:
274 return ISL_DIM_LAYOUT_GEN4_2D
;
276 case PIPE_TEXTURE_3D
:
277 return (devinfo
->gen
>= 9 ?
278 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
280 case PIPE_MAX_TEXTURE_TYPES
:
284 unreachable("invalid texture type");
288 iris_resource_disable_aux(struct iris_resource
*res
)
290 iris_bo_unreference(res
->aux
.bo
);
291 iris_bo_unreference(res
->aux
.clear_color_bo
);
292 free(res
->aux
.state
);
294 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
295 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
296 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
297 res
->aux
.has_hiz
= 0;
298 res
->aux
.surf
.size_B
= 0;
300 res
->aux
.extra_aux
.surf
.size_B
= 0;
301 res
->aux
.clear_color_bo
= NULL
;
302 res
->aux
.state
= NULL
;
306 iris_resource_destroy(struct pipe_screen
*screen
,
307 struct pipe_resource
*resource
)
309 struct iris_resource
*res
= (struct iris_resource
*)resource
;
311 if (resource
->target
== PIPE_BUFFER
)
312 util_range_destroy(&res
->valid_buffer_range
);
314 iris_resource_disable_aux(res
);
316 iris_bo_unreference(res
->bo
);
320 static struct iris_resource
*
321 iris_alloc_resource(struct pipe_screen
*pscreen
,
322 const struct pipe_resource
*templ
)
324 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
329 res
->base
.screen
= pscreen
;
330 pipe_reference_init(&res
->base
.reference
, 1);
332 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
333 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
335 if (templ
->target
== PIPE_BUFFER
)
336 util_range_init(&res
->valid_buffer_range
);
342 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
344 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
345 return minify(res
->surf
.logical_level0_px
.depth
, level
);
347 return res
->surf
.logical_level0_px
.array_len
;
350 static enum isl_aux_state
**
351 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
353 assert(res
->aux
.state
== NULL
);
355 uint32_t total_slices
= 0;
356 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
357 total_slices
+= iris_get_num_logical_layers(res
, level
);
359 const size_t per_level_array_size
=
360 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
362 /* We're going to allocate a single chunk of data for both the per-level
363 * reference array and the arrays of aux_state. This makes cleanup
364 * significantly easier.
366 const size_t total_size
=
367 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
369 void *data
= malloc(total_size
);
373 enum isl_aux_state
**per_level_arr
= data
;
374 enum isl_aux_state
*s
= data
+ per_level_array_size
;
375 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
376 per_level_arr
[level
] = s
;
377 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
378 for (uint32_t a
= 0; a
< level_layers
; a
++)
381 assert((void *)s
== data
+ total_size
);
383 return per_level_arr
;
387 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
389 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
390 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
394 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
396 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
397 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
398 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
400 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
401 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
402 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
403 res
->aux
.bo
->gtt_offset
+ aux_offset
);
404 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
409 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
410 enum isl_format format
)
412 if (!isl_format_supports_ccs_e(devinfo
, format
))
415 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
417 /* CCS_E seems to significantly hurt performance with 32-bit floating
418 * point formats. For example, Paraview's "Wavelet Volume" case uses
419 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
420 * formats causes a 62% FPS drop.
422 * However, many benchmarks seem to use 16-bit float with no issues.
424 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
431 * Configure aux for the resource, but don't allocate it. For images which
432 * might be shared with modifiers, we must allocate the image and aux data in
435 * Returns false on unexpected error (e.g. allocation failed, or invalid
436 * configuration result).
439 iris_resource_configure_aux(struct iris_screen
*screen
,
440 struct iris_resource
*res
, bool imported
,
441 uint64_t *aux_size_B
,
442 uint32_t *alloc_flags
)
444 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
446 /* Try to create the auxiliary surfaces allowed by the modifier or by
447 * the user if no modifier is specified.
449 assert(!res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
450 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
452 const bool has_mcs
= !res
->mod_info
&&
453 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
455 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
456 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
459 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
460 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
461 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
462 &res
->aux
.extra_aux
.surf
, 0);
464 /* Having both HIZ and MCS is impossible. */
465 assert(!has_mcs
|| !has_hiz
);
467 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
468 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
469 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
470 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
471 assert(res
->aux
.surf
.size_B
> 0 &&
472 res
->aux
.surf
.usage
&
473 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
476 if (res
->mod_info
&& has_ccs
) {
477 /* Only allow a CCS modifier if the aux was created successfully. */
478 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
479 } else if (has_mcs
) {
480 res
->aux
.possible_usages
|=
481 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
482 } else if (has_hiz
) {
484 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
485 } else if (res
->surf
.samples
== 1 &&
486 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
487 /* If this resource is single-sampled and will be used as a texture,
488 * put the HiZ surface in write-through mode so that we can sample
491 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
493 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
495 } else if (has_ccs
) {
496 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
))
497 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
499 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
500 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
503 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
505 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
507 /* We don't always support sampling with hiz. But when we do, it must be
510 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
511 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
513 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
514 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
516 enum isl_aux_state initial_state
;
519 assert(!res
->aux
.bo
);
521 switch (res
->aux
.usage
) {
522 case ISL_AUX_USAGE_NONE
:
523 /* Having no aux buffer is only okay if there's no modifier with aux. */
524 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
525 case ISL_AUX_USAGE_HIZ
:
526 case ISL_AUX_USAGE_HIZ_CCS
:
527 case ISL_AUX_USAGE_HIZ_CCS_WT
:
528 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
530 case ISL_AUX_USAGE_MCS
:
531 case ISL_AUX_USAGE_MCS_CCS
:
532 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
534 * "When MCS buffer is enabled and bound to MSRT, it is required
535 * that it is cleared prior to any rendering."
537 * Since we only use the MCS buffer for rendering, we just clear it
538 * immediately on allocation. The clear value for MCS buffers is all
539 * 1's, so we simply memset it to 0xff.
541 initial_state
= ISL_AUX_STATE_CLEAR
;
543 case ISL_AUX_USAGE_CCS_D
:
544 case ISL_AUX_USAGE_CCS_E
:
545 /* When CCS_E is used, we need to ensure that the CCS starts off in
546 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
549 * "If Software wants to enable Color Compression without Fast
550 * clear, Software needs to initialize MCS with zeros."
552 * A CCS value of 0 indicates that the corresponding block is in the
553 * pass-through state which is what we want.
555 * For CCS_D, do the same thing. On Gen9+, this avoids having any
556 * undefined bits in the aux buffer.
560 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
562 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
563 *alloc_flags
|= BO_ALLOC_ZEROED
;
565 case ISL_AUX_USAGE_MC
:
566 unreachable("Unsupported aux mode");
569 /* Create the aux_state for the auxiliary buffer. */
570 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
574 /* Increase the aux offset if the main and aux surfaces will share a BO. */
576 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
577 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
578 uint64_t size
= res
->aux
.surf
.size_B
;
580 /* Allocate space in the buffer for storing the CCS. */
581 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
582 const uint64_t padded_aux_size
=
583 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
584 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
585 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
588 /* Allocate space in the buffer for storing the clear color. On modern
589 * platforms (gen > 9), we can read it directly from such buffer.
591 * On gen <= 9, we are going to store the clear color on the buffer
592 * anyways, and copy it back to the surface state during state emission.
594 * Also add some padding to make sure the fast clear color state buffer
595 * starts at a 4K alignment. We believe that 256B might be enough, but due
596 * to lack of testing we will leave this as 4K for now.
598 size
= ALIGN(size
, 4096);
599 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
600 size
+= iris_get_aux_clear_color_state_size(screen
);
603 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
604 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
605 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
606 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
608 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
609 * For LOD == 0, we can grow the dimensions to make it work.
611 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
612 res
->aux
.has_hiz
|= 1 << level
;
620 * Initialize the aux buffer contents.
622 * Returns false on unexpected error (e.g. mapping a BO failed).
625 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
626 unsigned clear_color_state_size
)
628 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
629 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
634 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
635 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
636 memset((char*)map
+ res
->aux
.offset
, memset_value
,
637 res
->aux
.surf
.size_B
);
640 /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
641 * - If Software wants to enable Color Compression without Fast clear,
642 * Software needs to initialize MCS with zeros.
643 * - Lossless compression and CCS initialized to all F (using HW Fast
644 * Clear or SW direct Clear)
646 * We think, the first bullet point above is referring to CCS aux
647 * surface. Since we initialize the MCS in the clear state, we also
648 * initialize the CCS in the clear state (via SW direct clear) to keep
651 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
652 isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0,
653 res
->aux
.extra_aux
.surf
.size_B
);
655 /* Zero the indirect clear color to match ::fast_clear_color. */
656 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
657 clear_color_state_size
);
659 iris_bo_unmap(res
->aux
.bo
);
662 if (clear_color_state_size
> 0) {
663 res
->aux
.clear_color_bo
= res
->aux
.bo
;
664 iris_bo_reference(res
->aux
.clear_color_bo
);
671 * Allocate the initial aux surface for a resource based on aux.usage
673 * Returns false on unexpected error (e.g. allocation failed, or invalid
674 * configuration result).
677 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
678 struct iris_resource
*res
)
680 uint32_t alloc_flags
;
682 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
688 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
689 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
690 * of bytes instead of trying to recalculate based on different format
693 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
695 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
696 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
701 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
702 iris_get_aux_clear_color_state_size(screen
)))
705 map_aux_addresses(screen
, res
);
711 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
712 struct iris_resource
*res
)
714 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
715 assert(iris_resource_unfinished_aux_import(res
));
716 assert(!res
->mod_info
->supports_clear_color
);
718 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
719 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
722 assert(res
->bo
== aux_res
->aux
.bo
);
723 iris_bo_reference(aux_res
->aux
.bo
);
724 res
->aux
.bo
= aux_res
->aux
.bo
;
726 res
->aux
.offset
= aux_res
->aux
.offset
;
728 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
729 assert(res
->aux
.clear_color_bo
== NULL
);
730 res
->aux
.clear_color_offset
= 0;
732 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
734 unsigned clear_color_state_size
=
735 iris_get_aux_clear_color_state_size(screen
);
737 if (clear_color_state_size
> 0) {
738 res
->aux
.clear_color_bo
=
739 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
740 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
741 res
->aux
.clear_color_offset
= 0;
744 iris_resource_destroy(&screen
->base
, res
->base
.next
);
745 res
->base
.next
= NULL
;
748 static struct pipe_resource
*
749 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
750 const struct pipe_resource
*templ
)
752 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
753 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
755 assert(templ
->target
== PIPE_BUFFER
);
756 assert(templ
->height0
<= 1);
757 assert(templ
->depth0
<= 1);
758 assert(templ
->format
== PIPE_FORMAT_NONE
||
759 util_format_get_blocksize(templ
->format
) == 1);
761 res
->internal_format
= templ
->format
;
762 res
->surf
.tiling
= ISL_TILING_LINEAR
;
764 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
765 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
766 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
767 memzone
= IRIS_MEMZONE_SHADER
;
768 name
= "shader kernels";
769 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
770 memzone
= IRIS_MEMZONE_SURFACE
;
771 name
= "surface state";
772 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
773 memzone
= IRIS_MEMZONE_DYNAMIC
;
774 name
= "dynamic state";
777 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
779 iris_resource_destroy(pscreen
, &res
->base
);
786 static struct pipe_resource
*
787 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
788 const struct pipe_resource
*templ
,
789 const uint64_t *modifiers
,
792 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
793 struct gen_device_info
*devinfo
= &screen
->devinfo
;
794 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
799 const struct util_format_description
*format_desc
=
800 util_format_description(templ
->format
);
801 const bool has_depth
= util_format_has_depth(format_desc
);
803 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
805 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
807 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
808 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
810 tiling_flags
= 1 << res
->mod_info
->tiling
;
812 if (modifiers_count
> 0) {
813 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
817 /* Use linear for staging buffers */
818 if (templ
->usage
== PIPE_USAGE_STAGING
||
819 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
820 tiling_flags
= ISL_TILING_LINEAR_BIT
;
821 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
822 tiling_flags
= ISL_TILING_X_BIT
;
825 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
827 if (templ
->target
== PIPE_TEXTURE_CUBE
||
828 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
829 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
831 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
832 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
833 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
835 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
838 enum pipe_format pfmt
= templ
->format
;
839 res
->internal_format
= pfmt
;
841 /* Should be handled by u_transfer_helper */
842 assert(!util_format_is_depth_and_stencil(pfmt
));
844 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
845 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
847 UNUSED
const bool isl_surf_created_successfully
=
848 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
849 .dim
= target_to_isl_surf_dim(templ
->target
),
851 .width
= templ
->width0
,
852 .height
= templ
->height0
,
853 .depth
= templ
->depth0
,
854 .levels
= templ
->last_level
+ 1,
855 .array_len
= templ
->array_size
,
856 .samples
= MAX2(templ
->nr_samples
, 1),
857 .min_alignment_B
= 0,
860 .tiling_flags
= tiling_flags
);
861 assert(isl_surf_created_successfully
);
863 const char *name
= "miptree";
864 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
866 unsigned int flags
= 0;
867 if (templ
->usage
== PIPE_USAGE_STAGING
)
868 flags
|= BO_ALLOC_COHERENT
;
870 /* These are for u_upload_mgr buffers only */
871 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
872 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
873 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
875 uint32_t aux_preferred_alloc_flags
;
876 uint64_t aux_size
= 0;
877 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
878 &aux_preferred_alloc_flags
)) {
882 /* Modifiers require the aux data to be in the same buffer as the main
883 * surface, but we combine them even when a modifiers is not being used.
885 const uint64_t bo_size
=
886 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
887 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
888 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
890 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
891 res
->surf
.row_pitch_B
, flags
);
897 res
->aux
.bo
= res
->bo
;
898 iris_bo_reference(res
->aux
.bo
);
899 unsigned clear_color_state_size
=
900 iris_get_aux_clear_color_state_size(screen
);
901 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
903 map_aux_addresses(screen
, res
);
909 fprintf(stderr
, "XXX: resource creation failed\n");
910 iris_resource_destroy(pscreen
, &res
->base
);
915 static struct pipe_resource
*
916 iris_resource_create(struct pipe_screen
*pscreen
,
917 const struct pipe_resource
*templ
)
919 if (templ
->target
== PIPE_BUFFER
)
920 return iris_resource_create_for_buffer(pscreen
, templ
);
922 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
926 tiling_to_modifier(uint32_t tiling
)
928 static const uint64_t map
[] = {
929 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
930 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
931 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
934 assert(tiling
< ARRAY_SIZE(map
));
939 static struct pipe_resource
*
940 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
941 const struct pipe_resource
*templ
,
944 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
945 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
946 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
950 assert(templ
->target
== PIPE_BUFFER
);
952 res
->internal_format
= templ
->format
;
953 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
954 user_memory
, templ
->width0
,
961 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
966 static struct pipe_resource
*
967 iris_resource_from_handle(struct pipe_screen
*pscreen
,
968 const struct pipe_resource
*templ
,
969 struct winsys_handle
*whandle
,
972 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
973 struct gen_device_info
*devinfo
= &screen
->devinfo
;
974 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
975 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
976 const struct isl_drm_modifier_info
*mod_inf
=
977 isl_drm_modifier_get_info(whandle
->modifier
);
983 switch (whandle
->type
) {
984 case WINSYS_HANDLE_TYPE_FD
:
986 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
988 tiling
= I915_TILING_LAST
+ 1;
989 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
990 tiling
, whandle
->stride
);
992 case WINSYS_HANDLE_TYPE_SHARED
:
993 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
997 unreachable("invalid winsys handle type");
1002 res
->offset
= whandle
->offset
;
1004 if (mod_inf
== NULL
) {
1006 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1010 res
->external_format
= whandle
->format
;
1011 res
->mod_info
= mod_inf
;
1013 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1015 const struct iris_format_info fmt
=
1016 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1017 res
->internal_format
= templ
->format
;
1019 if (templ
->target
== PIPE_BUFFER
) {
1020 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1022 /* Create a surface for each plane specified by the external format. */
1023 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1024 UNUSED
const bool isl_surf_created_successfully
=
1025 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1026 .dim
= target_to_isl_surf_dim(templ
->target
),
1028 .width
= templ
->width0
,
1029 .height
= templ
->height0
,
1030 .depth
= templ
->depth0
,
1031 .levels
= templ
->last_level
+ 1,
1032 .array_len
= templ
->array_size
,
1033 .samples
= MAX2(templ
->nr_samples
, 1),
1034 .min_alignment_B
= 0,
1035 .row_pitch_B
= whandle
->stride
,
1037 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1038 assert(isl_surf_created_successfully
);
1039 assert(res
->bo
->tiling_mode
==
1040 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1042 // XXX: create_ccs_buf_for_image?
1043 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1044 if (!iris_resource_alloc_separate_aux(screen
, res
))
1047 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1048 uint32_t alloc_flags
;
1050 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1053 /* The gallium dri layer will create a separate plane resource
1054 * for the aux image. iris_resource_finish_aux_import will
1055 * merge the separate aux parameters back into a single
1061 /* Save modifier import information to reconstruct later. After
1062 * import, this will be available under a second image accessible
1063 * from the main image with res->base.next. See
1064 * iris_resource_finish_aux_import.
1066 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1067 res
->aux
.offset
= whandle
->offset
;
1068 res
->aux
.bo
= res
->bo
;
1076 iris_resource_destroy(pscreen
, &res
->base
);
1081 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1083 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1084 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1085 struct iris_resource
*res
= (void *) resource
;
1086 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1088 iris_resource_prepare_access(ice
, render_batch
, res
,
1089 0, INTEL_REMAINING_LEVELS
,
1090 0, INTEL_REMAINING_LAYERS
,
1091 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1092 mod
? mod
->supports_clear_color
: false);
1096 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1099 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1101 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1103 /* Disable aux usage if explicit flush not set and this is the first time
1104 * we are dealing with this resource and the resource was not created with
1105 * a modifier with aux.
1107 if (!mod_with_aux
&&
1108 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1109 p_atomic_read(&resource
->reference
.count
) == 1) {
1110 iris_resource_disable_aux(res
);
1115 iris_resource_get_param(struct pipe_screen
*screen
,
1116 struct pipe_context
*context
,
1117 struct pipe_resource
*resource
,
1120 enum pipe_resource_param param
,
1121 unsigned handle_usage
,
1124 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1126 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1127 bool wants_aux
= mod_with_aux
&& plane
> 0;
1131 if (iris_resource_unfinished_aux_import(res
))
1132 iris_resource_finish_aux_import(screen
, res
);
1134 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1136 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1139 case PIPE_RESOURCE_PARAM_NPLANES
:
1144 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1149 case PIPE_RESOURCE_PARAM_STRIDE
:
1150 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1152 case PIPE_RESOURCE_PARAM_OFFSET
:
1153 *value
= wants_aux
? res
->aux
.offset
: 0;
1155 case PIPE_RESOURCE_PARAM_MODIFIER
:
1156 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1157 tiling_to_modifier(res
->bo
->tiling_mode
);
1159 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1160 result
= iris_bo_flink(bo
, &handle
) == 0;
1164 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1165 *value
= iris_bo_export_gem_handle(bo
);
1167 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1168 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1178 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1179 struct pipe_context
*ctx
,
1180 struct pipe_resource
*resource
,
1181 struct winsys_handle
*whandle
,
1184 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1186 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1188 iris_resource_disable_aux_on_first_query(resource
, usage
);
1191 if (mod_with_aux
&& whandle
->plane
> 0) {
1192 assert(res
->aux
.bo
);
1194 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1195 whandle
->offset
= res
->aux
.offset
;
1197 /* If this is a buffer, stride should be 0 - no need to special case */
1198 whandle
->stride
= res
->surf
.row_pitch_B
;
1202 whandle
->format
= res
->external_format
;
1204 res
->mod_info
? res
->mod_info
->modifier
1205 : tiling_to_modifier(res
->bo
->tiling_mode
);
1208 enum isl_aux_usage allowed_usage
=
1209 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1211 if (res
->aux
.usage
!= allowed_usage
) {
1212 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1213 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1214 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1218 switch (whandle
->type
) {
1219 case WINSYS_HANDLE_TYPE_SHARED
:
1220 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1221 case WINSYS_HANDLE_TYPE_KMS
:
1222 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1224 case WINSYS_HANDLE_TYPE_FD
:
1225 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1232 resource_is_busy(struct iris_context
*ice
,
1233 struct iris_resource
*res
)
1235 bool busy
= iris_bo_busy(res
->bo
);
1237 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1238 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1244 iris_invalidate_resource(struct pipe_context
*ctx
,
1245 struct pipe_resource
*resource
)
1247 struct iris_screen
*screen
= (void *) ctx
->screen
;
1248 struct iris_context
*ice
= (void *) ctx
;
1249 struct iris_resource
*res
= (void *) resource
;
1251 if (resource
->target
!= PIPE_BUFFER
)
1254 /* If it's already invalidated, don't bother doing anything. */
1255 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1258 if (!resource_is_busy(ice
, res
)) {
1259 /* The resource is idle, so just mark that it contains no data and
1260 * keep using the same underlying buffer object.
1262 util_range_set_empty(&res
->valid_buffer_range
);
1266 /* Otherwise, try and replace the backing storage with a new BO. */
1268 /* We can't reallocate memory we didn't allocate in the first place. */
1269 if (res
->bo
->userptr
)
1272 // XXX: We should support this.
1273 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1276 struct iris_bo
*old_bo
= res
->bo
;
1277 struct iris_bo
*new_bo
=
1278 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1279 iris_memzone_for_address(old_bo
->gtt_offset
));
1283 /* Swap out the backing storage */
1286 /* Rebind the buffer, replacing any state referring to the old BO's
1287 * address, and marking state dirty so it's reemitted.
1289 ice
->vtbl
.rebind_buffer(ice
, res
);
1291 util_range_set_empty(&res
->valid_buffer_range
);
1293 iris_bo_unreference(old_bo
);
1297 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1298 const struct pipe_box
*flush_box
)
1300 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1303 struct iris_transfer
*map
= (void *) xfer
;
1305 struct pipe_box src_box
= *flush_box
;
1307 /* Account for extra alignment padding in staging buffer */
1308 if (xfer
->resource
->target
== PIPE_BUFFER
)
1309 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1311 struct pipe_box dst_box
= (struct pipe_box
) {
1312 .x
= xfer
->box
.x
+ flush_box
->x
,
1313 .y
= xfer
->box
.y
+ flush_box
->y
,
1314 .z
= xfer
->box
.z
+ flush_box
->z
,
1315 .width
= flush_box
->width
,
1316 .height
= flush_box
->height
,
1317 .depth
= flush_box
->depth
,
1320 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1321 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1326 iris_unmap_copy_region(struct iris_transfer
*map
)
1328 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1334 iris_map_copy_region(struct iris_transfer
*map
)
1336 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1337 struct pipe_transfer
*xfer
= &map
->base
;
1338 struct pipe_box
*box
= &xfer
->box
;
1339 struct iris_resource
*res
= (void *) xfer
->resource
;
1341 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1342 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1344 struct pipe_resource templ
= (struct pipe_resource
) {
1345 .usage
= PIPE_USAGE_STAGING
,
1346 .width0
= box
->width
+ extra
,
1347 .height0
= box
->height
,
1349 .nr_samples
= xfer
->resource
->nr_samples
,
1350 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1351 .array_size
= box
->depth
,
1352 .format
= res
->internal_format
,
1355 if (xfer
->resource
->target
== PIPE_BUFFER
)
1356 templ
.target
= PIPE_BUFFER
;
1357 else if (templ
.array_size
> 1)
1358 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1360 templ
.target
= PIPE_TEXTURE_2D
;
1362 map
->staging
= iris_resource_create(pscreen
, &templ
);
1363 assert(map
->staging
);
1365 if (templ
.target
!= PIPE_BUFFER
) {
1366 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1367 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1368 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1371 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1372 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1373 xfer
->resource
, xfer
->level
, box
);
1374 /* Ensure writes to the staging BO land before we map it below. */
1375 iris_emit_pipe_control_flush(map
->batch
,
1376 "transfer read: flush before mapping",
1377 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1378 PIPE_CONTROL_CS_STALL
);
1381 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1383 if (iris_batch_references(map
->batch
, staging_bo
))
1384 iris_batch_flush(map
->batch
);
1387 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1389 map
->unmap
= iris_unmap_copy_region
;
1393 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1394 unsigned *out_x0_el
, unsigned *out_y0_el
)
1396 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1397 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1399 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1404 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1405 * different tiling patterns.
1408 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1409 uint32_t *tile_w
, uint32_t *tile_h
)
1420 case ISL_TILING_LINEAR
:
1425 unreachable("not reached");
1431 * This function computes masks that may be used to select the bits of the X
1432 * and Y coordinates that indicate the offset within a tile. If the BO is
1433 * untiled, the masks are set to 0.
1436 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1437 uint32_t *mask_x
, uint32_t *mask_y
)
1439 uint32_t tile_w_bytes
, tile_h
;
1441 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1443 *mask_x
= tile_w_bytes
/ cpp
- 1;
1444 *mask_y
= tile_h
- 1;
1448 * Compute the offset (in bytes) from the start of the BO to the given x
1449 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1450 * multiples of the tile size.
1453 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1454 uint32_t x
, uint32_t y
)
1456 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1457 unsigned cpp
= fmtl
->bpb
/ 8;
1458 uint32_t pitch
= res
->surf
.row_pitch_B
;
1460 switch (res
->surf
.tiling
) {
1462 unreachable("not reached");
1463 case ISL_TILING_LINEAR
:
1464 return y
* pitch
+ x
* cpp
;
1466 assert((x
% (512 / cpp
)) == 0);
1467 assert((y
% 8) == 0);
1468 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1470 assert((x
% (128 / cpp
)) == 0);
1471 assert((y
% 32) == 0);
1472 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1477 * Rendering with tiled buffers requires that the base address of the buffer
1478 * be aligned to a page boundary. For renderbuffers, and sometimes with
1479 * textures, we may want the surface to point at a texture image level that
1480 * isn't at a page boundary.
1482 * This function returns an appropriately-aligned base offset
1483 * according to the tiling restrictions, plus any required x/y offset
1487 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1488 uint32_t level
, uint32_t z
,
1489 uint32_t *tile_x
, uint32_t *tile_y
)
1492 uint32_t mask_x
, mask_y
;
1494 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1495 const unsigned cpp
= fmtl
->bpb
/ 8;
1497 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1498 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1500 *tile_x
= x
& mask_x
;
1501 *tile_y
= y
& mask_y
;
1503 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1507 * Get pointer offset into stencil buffer.
1509 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1510 * must decode the tile's layout in software.
1513 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1515 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1517 * Even though the returned offset is always positive, the return type is
1519 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1520 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1523 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1525 uint32_t tile_size
= 4096;
1526 uint32_t tile_width
= 64;
1527 uint32_t tile_height
= 64;
1528 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1530 uint32_t tile_x
= x
/ tile_width
;
1531 uint32_t tile_y
= y
/ tile_height
;
1533 /* The byte's address relative to the tile's base addres. */
1534 uint32_t byte_x
= x
% tile_width
;
1535 uint32_t byte_y
= y
% tile_height
;
1537 uintptr_t u
= tile_y
* row_size
1538 + tile_x
* tile_size
1539 + 512 * (byte_x
/ 8)
1541 + 32 * ((byte_y
/ 4) % 2)
1542 + 16 * ((byte_x
/ 4) % 2)
1543 + 8 * ((byte_y
/ 2) % 2)
1544 + 4 * ((byte_x
/ 2) % 2)
1552 iris_unmap_s8(struct iris_transfer
*map
)
1554 struct pipe_transfer
*xfer
= &map
->base
;
1555 const struct pipe_box
*box
= &xfer
->box
;
1556 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1557 struct isl_surf
*surf
= &res
->surf
;
1559 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1560 uint8_t *untiled_s8_map
= map
->ptr
;
1561 uint8_t *tiled_s8_map
=
1562 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1564 for (int s
= 0; s
< box
->depth
; s
++) {
1565 unsigned x0_el
, y0_el
;
1566 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1568 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1569 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1570 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1572 y0_el
+ box
->y
+ y
);
1573 tiled_s8_map
[offset
] =
1574 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1584 iris_map_s8(struct iris_transfer
*map
)
1586 struct pipe_transfer
*xfer
= &map
->base
;
1587 const struct pipe_box
*box
= &xfer
->box
;
1588 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1589 struct isl_surf
*surf
= &res
->surf
;
1591 xfer
->stride
= surf
->row_pitch_B
;
1592 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1594 /* The tiling and detiling functions require that the linear buffer has
1595 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1596 * over-allocate the linear buffer to get the proper alignment.
1598 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1599 assert(map
->buffer
);
1601 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1602 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1603 * invalidate is set, since we'll be writing the whole rectangle from our
1604 * temporary buffer back out.
1606 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1607 uint8_t *untiled_s8_map
= map
->ptr
;
1608 uint8_t *tiled_s8_map
=
1609 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1611 for (int s
= 0; s
< box
->depth
; s
++) {
1612 unsigned x0_el
, y0_el
;
1613 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1615 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1616 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1617 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1619 y0_el
+ box
->y
+ y
);
1620 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1621 tiled_s8_map
[offset
];
1627 map
->unmap
= iris_unmap_s8
;
1630 /* Compute extent parameters for use with tiled_memcpy functions.
1631 * xs are in units of bytes and ys are in units of strides.
1634 tile_extents(const struct isl_surf
*surf
,
1635 const struct pipe_box
*box
,
1636 unsigned level
, int z
,
1637 unsigned *x1_B
, unsigned *x2_B
,
1638 unsigned *y1_el
, unsigned *y2_el
)
1640 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1641 const unsigned cpp
= fmtl
->bpb
/ 8;
1643 assert(box
->x
% fmtl
->bw
== 0);
1644 assert(box
->y
% fmtl
->bh
== 0);
1646 unsigned x0_el
, y0_el
;
1647 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1649 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1650 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1651 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1652 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1656 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1658 struct pipe_transfer
*xfer
= &map
->base
;
1659 const struct pipe_box
*box
= &xfer
->box
;
1660 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1661 struct isl_surf
*surf
= &res
->surf
;
1663 const bool has_swizzling
= false;
1665 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1667 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1669 for (int s
= 0; s
< box
->depth
; s
++) {
1670 unsigned x1
, x2
, y1
, y2
;
1671 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1673 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1675 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1676 surf
->row_pitch_B
, xfer
->stride
,
1677 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1680 os_free_aligned(map
->buffer
);
1681 map
->buffer
= map
->ptr
= NULL
;
1685 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1687 struct pipe_transfer
*xfer
= &map
->base
;
1688 const struct pipe_box
*box
= &xfer
->box
;
1689 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1690 struct isl_surf
*surf
= &res
->surf
;
1692 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1693 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1695 unsigned x1
, x2
, y1
, y2
;
1696 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1698 /* The tiling and detiling functions require that the linear buffer has
1699 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1700 * over-allocate the linear buffer to get the proper alignment.
1703 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1704 assert(map
->buffer
);
1705 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1707 const bool has_swizzling
= false;
1709 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1711 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1713 for (int s
= 0; s
< box
->depth
; s
++) {
1714 unsigned x1
, x2
, y1
, y2
;
1715 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1717 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1718 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1720 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1721 surf
->row_pitch_B
, has_swizzling
,
1722 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1726 map
->unmap
= iris_unmap_tiled_memcpy
;
1730 iris_map_direct(struct iris_transfer
*map
)
1732 struct pipe_transfer
*xfer
= &map
->base
;
1733 struct pipe_box
*box
= &xfer
->box
;
1734 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1736 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1738 if (res
->base
.target
== PIPE_BUFFER
) {
1740 xfer
->layer_stride
= 0;
1742 map
->ptr
= ptr
+ box
->x
;
1744 struct isl_surf
*surf
= &res
->surf
;
1745 const struct isl_format_layout
*fmtl
=
1746 isl_format_get_layout(surf
->format
);
1747 const unsigned cpp
= fmtl
->bpb
/ 8;
1748 unsigned x0_el
, y0_el
;
1750 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1752 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1753 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1755 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1760 can_promote_to_async(const struct iris_resource
*res
,
1761 const struct pipe_box
*box
,
1762 enum pipe_transfer_usage usage
)
1764 /* If we're writing to a section of the buffer that hasn't even been
1765 * initialized with useful data, then we can safely promote this write
1766 * to be unsynchronized. This helps the common pattern of appending data.
1768 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1769 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1770 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1771 box
->x
+ box
->width
);
1775 iris_transfer_map(struct pipe_context
*ctx
,
1776 struct pipe_resource
*resource
,
1778 enum pipe_transfer_usage usage
,
1779 const struct pipe_box
*box
,
1780 struct pipe_transfer
**ptransfer
)
1782 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1783 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1784 struct isl_surf
*surf
= &res
->surf
;
1786 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1787 /* Replace the backing storage with a fresh buffer for non-async maps */
1788 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1789 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1790 iris_invalidate_resource(ctx
, resource
);
1792 /* If we can discard the whole resource, we can discard the range. */
1793 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1796 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1797 can_promote_to_async(res
, box
, usage
)) {
1798 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1801 bool need_resolve
= false;
1802 bool need_color_resolve
= false;
1804 if (resource
->target
!= PIPE_BUFFER
) {
1805 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1807 need_color_resolve
=
1808 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1809 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) &&
1810 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1812 need_resolve
= need_color_resolve
|| need_hiz_resolve
;
1815 bool map_would_stall
= false;
1817 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1818 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1820 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1821 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1825 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1826 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1829 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1830 struct pipe_transfer
*xfer
= &map
->base
;
1835 memset(map
, 0, sizeof(*map
));
1836 map
->dbg
= &ice
->dbg
;
1838 pipe_resource_reference(&xfer
->resource
, resource
);
1839 xfer
->level
= level
;
1840 xfer
->usage
= usage
;
1844 map
->dest_had_defined_contents
=
1845 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1846 box
->x
+ box
->width
);
1848 if (usage
& PIPE_TRANSFER_WRITE
)
1849 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1851 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1852 * there is to access them simultaneously on the CPU & GPU. This also
1853 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1854 * contain state we're constructing for a GPU draw call, which would
1855 * kill us with infinite stack recursion.
1857 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1858 PIPE_TRANSFER_COHERENT
|
1859 PIPE_TRANSFER_MAP_DIRECTLY
);
1861 /* GPU copies are not useful for buffer reads. Instead of stalling to
1862 * read from the original buffer, we'd simply copy it to a temporary...
1863 * then stall (a bit longer) to read from that buffer.
1865 * Images are less clear-cut. Color resolves are destructive, removing
1866 * the underlying compression, so we'd rather blit the data to a linear
1867 * temporary and map that, to avoid the resolve. (It might be better to
1868 * a tiled temporary and use the tiled_memcpy paths...)
1870 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1873 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1874 if (fmtl
->txc
== ISL_TXC_ASTC
)
1877 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1878 /* If we need a synchronous mapping and the resource is busy, or needs
1879 * resolving, we copy to/from a linear temporary buffer using the GPU.
1881 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1882 map
->blorp
= &ice
->blorp
;
1883 iris_map_copy_region(map
);
1885 /* Otherwise we're free to map on the CPU. */
1888 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1889 level
, box
->z
, box
->depth
,
1890 usage
& PIPE_TRANSFER_WRITE
);
1893 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1894 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1895 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1896 iris_batch_flush(&ice
->batches
[i
]);
1900 if (surf
->tiling
== ISL_TILING_W
) {
1901 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1903 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1904 iris_map_tiled_memcpy(map
);
1906 iris_map_direct(map
);
1914 iris_transfer_flush_region(struct pipe_context
*ctx
,
1915 struct pipe_transfer
*xfer
,
1916 const struct pipe_box
*box
)
1918 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1919 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1920 struct iris_transfer
*map
= (void *) xfer
;
1923 iris_flush_staging_region(xfer
, box
);
1925 uint32_t history_flush
= 0;
1927 if (res
->base
.target
== PIPE_BUFFER
) {
1929 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1931 if (map
->dest_had_defined_contents
)
1932 history_flush
|= iris_flush_bits_for_history(res
);
1934 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1937 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1938 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1939 struct iris_batch
*batch
= &ice
->batches
[i
];
1940 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1941 iris_batch_maybe_flush(batch
, 24);
1942 iris_emit_pipe_control_flush(batch
,
1943 "cache history: transfer flush",
1949 /* Make sure we flag constants dirty even if there's no need to emit
1950 * any PIPE_CONTROLs to a batch.
1952 iris_dirty_for_history(ice
, res
);
1956 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1958 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1959 struct iris_transfer
*map
= (void *) xfer
;
1961 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
1962 PIPE_TRANSFER_COHERENT
))) {
1963 struct pipe_box flush_box
= {
1964 .x
= 0, .y
= 0, .z
= 0,
1965 .width
= xfer
->box
.width
,
1966 .height
= xfer
->box
.height
,
1967 .depth
= xfer
->box
.depth
,
1969 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1975 pipe_resource_reference(&xfer
->resource
, NULL
);
1976 slab_free(&ice
->transfer_pool
, map
);
1980 * Mark state dirty that needs to be re-emitted when a resource is written.
1983 iris_dirty_for_history(struct iris_context
*ice
,
1984 struct iris_resource
*res
)
1986 uint64_t dirty
= 0ull;
1988 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1989 dirty
|= ((uint64_t)res
->bind_stages
) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS
;
1992 ice
->state
.dirty
|= dirty
;
1996 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1997 * resource becomes visible, and any stale read cache data is invalidated.
2000 iris_flush_bits_for_history(struct iris_resource
*res
)
2002 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2004 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2005 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2006 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2009 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2010 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2012 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2013 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2015 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2016 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2022 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2023 struct iris_batch
*batch
,
2024 struct iris_resource
*res
,
2025 uint32_t extra_flags
,
2028 if (res
->base
.target
!= PIPE_BUFFER
)
2031 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2033 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2035 iris_dirty_for_history(ice
, res
);
2039 iris_resource_set_clear_color(struct iris_context
*ice
,
2040 struct iris_resource
*res
,
2041 union isl_color_value color
)
2043 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2044 res
->aux
.clear_color
= color
;
2051 union isl_color_value
2052 iris_resource_get_clear_color(const struct iris_resource
*res
,
2053 struct iris_bo
**clear_color_bo
,
2054 uint64_t *clear_color_offset
)
2056 assert(res
->aux
.bo
);
2059 *clear_color_bo
= res
->aux
.clear_color_bo
;
2060 if (clear_color_offset
)
2061 *clear_color_offset
= res
->aux
.clear_color_offset
;
2062 return res
->aux
.clear_color
;
2065 static enum pipe_format
2066 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2068 struct iris_resource
*res
= (void *) p_res
;
2069 return res
->internal_format
;
2072 static const struct u_transfer_vtbl transfer_vtbl
= {
2073 .resource_create
= iris_resource_create
,
2074 .resource_destroy
= iris_resource_destroy
,
2075 .transfer_map
= iris_transfer_map
,
2076 .transfer_unmap
= iris_transfer_unmap
,
2077 .transfer_flush_region
= iris_transfer_flush_region
,
2078 .get_internal_format
= iris_resource_get_internal_format
,
2079 .set_stencil
= iris_resource_set_separate_stencil
,
2080 .get_stencil
= iris_resource_get_separate_stencil
,
2084 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2086 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2087 pscreen
->resource_create_with_modifiers
=
2088 iris_resource_create_with_modifiers
;
2089 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2090 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2091 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2092 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2093 pscreen
->resource_get_param
= iris_resource_get_param
;
2094 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2095 pscreen
->transfer_helper
=
2096 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2100 iris_init_resource_functions(struct pipe_context
*ctx
)
2102 ctx
->flush_resource
= iris_flush_resource
;
2103 ctx
->invalidate_resource
= iris_invalidate_resource
;
2104 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2105 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2106 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2107 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2108 ctx
->texture_subdata
= u_default_texture_subdata
;