src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_range.h"
  29 #include "intel/isl/isl.h"
  30 #include "iris_bufmgr.h"
  31
  32 struct iris_batch;
  33 struct iris_context;
  34 struct shader_info;
  35
  36 #define IRIS_MAX_MIPLEVELS 15
  37
  38 struct iris_format_info {
  39    enum isl_format fmt;
  40    struct isl_swizzle swizzle;
  41 };
  42
  43 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  44 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  45 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  46
  47 /**
  48  * Resources represent a GPU buffer object or image (mipmap tree).
  49  *
  50  * They contain the storage (BO) and layout information (ISL surface).
  51  */
  52 struct iris_resource {
  53    struct pipe_resource base;
  54    enum pipe_format internal_format;
  55
  56    /**
  57     * The ISL surface layout information for this resource.
  58     *
  59     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  60     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  61     * will be ISL_TILING_LINEAR, so it's safe to check that.
  62     */
  63    struct isl_surf surf;
  64
  65    /** Backing storage for the resource */
  66    struct iris_bo *bo;
  67
  68    /** offset at which data starts in the BO */
  69    uint64_t offset;
  70
  71    /**
  72     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  73     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  74     */
  75    unsigned bind_history;
  76
  77    /**
  78     * A bitfield of MESA_SHADER_* stages indicating where this resource
  79     * was bound.
  80     */
  81    unsigned bind_stages;
  82
  83    /**
  84     * For PIPE_BUFFER resources, a range which may contain valid data.
  85     *
  86     * This is a conservative estimate of what part of the buffer contains
  87     * valid data that we have to preserve.  The rest of the buffer is
  88     * considered invalid, and we can promote writes to that region to
  89     * be unsynchronized writes, avoiding blit copies.
  90     */
  91    struct util_range valid_buffer_range;
  92
  93    /**
  94     * Auxiliary buffer information (CCS, MCS, or HiZ).
  95     */
  96    struct {
  97       /** The surface layout for the auxiliary buffer. */
  98       struct isl_surf surf;
  99
 100       /** The buffer object containing the auxiliary data. */
 101       struct iris_bo *bo;
 102
 103       /** Offset into 'bo' where the auxiliary surface starts. */
 104       uint32_t offset;
 105
 106       struct {
 107          struct isl_surf surf;
 108
 109          /** Offset into 'bo' where the auxiliary surface starts. */
 110          uint32_t offset;
 111       } extra_aux;
 112
 113       /**
 114        * Fast clear color for this surface.  For depth surfaces, the clear
 115        * value is stored as a float32 in the red component.
 116        */
 117       union isl_color_value clear_color;
 118
 119       /** Buffer object containing the indirect clear color.  */
 120       struct iris_bo *clear_color_bo;
 121
 122       /** Offset into bo where the clear color can be found.  */
 123       uint64_t clear_color_offset;
 124
 125       /**
 126        * \brief The type of auxiliary compression used by this resource.
 127        *
 128        * This describes the type of auxiliary compression that is intended to
 129        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
 130        * that auxiliary compression is permanently disabled.  An aux usage
 131        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
 132        * compression will always be enabled for this surface.
 133        */
 134       enum isl_aux_usage usage;
 135
 136       /**
 137        * A bitfield of ISL_AUX_* modes that might this resource might use.
 138        *
 139        * For example, a surface might use both CCS_E and CCS_D at times.
 140        */
 141       unsigned possible_usages;
 142
 143       /**
 144        * Same as possible_usages, but only with modes supported for sampling.
 145        */
 146       unsigned sampler_usages;
 147
 148       /**
 149        * \brief Maps miptree slices to their current aux state.
 150        *
 151        * This two-dimensional array is indexed as [level][layer] and stores an
 152        * aux state for each slice.
 153        */
 154       enum isl_aux_state **state;
 155
 156       /**
 157        * If (1 << level) is set, HiZ is enabled for that miplevel.
 158        */
 159       uint16_t has_hiz;
 160    } aux;
 161
 162    /**
 163     * For external surfaces, this is format that was used to create or import
 164     * the surface. For internal surfaces, this will always be
 165     * PIPE_FORMAT_NONE.
 166     */
 167    enum pipe_format external_format;
 168
 169    /**
 170     * For external surfaces, this is DRM format modifier that was used to
 171     * create or import the surface.  For internal surfaces, this will always
 172     * be DRM_FORMAT_MOD_INVALID.
 173     */
 174    const struct isl_drm_modifier_info *mod_info;
 175 };
 176
 177 /**
 178  * A simple <resource, offset> tuple for storing a reference to a
 179  * piece of state stored in a GPU buffer object.
 180  */
 181 struct iris_state_ref {
 182    struct pipe_resource *res;
 183    uint32_t offset;
 184 };
 185
 186 /**
 187  * The SURFACE_STATE descriptors for a resource.
 188  */
 189 struct iris_surface_state {
 190    /**
 191     * CPU-side copy of the packed SURFACE_STATE structures, already
 192     * aligned so they can be uploaded as a contiguous pile of bytes.
 193     *
 194     * This can be updated and re-uploaded if (e.g.) addresses need to change.
 195     */
 196    uint32_t *cpu;
 197
 198    /**
 199     * How many states are there?  (Each aux mode has its own state.)
 200     */
 201    unsigned num_states;
 202
 203    /**
 204     * Address of the resource (res->bo->gtt_offset).  Note that "Surface
 205     * Base Address" may be offset from this value.
 206     */
 207    uint64_t bo_address;
 208
 209    /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
 210    struct iris_state_ref ref;
 211 };
 212
 213 /**
 214  * Gallium CSO for sampler views (texture views).
 215  *
 216  * In addition to the normal pipe_resource, this adds an ISL view
 217  * which may reinterpret the format or restrict levels/layers.
 218  *
 219  * These can also be linear texture buffers.
 220  */
 221 struct iris_sampler_view {
 222    struct pipe_sampler_view base;
 223    struct isl_view view;
 224
 225    union isl_color_value clear_color;
 226
 227    /* A short-cut (not a reference) to the actual resource being viewed.
 228     * Multi-planar (or depth+stencil) images may have multiple resources
 229     * chained together; this skips having to traverse base->texture->*.
 230     */
 231    struct iris_resource *res;
 232
 233    /** The resource (BO) holding our SURFACE_STATE. */
 234    struct iris_surface_state surface_state;
 235 };
 236
 237 /**
 238  * Image view representation.
 239  */
 240 struct iris_image_view {
 241    struct pipe_image_view base;
 242
 243    /** The resource (BO) holding our SURFACE_STATE. */
 244    struct iris_surface_state surface_state;
 245 };
 246
 247 /**
 248  * Gallium CSO for surfaces (framebuffer attachments).
 249  *
 250  * A view of a surface that can be bound to a color render target or
 251  * depth/stencil attachment.
 252  */
 253 struct iris_surface {
 254    struct pipe_surface base;
 255    struct isl_view view;
 256    struct isl_view read_view;
 257    union isl_color_value clear_color;
 258
 259    /** The resource (BO) holding our SURFACE_STATE. */
 260    struct iris_surface_state surface_state;
 261    /** The resource (BO) holding our SURFACE_STATE for read. */
 262    struct iris_surface_state surface_state_read;
 263 };
 264
 265 /**
 266  * Transfer object - information about a buffer mapping.
 267  */
 268 struct iris_transfer {
 269    struct pipe_transfer base;
 270    struct pipe_debug_callback *dbg;
 271    void *buffer;
 272    void *ptr;
 273
 274    /** A linear staging resource for GPU-based copy_region transfers. */
 275    struct pipe_resource *staging;
 276    struct blorp_context *blorp;
 277    struct iris_batch *batch;
 278
 279    bool dest_had_defined_contents;
 280
 281    void (*unmap)(struct iris_transfer *);
 282 };
 283
 284 /**
 285  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 286  */
 287 static inline struct iris_bo *
 288 iris_resource_bo(struct pipe_resource *p_res)
 289 {
 290    struct iris_resource *res = (void *) p_res;
 291    return res->bo;
 292 }
 293
 294 static inline uint32_t
 295 iris_mocs(const struct iris_bo *bo, const struct isl_device *dev)
 296 {
 297    return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
 298 }
 299
 300 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 301                                               enum pipe_format pf,
 302                                               isl_surf_usage_flags_t usage);
 303
 304 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 305
 306 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 307                                       struct iris_resource **out_z,
 308                                       struct iris_resource **out_s);
 309 bool iris_resource_set_clear_color(struct iris_context *ice,
 310                                    struct iris_resource *res,
 311                                    union isl_color_value color);
 312 union isl_color_value
 313 iris_resource_get_clear_color(const struct iris_resource *res,
 314                               struct iris_bo **clear_color_bo,
 315                               uint64_t *clear_color_offset);
 316
 317 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 318
 319 void iris_dirty_for_history(struct iris_context *ice,
 320                             struct iris_resource *res);
 321 uint32_t iris_flush_bits_for_history(struct iris_resource *res);
 322
 323 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 324                                       struct iris_batch *batch,
 325                                       struct iris_resource *res,
 326                                       uint32_t extra_flags,
 327                                       const char *reason);
 328
 329 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 330                                      unsigned level);
 331
 332 void iris_resource_disable_aux(struct iris_resource *res);
 333
 334 #define INTEL_REMAINING_LAYERS UINT32_MAX
 335 #define INTEL_REMAINING_LEVELS UINT32_MAX
 336
 337 void
 338 iris_hiz_exec(struct iris_context *ice,
 339               struct iris_batch *batch,
 340               struct iris_resource *res,
 341               unsigned int level, unsigned int start_layer,
 342               unsigned int num_layers, enum isl_aux_op op,
 343               bool update_clear_depth);
 344
 345 /**
 346  * Prepare a miptree for access
 347  *
 348  * This function should be called prior to any access to miptree in order to
 349  * perform any needed resolves.
 350  *
 351  * \param[in]  start_level    The first mip level to be accessed
 352  *
 353  * \param[in]  num_levels     The number of miplevels to be accessed or
 354  *                            INTEL_REMAINING_LEVELS to indicate every level
 355  *                            above start_level will be accessed
 356  *
 357  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 358  *
 359  * \param[in]  num_layers     The number of array slices or 3D layers be
 360  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 361  *                            every layer above start_layer will be accessed
 362  *
 363  * \param[in]  aux_supported  Whether or not the access will support the
 364  *                            miptree's auxiliary compression format;  this
 365  *                            must be false for uncompressed miptrees
 366  *
 367  * \param[in]  fast_clear_supported Whether or not the access will support
 368  *                                  fast clears in the miptree's auxiliary
 369  *                                  compression format
 370  */
 371 void
 372 iris_resource_prepare_access(struct iris_context *ice,
 373                              struct iris_resource *res,
 374                              uint32_t start_level, uint32_t num_levels,
 375                              uint32_t start_layer, uint32_t num_layers,
 376                              enum isl_aux_usage aux_usage,
 377                              bool fast_clear_supported);
 378
 379 /**
 380  * Complete a write operation
 381  *
 382  * This function should be called after any operation writes to a miptree.
 383  * This will update the miptree's compression state so that future resolves
 384  * happen correctly.  Technically, this function can be called before the
 385  * write occurs but the caller must ensure that they don't interlace
 386  * iris_resource_prepare_access and iris_resource_finish_write calls to
 387  * overlapping layer/level ranges.
 388  *
 389  * \param[in]  level             The mip level that was written
 390  *
 391  * \param[in]  start_layer       The first array slice or 3D layer written
 392  *
 393  * \param[in]  num_layers        The number of array slices or 3D layers
 394  *                               written or INTEL_REMAINING_LAYERS to indicate
 395  *                               every layer above start_layer was written
 396  *
 397  * \param[in]  written_with_aux  Whether or not the write was done with
 398  *                               auxiliary compression enabled
 399  */
 400 void
 401 iris_resource_finish_write(struct iris_context *ice,
 402                            struct iris_resource *res, uint32_t level,
 403                            uint32_t start_layer, uint32_t num_layers,
 404                            enum isl_aux_usage aux_usage);
 405
 406 /** Get the auxiliary compression state of a miptree slice */
 407 enum isl_aux_state
 408 iris_resource_get_aux_state(const struct iris_resource *res,
 409                             uint32_t level, uint32_t layer);
 410
 411 /**
 412  * Set the auxiliary compression state of a miptree slice range
 413  *
 414  * This function directly sets the auxiliary compression state of a slice
 415  * range of a miptree.  It only modifies data structures and does not do any
 416  * resolves.  This should only be called by code which directly performs
 417  * compression operations such as fast clears and resolves.  Most code should
 418  * use iris_resource_prepare_access or iris_resource_finish_write.
 419  */
 420 void
 421 iris_resource_set_aux_state(struct iris_context *ice,
 422                             struct iris_resource *res, uint32_t level,
 423                             uint32_t start_layer, uint32_t num_layers,
 424                             enum isl_aux_state aux_state);
 425
 426 /**
 427  * Prepare a miptree for raw access
 428  *
 429  * This helper prepares the miptree for access that knows nothing about any
 430  * sort of compression whatsoever.  This is useful when mapping the surface or
 431  * using it with the blitter.
 432  */
 433 static inline void
 434 iris_resource_access_raw(struct iris_context *ice,
 435                          struct iris_resource *res,
 436                          uint32_t level, uint32_t layer,
 437                          uint32_t num_layers,
 438                          bool write)
 439 {
 440    iris_resource_prepare_access(ice, res, level, 1, layer, num_layers,
 441                                 ISL_AUX_USAGE_NONE, false);
 442    if (write) {
 443       iris_resource_finish_write(ice, res, level, layer, num_layers,
 444                                  ISL_AUX_USAGE_NONE);
 445    }
 446 }
 447
 448 enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
 449                                             enum isl_tiling tiling,
 450                                             enum pipe_texture_target target);
 451 enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
 452 uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
 453                                         uint32_t level, uint32_t z,
 454                                         uint32_t *tile_x, uint32_t *tile_y);
 455 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 456                                                    const struct iris_resource *res,
 457                                                    enum isl_format view_fmt);
 458 void iris_resource_prepare_texture(struct iris_context *ice,
 459                                    struct iris_resource *res,
 460                                    enum isl_format view_format,
 461                                    uint32_t start_level, uint32_t num_levels,
 462                                    uint32_t start_layer, uint32_t num_layers);
 463
 464 enum isl_aux_usage iris_image_view_aux_usage(struct iris_context *ice,
 465                                              const struct pipe_image_view *pview,
 466                                              const struct shader_info *info);
 467 enum isl_format iris_image_view_get_format(struct iris_context *ice,
 468                                            const struct pipe_image_view *img);
 469
 470 static inline bool
 471 iris_resource_unfinished_aux_import(struct iris_resource *res)
 472 {
 473    return res->base.next != NULL && res->mod_info &&
 474       res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
 475 }
 476
 477 void iris_resource_finish_aux_import(struct pipe_screen *pscreen,
 478                                      struct iris_resource *res);
 479
 480 bool iris_has_invalid_primary(const struct iris_resource *res,
 481                               unsigned start_level, unsigned num_levels,
 482                               unsigned start_layer, unsigned num_layers);
 483
 484 void iris_resource_check_level_layer(const struct iris_resource *res,
 485                                      uint32_t level, uint32_t layer);
 486
 487 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 488                                  uint32_t level);
 489
 490 bool iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
 491                                 const struct iris_resource *res);
 492
 493 bool iris_has_color_unresolved(const struct iris_resource *res,
 494                                unsigned start_level, unsigned num_levels,
 495                                unsigned start_layer, unsigned num_layers);
 496
 497 bool iris_render_formats_color_compatible(enum isl_format a,
 498                                           enum isl_format b,
 499                                           union isl_color_value color);
 500 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 501                                                   struct iris_resource *res,
 502                                                   enum isl_format render_fmt,
 503                                                   bool draw_aux_disabled);
 504 void iris_resource_prepare_render(struct iris_context *ice,
 505                                   struct iris_batch *batch,
 506                                   struct iris_resource *res, uint32_t level,
 507                                   uint32_t start_layer, uint32_t layer_count,
 508                                   enum isl_aux_usage aux_usage);
 509 void iris_resource_finish_render(struct iris_context *ice,
 510                                  struct iris_resource *res, uint32_t level,
 511                                  uint32_t start_layer, uint32_t layer_count,
 512                                  enum isl_aux_usage aux_usage);
 513 void iris_resource_prepare_depth(struct iris_context *ice,
 514                                  struct iris_batch *batch,
 515                                  struct iris_resource *res, uint32_t level,
 516                                  uint32_t start_layer, uint32_t layer_count);
 517 void iris_resource_finish_depth(struct iris_context *ice,
 518                                 struct iris_resource *res, uint32_t level,
 519                                 uint32_t start_layer, uint32_t layer_count,
 520                                 bool depth_written);
 521 #endif