src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/format/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "intel/common/gen_l3_config.h"
  57 #include "iris_monitor.h"
  58
  59 static void
  60 iris_flush_frontbuffer(struct pipe_screen *_screen,
  61                        struct pipe_resource *resource,
  62                        unsigned level, unsigned layer,
  63                        void *context_private, struct pipe_box *box)
  64 {
  65 }
  66
  67 static const char *
  68 iris_get_vendor(struct pipe_screen *pscreen)
  69 {
  70    return "Intel";
  71 }
  72
  73 static const char *
  74 iris_get_device_vendor(struct pipe_screen *pscreen)
  75 {
  76    return "Intel";
  77 }
  78
  79 static const char *
  80 iris_get_name(struct pipe_screen *pscreen)
  81 {
  82    struct iris_screen *screen = (struct iris_screen *)pscreen;
  83    static char buf[128];
  84    const char *name = gen_get_device_name(screen->pci_id);
  85
  86    if (!name)
  87       name = "Intel Unknown";
  88
  89    snprintf(buf, sizeof(buf), "Mesa %s", name);
  90    return buf;
  91 }
  92
  93 static int
  94 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  95 {
  96    struct iris_screen *screen = (struct iris_screen *)pscreen;
  97    const struct gen_device_info *devinfo = &screen->devinfo;
  98
  99    switch (param) {
 100    case PIPE_CAP_NPOT_TEXTURES:
 101    case PIPE_CAP_ANISOTROPIC_FILTER:
 102    case PIPE_CAP_POINT_SPRITE:
 103    case PIPE_CAP_OCCLUSION_QUERY:
 104    case PIPE_CAP_QUERY_TIME_ELAPSED:
 105    case PIPE_CAP_TEXTURE_SWIZZLE:
 106    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 107    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 108    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 109    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 110    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 111    case PIPE_CAP_PRIMITIVE_RESTART:
 112    case PIPE_CAP_INDEP_BLEND_ENABLE:
 113    case PIPE_CAP_INDEP_BLEND_FUNC:
 114    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 116    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 120    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 121    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 122    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 123    case PIPE_CAP_CONDITIONAL_RENDER:
 124    case PIPE_CAP_TEXTURE_BARRIER:
 125    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 126    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 127    case PIPE_CAP_COMPUTE:
 128    case PIPE_CAP_START_INSTANCE:
 129    case PIPE_CAP_QUERY_TIMESTAMP:
 130    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 131    case PIPE_CAP_CUBE_MAP_ARRAY:
 132    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 134    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 135    case PIPE_CAP_TEXTURE_QUERY_LOD:
 136    case PIPE_CAP_SAMPLE_SHADING:
 137    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 138    case PIPE_CAP_DRAW_INDIRECT:
 139    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 140    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 141    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 142    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 143    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 144    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 145    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 146    case PIPE_CAP_ACCELERATED:
 147    case PIPE_CAP_UMA:
 148    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 149    case PIPE_CAP_CLIP_HALFZ:
 150    case PIPE_CAP_TGSI_TEXCOORD:
 151    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 152    case PIPE_CAP_DOUBLES:
 153    case PIPE_CAP_INT64:
 154    case PIPE_CAP_INT64_DIVMOD:
 155    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 156    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 157    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 158    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 159    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 160    case PIPE_CAP_CULL_DISTANCE:
 161    case PIPE_CAP_PACKED_UNIFORMS:
 162    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 163    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 164    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 165    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 166    case PIPE_CAP_QUERY_SO_OVERFLOW:
 167    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 168    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 169    case PIPE_CAP_TGSI_TXQS:
 170    case PIPE_CAP_TGSI_CLOCK:
 171    case PIPE_CAP_TGSI_BALLOT:
 172    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 173    case PIPE_CAP_CLEAR_TEXTURE:
 174    case PIPE_CAP_CLEAR_SCISSORED:
 175    case PIPE_CAP_TGSI_VOTE:
 176    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 177    case PIPE_CAP_TEXTURE_GATHER_SM5:
 178    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 179    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 180    case PIPE_CAP_LOAD_CONSTBUF:
 181    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 182    case PIPE_CAP_DRAW_PARAMETERS:
 183    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 184    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 185    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 186    case PIPE_CAP_INVALIDATE_BUFFER:
 187    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 188    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 189    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 190    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 191    case PIPE_CAP_GL_SPIRV:
 192    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
 193    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 194    case PIPE_CAP_NATIVE_FENCE_FD:
 195    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 196       return true;
 197    case PIPE_CAP_FBFETCH:
 198       return BRW_MAX_DRAW_BUFFERS;
 199    case PIPE_CAP_FBFETCH_COHERENT:
 200    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 201    case PIPE_CAP_POST_DEPTH_COVERAGE:
 202    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 203    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 204    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 205    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 206       return devinfo->gen >= 9;
 207    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 208       return devinfo->gen >= 12;
 209    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 210       return 1;
 211    case PIPE_CAP_MAX_RENDER_TARGETS:
 212       return BRW_MAX_DRAW_BUFFERS;
 213    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 214       return 16384;
 215    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 216       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 217    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 218       return 12; /* 2048x2048 */
 219    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 220       return 4;
 221    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 222       return 2048;
 223    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 224       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 225    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 226       return BRW_MAX_SOL_BINDINGS;
 227    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 228    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 229       return 460;
 230    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 231       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 232       return 32;
 233    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 234       return IRIS_MAP_BUFFER_ALIGNMENT;
 235    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 236       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 237        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 238        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 239        * GPU and the CPU can be updating disjoint regions of the buffer
 240        * simultaneously and that will break if the regions overlap the same
 241        * cacheline.
 242        */
 243       return 64;
 244    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 245       return 1 << 27;
 246    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 247       return 16; // XXX: u_screen says 256 is the minimum value...
 248    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 249       return true;
 250    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 251       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 252    case PIPE_CAP_MAX_VIEWPORTS:
 253       return 16;
 254    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 255       return 256;
 256    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 257       return 1024;
 258    case PIPE_CAP_MAX_GS_INVOCATIONS:
 259       return 32;
 260    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 261       return 4;
 262    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 263       return -32;
 264    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 265       return 31;
 266    case PIPE_CAP_MAX_VERTEX_STREAMS:
 267       return 4;
 268    case PIPE_CAP_VENDOR_ID:
 269       return 0x8086;
 270    case PIPE_CAP_DEVICE_ID:
 271       return screen->pci_id;
 272    case PIPE_CAP_VIDEO_MEMORY: {
 273       /* Once a batch uses more than 75% of the maximum mappable size, we
 274        * assume that there's some fragmentation, and we start doing extra
 275        * flushing, etc.  That's the big cliff apps will care about.
 276        */
 277       const unsigned gpu_mappable_megabytes =
 278          (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024);
 279
 280       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 281       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 282
 283       if (system_memory_pages <= 0 || system_page_size <= 0)
 284          return -1;
 285
 286       const uint64_t system_memory_bytes =
 287          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 288
 289       const unsigned system_memory_megabytes =
 290          (unsigned) (system_memory_bytes / (1024 * 1024));
 291
 292       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 293    }
 294    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 295    case PIPE_CAP_MAX_VARYINGS:
 296       return 32;
 297    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 298       /* AMD_pinned_memory assumes the flexibility of using client memory
 299        * for any buffer (incl. vertex buffers) which rules out the prospect
 300        * of using snooped buffers, as using snooped buffers without
 301        * cogniscience is likely to be detrimental to performance and require
 302        * extensive checking in the driver for correctness, e.g. to prevent
 303        * illegal snoop <-> snoop transfers.
 304        */
 305       return devinfo->has_llc;
 306    case PIPE_CAP_THROTTLE:
 307       return screen->driconf.disable_throttling ? 0 : 1;
 308
 309    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 310       return PIPE_CONTEXT_PRIORITY_LOW |
 311              PIPE_CONTEXT_PRIORITY_MEDIUM |
 312              PIPE_CONTEXT_PRIORITY_HIGH;
 313
 314    case PIPE_CAP_FRONTEND_NOOP:
 315       return true;
 316
 317    // XXX: don't hardcode 00:00:02.0 PCI here
 318    case PIPE_CAP_PCI_GROUP:
 319       return 0;
 320    case PIPE_CAP_PCI_BUS:
 321       return 0;
 322    case PIPE_CAP_PCI_DEVICE:
 323       return 2;
 324    case PIPE_CAP_PCI_FUNCTION:
 325       return 0;
 326
 327    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
 328    case PIPE_CAP_INTEGER_MULTIPLY_32X16:
 329       return true;
 330
 331    default:
 332       return u_pipe_screen_get_param_defaults(pscreen, param);
 333    }
 334    return 0;
 335 }
 336
 337 static float
 338 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 339 {
 340    switch (param) {
 341    case PIPE_CAPF_MAX_LINE_WIDTH:
 342    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 343       return 7.375f;
 344
 345    case PIPE_CAPF_MAX_POINT_WIDTH:
 346    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 347       return 255.0f;
 348
 349    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 350       return 16.0f;
 351    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 352       return 15.0f;
 353    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 354    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 355    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 356       return 0.0f;
 357    default:
 358       unreachable("unknown param");
 359    }
 360 }
 361
 362 static int
 363 iris_get_shader_param(struct pipe_screen *pscreen,
 364                       enum pipe_shader_type p_stage,
 365                       enum pipe_shader_cap param)
 366 {
 367    gl_shader_stage stage = stage_from_pipe(p_stage);
 368
 369    /* this is probably not totally correct.. but it's a start: */
 370    switch (param) {
 371    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 372       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 373    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 374    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 375    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 376       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 377
 378    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 379       return UINT_MAX;
 380
 381    case PIPE_SHADER_CAP_MAX_INPUTS:
 382       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 383    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 384       return 32;
 385    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 386       return 16 * 1024 * sizeof(float);
 387    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 388       return 16;
 389    case PIPE_SHADER_CAP_MAX_TEMPS:
 390       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 391    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 392       return 0;
 393    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 394    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 395    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 396    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 397       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 398        * which we don't want.  Our compiler backend will check brw_compiler's
 399        * options and call nir_lower_indirect_derefs appropriately anyway.
 400        */
 401       return true;
 402    case PIPE_SHADER_CAP_SUBROUTINES:
 403       return 0;
 404    case PIPE_SHADER_CAP_INTEGERS:
 405       return 1;
 406    case PIPE_SHADER_CAP_INT64_ATOMICS:
 407    case PIPE_SHADER_CAP_FP16:
 408    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 409    case PIPE_SHADER_CAP_INT16:
 410       return 0;
 411    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 412    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 413    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 414       return IRIS_MAX_TEXTURE_SAMPLERS;
 415    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 416       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 417    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 418    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 419       return 0;
 420    case PIPE_SHADER_CAP_PREFERRED_IR:
 421       return PIPE_SHADER_IR_NIR;
 422    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 423       return 1 << PIPE_SHADER_IR_NIR;
 424    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 425    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 426       return 1;
 427    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 428    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 429    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 431    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 432    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 433    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 434       return 0;
 435    default:
 436       unreachable("unknown shader param");
 437    }
 438 }
 439
 440 static int
 441 iris_get_compute_param(struct pipe_screen *pscreen,
 442                        enum pipe_shader_ir ir_type,
 443                        enum pipe_compute_cap param,
 444                        void *ret)
 445 {
 446    struct iris_screen *screen = (struct iris_screen *)pscreen;
 447    const struct gen_device_info *devinfo = &screen->devinfo;
 448
 449    /* Limit max_threads to 64 for the GPGPU_WALKER command. */
 450    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 451    const uint32_t max_invocations = 32 * max_threads;
 452
 453 #define RET(x) do {                  \
 454    if (ret)                          \
 455       memcpy(ret, x, sizeof(x));     \
 456    return sizeof(x);                 \
 457 } while (0)
 458
 459    switch (param) {
 460    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 461       RET((uint32_t []){ 32 });
 462
 463    case PIPE_COMPUTE_CAP_IR_TARGET:
 464       if (ret)
 465          strcpy(ret, "gen");
 466       return 4;
 467
 468    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 469       RET((uint64_t []) { 3 });
 470
 471    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 472       RET(((uint64_t []) { 65535, 65535, 65535 }));
 473
 474    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 475       /* MaxComputeWorkGroupSize[0..2] */
 476       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 477
 478    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 479       /* MaxComputeWorkGroupInvocations */
 480    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 481       /* MaxComputeVariableGroupInvocations */
 482       RET((uint64_t []) { max_invocations });
 483
 484    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 485       /* MaxComputeSharedMemorySize */
 486       RET((uint64_t []) { 64 * 1024 });
 487
 488    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 489       RET((uint32_t []) { 1 });
 490
 491    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 492       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 493
 494    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 495    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 496    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 497    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 498    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 499    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 500       // XXX: I think these are for Clover...
 501       return 0;
 502
 503    default:
 504       unreachable("unknown compute param");
 505    }
 506 }
 507
 508 static uint64_t
 509 iris_get_timestamp(struct pipe_screen *pscreen)
 510 {
 511    struct iris_screen *screen = (struct iris_screen *) pscreen;
 512    const unsigned TIMESTAMP = 0x2358;
 513    uint64_t result;
 514
 515    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 516
 517    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 518    result &= (1ull << TIMESTAMP_BITS) - 1;
 519
 520    return result;
 521 }
 522
 523 void
 524 iris_screen_destroy(struct iris_screen *screen)
 525 {
 526    iris_bo_unreference(screen->workaround_bo);
 527    u_transfer_helper_destroy(screen->base.transfer_helper);
 528    iris_bufmgr_unref(screen->bufmgr);
 529    disk_cache_destroy(screen->disk_cache);
 530    ralloc_free(screen);
 531 }
 532
 533 static void
 534 iris_screen_unref(struct pipe_screen *pscreen)
 535 {
 536    iris_pscreen_unref(pscreen);
 537 }
 538
 539 static void
 540 iris_query_memory_info(struct pipe_screen *pscreen,
 541                        struct pipe_memory_info *info)
 542 {
 543 }
 544
 545 static const void *
 546 iris_get_compiler_options(struct pipe_screen *pscreen,
 547                           enum pipe_shader_ir ir,
 548                           enum pipe_shader_type pstage)
 549 {
 550    struct iris_screen *screen = (struct iris_screen *) pscreen;
 551    gl_shader_stage stage = stage_from_pipe(pstage);
 552    assert(ir == PIPE_SHADER_IR_NIR);
 553
 554    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 555 }
 556
 557 static struct disk_cache *
 558 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 559 {
 560    struct iris_screen *screen = (struct iris_screen *) pscreen;
 561    return screen->disk_cache;
 562 }
 563
 564 static int
 565 iris_getparam(int fd, int param, int *value)
 566 {
 567    struct drm_i915_getparam gp = { .param = param, .value = value };
 568
 569    if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 570       return -errno;
 571
 572    return 0;
 573 }
 574
 575 static int
 576 iris_getparam_integer(int fd, int param)
 577 {
 578    int value = -1;
 579
 580    if (iris_getparam(fd, param, &value) == 0)
 581       return value;
 582
 583    return -1;
 584 }
 585
 586 static const struct gen_l3_config *
 587 iris_get_default_l3_config(const struct gen_device_info *devinfo,
 588                            bool compute)
 589 {
 590    bool wants_dc_cache = true;
 591    bool has_slm = compute;
 592    const struct gen_l3_weights w =
 593       gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
 594    return gen_get_l3_config(devinfo, w);
 595 }
 596
 597 static void
 598 iris_shader_debug_log(void *data, const char *fmt, ...)
 599 {
 600    struct pipe_debug_callback *dbg = data;
 601    unsigned id = 0;
 602    va_list args;
 603
 604    if (!dbg->debug_message)
 605       return;
 606
 607    va_start(args, fmt);
 608    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 609    va_end(args);
 610 }
 611
 612 static void
 613 iris_shader_perf_log(void *data, const char *fmt, ...)
 614 {
 615    struct pipe_debug_callback *dbg = data;
 616    unsigned id = 0;
 617    va_list args;
 618    va_start(args, fmt);
 619
 620    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 621       va_list args_copy;
 622       va_copy(args_copy, args);
 623       vfprintf(stderr, fmt, args_copy);
 624       va_end(args_copy);
 625    }
 626
 627    if (dbg->debug_message) {
 628       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 629    }
 630
 631    va_end(args);
 632 }
 633
 634 static void
 635 iris_detect_kernel_features(struct iris_screen *screen)
 636 {
 637    /* Kernel 5.2+ */
 638    if (gen_gem_supports_syncobj_wait(screen->fd))
 639       screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
 640 }
 641
 642 static bool
 643 iris_init_identifier_bo(struct iris_screen *screen)
 644 {
 645    void *bo_map;
 646
 647    bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
 648    if (!bo_map)
 649       return false;
 650
 651    screen->workaround_bo->kflags |= EXEC_OBJECT_CAPTURE;
 652    screen->workaround_address = (struct iris_address) {
 653       .bo = screen->workaround_bo,
 654       .offset = ALIGN(
 655          intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8),
 656    };
 657
 658    iris_bo_unmap(screen->workaround_bo);
 659
 660    return true;
 661 }
 662
 663 struct pipe_screen *
 664 iris_screen_create(int fd, const struct pipe_screen_config *config)
 665 {
 666    /* Here are the i915 features we need for Iris (in chronoligical order) :
 667     *    - I915_PARAM_HAS_EXEC_NO_RELOC     (3.10)
 668     *    - I915_PARAM_HAS_EXEC_HANDLE_LUT   (3.10)
 669     *    - I915_PARAM_HAS_EXEC_BATCH_FIRST  (4.13)
 670     *    - I915_PARAM_HAS_EXEC_FENCE_ARRAY  (4.14)
 671     *    - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
 672     *
 673     * Checking the last feature availability will include all previous ones.
 674     */
 675    if (!iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION)) {
 676       debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n");
 677       return NULL;
 678    }
 679
 680    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 681    if (!screen)
 682       return NULL;
 683
 684    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 685       return NULL;
 686    screen->pci_id = screen->devinfo.chipset_id;
 687    screen->no_hw = screen->devinfo.no_hw;
 688
 689    p_atomic_set(&screen->refcount, 1);
 690
 691    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 692       return NULL;
 693
 694    bool bo_reuse = false;
 695    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 696    switch (bo_reuse_mode) {
 697    case DRI_CONF_BO_REUSE_DISABLED:
 698       break;
 699    case DRI_CONF_BO_REUSE_ALL:
 700       bo_reuse = true;
 701       break;
 702    }
 703
 704    screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse);
 705    if (!screen->bufmgr)
 706       return NULL;
 707
 708    screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
 709
 710    if (getenv("INTEL_NO_HW") != NULL)
 711       screen->no_hw = true;
 712
 713    screen->workaround_bo =
 714       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 715    if (!screen->workaround_bo)
 716       return NULL;
 717
 718    if (!iris_init_identifier_bo(screen))
 719       return NULL;
 720
 721    brw_process_intel_debug_variable();
 722
 723    screen->driconf.dual_color_blend_by_location =
 724       driQueryOptionb(config->options, "dual_color_blend_by_location");
 725    screen->driconf.disable_throttling =
 726       driQueryOptionb(config->options, "disable_throttling");
 727    screen->driconf.always_flush_cache =
 728       driQueryOptionb(config->options, "always_flush_cache");
 729
 730    screen->precompile = env_var_as_boolean("shader_precompile", true);
 731
 732    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 733
 734    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 735    screen->compiler->shader_debug_log = iris_shader_debug_log;
 736    screen->compiler->shader_perf_log = iris_shader_perf_log;
 737    screen->compiler->supports_pull_constants = false;
 738    screen->compiler->supports_shader_constants = true;
 739    screen->compiler->compact_params = false;
 740
 741    screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
 742    screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
 743
 744    iris_disk_cache_init(screen);
 745
 746    slab_create_parent(&screen->transfer_pool,
 747                       sizeof(struct iris_transfer), 64);
 748
 749    screen->subslice_total =
 750       iris_getparam_integer(screen->fd, I915_PARAM_SUBSLICE_TOTAL);
 751    assert(screen->subslice_total >= 1);
 752
 753    iris_detect_kernel_features(screen);
 754
 755    struct pipe_screen *pscreen = &screen->base;
 756
 757    iris_init_screen_fence_functions(pscreen);
 758    iris_init_screen_resource_functions(pscreen);
 759
 760    pscreen->destroy = iris_screen_unref;
 761    pscreen->get_name = iris_get_name;
 762    pscreen->get_vendor = iris_get_vendor;
 763    pscreen->get_device_vendor = iris_get_device_vendor;
 764    pscreen->get_param = iris_get_param;
 765    pscreen->get_shader_param = iris_get_shader_param;
 766    pscreen->get_compute_param = iris_get_compute_param;
 767    pscreen->get_paramf = iris_get_paramf;
 768    pscreen->get_compiler_options = iris_get_compiler_options;
 769    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 770    pscreen->is_format_supported = iris_is_format_supported;
 771    pscreen->context_create = iris_create_context;
 772    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 773    pscreen->get_timestamp = iris_get_timestamp;
 774    pscreen->query_memory_info = iris_query_memory_info;
 775    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 776    pscreen->get_driver_query_info = iris_get_monitor_info;
 777
 778    return pscreen;
 779 }