src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include <sys/ioctl.h>
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_state.h"
  28 #include "pipe/p_context.h"
  29 #include "pipe/p_screen.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_format.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "util/ralloc.h"
  34 #include "drm-uapi/i915_drm.h"
  35 #include "iris_context.h"
  36 #include "iris_resource.h"
  37 #include "iris_screen.h"
  38 #include "intel/compiler/brw_compiler.h"
  39
  40 static void
  41 iris_flush_frontbuffer(struct pipe_screen *_screen,
  42                        struct pipe_resource *resource,
  43                        unsigned level, unsigned layer,
  44                        void *context_private, struct pipe_box *box)
  45 {
  46 }
  47
  48 static const char *
  49 iris_get_vendor(struct pipe_screen *pscreen)
  50 {
  51    return "Mesa Project";
  52 }
  53
  54 static const char *
  55 iris_get_device_vendor(struct pipe_screen *pscreen)
  56 {
  57    return "Intel";
  58 }
  59
  60 static const char *
  61 iris_get_name(struct pipe_screen *pscreen)
  62 {
  63    struct iris_screen *screen = (struct iris_screen *)pscreen;
  64    const char *chipset;
  65
  66    switch (screen->pci_id) {
  67 #undef CHIPSET
  68 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  69 #include "pci_ids/i965_pci_ids.h"
  70    default:
  71       chipset = "Unknown Intel Chipset";
  72       break;
  73    }
  74    return &chipset[9];
  75 }
  76
  77 static int
  78 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  79 {
  80    struct iris_screen *screen = (struct iris_screen *)pscreen;
  81
  82    switch (param) {
  83    case PIPE_CAP_NPOT_TEXTURES:
  84    case PIPE_CAP_ANISOTROPIC_FILTER:
  85    case PIPE_CAP_POINT_SPRITE:
  86    case PIPE_CAP_OCCLUSION_QUERY:
  87    case PIPE_CAP_QUERY_TIME_ELAPSED:
  88    case PIPE_CAP_TEXTURE_SWIZZLE:
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_SM3:
  92    case PIPE_CAP_PRIMITIVE_RESTART:
  93    case PIPE_CAP_INDEP_BLEND_ENABLE:
  94    case PIPE_CAP_INDEP_BLEND_FUNC:
  95    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
  96    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  97    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  98    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  99    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 100    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 101    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 102    case PIPE_CAP_TGSI_INSTANCEID:
 103    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 104    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 105    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 106    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 107    case PIPE_CAP_CONDITIONAL_RENDER:
 108    case PIPE_CAP_TEXTURE_BARRIER:
 109    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 110    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 111    case PIPE_CAP_COMPUTE:
 112    case PIPE_CAP_START_INSTANCE:
 113    case PIPE_CAP_QUERY_TIMESTAMP:
 114    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 115    case PIPE_CAP_CUBE_MAP_ARRAY:
 116    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 117    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 118    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 119    case PIPE_CAP_TEXTURE_QUERY_LOD:
 120    case PIPE_CAP_SAMPLE_SHADING:
 121    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 122    case PIPE_CAP_DRAW_INDIRECT:
 123    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 124    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 125    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 126    case PIPE_CAP_ACCELERATED:
 127    case PIPE_CAP_UMA:
 128    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 129    case PIPE_CAP_CLIP_HALFZ:
 130       return true;
 131
 132    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 133    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 134    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 135    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 136    case PIPE_CAP_USER_VERTEX_BUFFERS:
 137    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 141    case PIPE_CAP_TGSI_TEXCOORD:
 142    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 143    case PIPE_CAP_FAKE_SW_MSAA:
 144    case PIPE_CAP_VERTEXID_NOBASE:
 145       return false;
 146
 147    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 148       return 1;
 149    case PIPE_CAP_MAX_RENDER_TARGETS:
 150       return BRW_MAX_DRAW_BUFFERS;
 151    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 152    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 153       return 15; /* 16384x16384 */
 154    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 155       return 12; /* 2048x2048 */
 156    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 157       return 4;
 158    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 159       return 2048;
 160    case PIPE_CAP_MIN_TEXEL_OFFSET:
 161       return -8;
 162    case PIPE_CAP_MAX_TEXEL_OFFSET:
 163       return 7;
 164    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 165       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 166    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 167       return BRW_MAX_SOL_BINDINGS;
 168    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 169       return 460;
 170    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 171       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 172       return 32;
 173    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 174       return 64; // XXX: ?
 175    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 176       return 1;
 177    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 178       return true; // XXX: ?????
 179    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 180       return 1 << 27; /* 128MB */
 181    case PIPE_CAP_MAX_VIEWPORTS:
 182       return 16;
 183    case PIPE_CAP_ENDIANNESS:
 184       return PIPE_ENDIAN_LITTLE;
 185    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 186       return 256;
 187    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 188       return 128;
 189    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 190    case PIPE_CAP_TEXTURE_GATHER_SM5:
 191       return 0; // XXX:
 192    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 193       return -32;
 194    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 195       return 31;
 196    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 197    case PIPE_CAP_MAX_VERTEX_STREAMS:
 198       return 4;
 199    case PIPE_CAP_VENDOR_ID:
 200       return 0x8086;
 201    case PIPE_CAP_DEVICE_ID:
 202       return screen->pci_id;
 203    case PIPE_CAP_VIDEO_MEMORY:
 204       return 0xffffffff; // XXX: bogus
 205    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 206       return 2048;
 207    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 208       return false; // XXX: what is this?
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 213    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 214    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 215    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 217    case PIPE_CAP_TGSI_TXQS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 221    case PIPE_CAP_CLEAR_TEXTURE:
 222    case PIPE_CAP_DRAW_PARAMETERS:
 223    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 226    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 227    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 229    case PIPE_CAP_INVALIDATE_BUFFER:
 230    case PIPE_CAP_GENERATE_MIPMAP:
 231    case PIPE_CAP_STRING_MARKER:
 232    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 233    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234    case PIPE_CAP_QUERY_MEMORY_INFO:
 235    case PIPE_CAP_PCI_GROUP:
 236    case PIPE_CAP_PCI_BUS:
 237    case PIPE_CAP_PCI_DEVICE:
 238    case PIPE_CAP_PCI_FUNCTION:
 239    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 240    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 241    case PIPE_CAP_CULL_DISTANCE:
 242    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 243    case PIPE_CAP_TGSI_VOTE:
 244    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 245    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 246    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 247    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 248    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 249    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 250    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 251    case PIPE_CAP_NATIVE_FENCE_FD:
 252    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 253    case PIPE_CAP_TGSI_FS_FBFETCH:
 254    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 255    case PIPE_CAP_DOUBLES:
 256    case PIPE_CAP_INT64:
 257    case PIPE_CAP_INT64_DIVMOD:
 258    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 259    case PIPE_CAP_TGSI_CLOCK:
 260    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 261    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 262    case PIPE_CAP_TGSI_BALLOT:
 263    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 264    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 265    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 266    case PIPE_CAP_POST_DEPTH_COVERAGE:
 267    case PIPE_CAP_BINDLESS_TEXTURE:
 268    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 269    case PIPE_CAP_QUERY_SO_OVERFLOW:
 270    case PIPE_CAP_MEMOBJ:
 271    case PIPE_CAP_LOAD_CONSTBUF:
 272    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 273    case PIPE_CAP_TILE_RASTER_ORDER:
 274    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 275    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 276    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 277       // XXX: TODO: fill these out
 278       break;
 279    }
 280    return 0;
 281 }
 282
 283 static float
 284 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 285 {
 286    switch (param) {
 287    case PIPE_CAPF_MAX_LINE_WIDTH:
 288    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 289       return 7.375f;
 290
 291    case PIPE_CAPF_MAX_POINT_WIDTH:
 292    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 293       return 255.0f;
 294
 295    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 296       return 16.0f;
 297    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 298       return 15.0f;
 299    default:
 300       unreachable("unknown param");
 301    }
 302 }
 303
 304 static int
 305 iris_get_shader_param(struct pipe_screen *pscreen,
 306                       enum pipe_shader_type shader,
 307                       enum pipe_shader_cap param)
 308 {
 309    struct iris_screen *screen = (struct iris_screen *)pscreen;
 310    struct brw_compiler *compiler = screen->compiler;
 311
 312    /* this is probably not totally correct.. but it's a start: */
 313    switch (param) {
 314    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 315       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 16384;
 316    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 317    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 318    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 319       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 0;
 320
 321    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 322       return UINT_MAX;
 323
 324    case PIPE_SHADER_CAP_MAX_INPUTS:
 325       return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 326    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 327       return 32;
 328    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 329       return 16 * 1024 * sizeof(float);
 330    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 331       return 16;
 332    case PIPE_SHADER_CAP_MAX_TEMPS:
 333       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 334    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 335       return 0;
 336    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 337       return !compiler->glsl_compiler_options[shader].EmitNoIndirectInput;
 338    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 339       return !compiler->glsl_compiler_options[shader].EmitNoIndirectOutput;
 340    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 341       return !compiler->glsl_compiler_options[shader].EmitNoIndirectTemp;
 342    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 343       return 1;
 344    case PIPE_SHADER_CAP_SUBROUTINES:
 345       return 0;
 346    case PIPE_SHADER_CAP_INTEGERS:
 347    case PIPE_SHADER_CAP_SCALAR_ISA:
 348       return 1;
 349    case PIPE_SHADER_CAP_INT64_ATOMICS:
 350    case PIPE_SHADER_CAP_FP16:
 351       return 0;
 352    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 353    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 354    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 355    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 356       return IRIS_MAX_TEXTURE_SAMPLERS;
 357    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 358    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 359       return 0;
 360    case PIPE_SHADER_CAP_PREFERRED_IR:
 361       return PIPE_SHADER_IR_NIR;
 362    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 363       return 0;
 364    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 365       return 32;
 366    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 367    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 368    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 369    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 370    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 371    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 372    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 373    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 374       return 0;
 375    default:
 376       unreachable("unknown shader param");
 377    }
 378 }
 379
 380 static int
 381 iris_get_compute_param(struct pipe_screen *pscreen,
 382                        enum pipe_shader_ir ir_type,
 383                        enum pipe_compute_cap param,
 384                        void *ret)
 385 {
 386    /* TODO: compute shaders */
 387    return 0;
 388 }
 389
 390 static uint64_t
 391 iris_get_timestamp(struct pipe_screen *pscreen)
 392 {
 393    return 0;
 394 }
 395
 396 static void
 397 iris_destroy_screen(struct pipe_screen *pscreen)
 398 {
 399    struct iris_screen *screen = (struct iris_screen *) pscreen;
 400    ralloc_free(screen);
 401 }
 402
 403 static void
 404 iris_fence_reference(struct pipe_screen *screen,
 405                      struct pipe_fence_handle **ptr,
 406                      struct pipe_fence_handle *fence)
 407 {
 408 }
 409
 410 static boolean
 411 iris_fence_finish(struct pipe_screen *screen,
 412                   struct pipe_context *ctx,
 413                   struct pipe_fence_handle *fence,
 414                   uint64_t timeout)
 415 {
 416    return true;
 417 }
 418
 419 static void
 420 iris_query_memory_info(struct pipe_screen *pscreen,
 421                        struct pipe_memory_info *info)
 422 {
 423 }
 424
 425 static gl_shader_stage
 426 stage_from_pipe(enum pipe_shader_type pstage)
 427 {
 428    static const gl_shader_stage stages[PIPE_SHADER_TYPES] = {
 429       [PIPE_SHADER_VERTEX] = MESA_SHADER_VERTEX,
 430       [PIPE_SHADER_TESS_CTRL] = MESA_SHADER_TESS_CTRL,
 431       [PIPE_SHADER_TESS_EVAL] = MESA_SHADER_TESS_EVAL,
 432       [PIPE_SHADER_GEOMETRY] = MESA_SHADER_GEOMETRY,
 433       [PIPE_SHADER_FRAGMENT] = MESA_SHADER_FRAGMENT,
 434       [PIPE_SHADER_COMPUTE] = MESA_SHADER_COMPUTE,
 435    };
 436    return stages[pstage];
 437 }
 438
 439 static const void *
 440 iris_get_compiler_options(struct pipe_screen *pscreen,
 441                           enum pipe_shader_ir ir,
 442                           enum pipe_shader_type pstage)
 443 {
 444    struct iris_screen *screen = (struct iris_screen *) pscreen;
 445    gl_shader_stage stage = stage_from_pipe(pstage);
 446    assert(ir == PIPE_SHADER_IR_NIR);
 447
 448    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 449 }
 450
 451 static int
 452 iris_getparam(struct iris_screen *screen, int param, int *value)
 453 {
 454    struct drm_i915_getparam gp = { .param = param, .value = value };
 455
 456    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 457       return -errno;
 458
 459    return 0;
 460 }
 461
 462 static bool
 463 iris_getparam_boolean(struct iris_screen *screen, int param)
 464 {
 465    int value = 0;
 466    return (iris_getparam(screen, param, &value) == 0) && value;
 467 }
 468
 469 static int
 470 iris_getparam_integer(struct iris_screen *screen, int param)
 471 {
 472    int value = -1;
 473
 474    if (iris_getparam(screen, param, &value) == 0)
 475       return value;
 476
 477    return -1;
 478 }
 479
 480 struct pipe_screen *
 481 iris_screen_create(int fd)
 482 {
 483    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 484    if (!screen)
 485       return NULL;
 486
 487    screen->fd = fd;
 488    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 489
 490    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 491       return NULL;
 492
 493    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 494    if (!screen->bufmgr)
 495       return NULL;
 496
 497    bool hw_has_swizzling = false; // XXX: detect?
 498    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 499
 500    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 501
 502    struct pipe_screen *pscreen = &screen->base;
 503
 504    iris_init_screen_resource_functions(pscreen);
 505
 506    pscreen->destroy = iris_destroy_screen;
 507    pscreen->get_name = iris_get_name;
 508    pscreen->get_vendor = iris_get_vendor;
 509    pscreen->get_device_vendor = iris_get_device_vendor;
 510    pscreen->get_param = iris_get_param;
 511    pscreen->get_shader_param = iris_get_shader_param;
 512    pscreen->get_compute_param = iris_get_compute_param;
 513    pscreen->get_paramf = iris_get_paramf;
 514    pscreen->get_compiler_options = iris_get_compiler_options;
 515    pscreen->is_format_supported = iris_is_format_supported;
 516    pscreen->context_create = iris_create_context;
 517    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 518    pscreen->get_timestamp = iris_get_timestamp;
 519    pscreen->fence_reference = iris_fence_reference;
 520    pscreen->fence_finish = iris_fence_finish;
 521    pscreen->query_memory_info = iris_query_memory_info;
 522
 523    return pscreen;
 524 }