2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Screen related driver hooks and capability lists.
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/debug.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "util/xmlconfig.h"
47 #include "drm-uapi/i915_drm.h"
48 #include "iris_context.h"
49 #include "iris_defines.h"
50 #include "iris_fence.h"
51 #include "iris_pipe.h"
52 #include "iris_resource.h"
53 #include "iris_screen.h"
54 #include "intel/compiler/brw_compiler.h"
55 #include "intel/common/gen_gem.h"
56 #include "iris_monitor.h"
59 iris_flush_frontbuffer(struct pipe_screen
*_screen
,
60 struct pipe_resource
*resource
,
61 unsigned level
, unsigned layer
,
62 void *context_private
, struct pipe_box
*box
)
67 iris_get_vendor(struct pipe_screen
*pscreen
)
73 iris_get_device_vendor(struct pipe_screen
*pscreen
)
79 iris_get_name(struct pipe_screen
*pscreen
)
81 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
85 switch (screen
->pci_id
) {
87 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
88 #include "pci_ids/i965_pci_ids.h"
89 #include "pci_ids/iris_pci_ids.h"
91 chipset
= "Unknown Intel Chipset";
95 snprintf(buf
, sizeof(buf
), "Mesa %s", chipset
);
100 get_aperture_size(int fd
)
102 struct drm_i915_gem_get_aperture aperture
= {};
103 gen_ioctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
);
104 return aperture
.aper_size
;
108 iris_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
110 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
111 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
114 case PIPE_CAP_NPOT_TEXTURES
:
115 case PIPE_CAP_ANISOTROPIC_FILTER
:
116 case PIPE_CAP_POINT_SPRITE
:
117 case PIPE_CAP_OCCLUSION_QUERY
:
118 case PIPE_CAP_QUERY_TIME_ELAPSED
:
119 case PIPE_CAP_TEXTURE_SWIZZLE
:
120 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
121 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
122 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
123 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
124 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
125 case PIPE_CAP_PRIMITIVE_RESTART
:
126 case PIPE_CAP_INDEP_BLEND_ENABLE
:
127 case PIPE_CAP_INDEP_BLEND_FUNC
:
128 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
129 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
130 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
131 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
132 case PIPE_CAP_TGSI_INSTANCEID
:
133 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
134 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
135 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
137 case PIPE_CAP_CONDITIONAL_RENDER
:
138 case PIPE_CAP_TEXTURE_BARRIER
:
139 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
140 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
141 case PIPE_CAP_COMPUTE
:
142 case PIPE_CAP_START_INSTANCE
:
143 case PIPE_CAP_QUERY_TIMESTAMP
:
144 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
145 case PIPE_CAP_CUBE_MAP_ARRAY
:
146 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
147 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE
:
148 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
149 case PIPE_CAP_TEXTURE_QUERY_LOD
:
150 case PIPE_CAP_SAMPLE_SHADING
:
151 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
152 case PIPE_CAP_DRAW_INDIRECT
:
153 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
154 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
155 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
156 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
157 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
158 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
159 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
160 case PIPE_CAP_ACCELERATED
:
162 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
163 case PIPE_CAP_CLIP_HALFZ
:
164 case PIPE_CAP_TGSI_TEXCOORD
:
165 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
166 case PIPE_CAP_DOUBLES
:
168 case PIPE_CAP_INT64_DIVMOD
:
169 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
170 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
171 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
172 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
173 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
174 case PIPE_CAP_CULL_DISTANCE
:
175 case PIPE_CAP_PACKED_UNIFORMS
:
176 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
177 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
178 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
179 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
180 case PIPE_CAP_QUERY_SO_OVERFLOW
:
181 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
182 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
183 case PIPE_CAP_TGSI_TXQS
:
184 case PIPE_CAP_TGSI_CLOCK
:
185 case PIPE_CAP_TGSI_BALLOT
:
186 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
187 case PIPE_CAP_CLEAR_TEXTURE
:
188 case PIPE_CAP_TGSI_VOTE
:
189 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
190 case PIPE_CAP_TEXTURE_GATHER_SM5
:
191 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
192 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
193 case PIPE_CAP_LOAD_CONSTBUF
:
194 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
195 case PIPE_CAP_DRAW_PARAMETERS
:
196 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
197 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
198 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES
:
199 case PIPE_CAP_INVALIDATE_BUFFER
:
200 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
201 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED
:
202 case PIPE_CAP_TEXTURE_SHADOW_LOD
:
203 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
204 case PIPE_CAP_GL_SPIRV
:
205 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS
:
206 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION
:
208 case PIPE_CAP_FBFETCH
:
209 return BRW_MAX_DRAW_BUFFERS
;
210 case PIPE_CAP_FBFETCH_COHERENT
:
211 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE
:
212 case PIPE_CAP_POST_DEPTH_COVERAGE
:
213 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
214 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
215 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK
:
216 case PIPE_CAP_ATOMIC_FLOAT_MINMAX
:
217 return devinfo
->gen
>= 9;
218 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
220 case PIPE_CAP_MAX_RENDER_TARGETS
:
221 return BRW_MAX_DRAW_BUFFERS
;
222 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
224 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
225 return IRIS_MAX_MIPLEVELS
; /* 16384x16384 */
226 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
227 return 12; /* 2048x2048 */
228 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
230 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
232 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
233 return BRW_MAX_SOL_BINDINGS
/ IRIS_MAX_SOL_BUFFERS
;
234 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
235 return BRW_MAX_SOL_BINDINGS
;
236 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
237 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
239 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
240 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
242 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
243 return IRIS_MAP_BUFFER_ALIGNMENT
;
244 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
245 /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
246 * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
247 * UBOs, the GPU never writes, so there's no problem. For an SSBO, the
248 * GPU and the CPU can be updating disjoint regions of the buffer
249 * simultaneously and that will break if the regions overlap the same
253 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
255 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
256 return 16; // XXX: u_screen says 256 is the minimum value...
257 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
259 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
260 return IRIS_MAX_TEXTURE_BUFFER_SIZE
;
261 case PIPE_CAP_MAX_VIEWPORTS
:
263 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
265 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
267 case PIPE_CAP_MAX_GS_INVOCATIONS
:
269 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
271 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
273 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
275 case PIPE_CAP_MAX_VERTEX_STREAMS
:
277 case PIPE_CAP_VENDOR_ID
:
279 case PIPE_CAP_DEVICE_ID
:
280 return screen
->pci_id
;
281 case PIPE_CAP_VIDEO_MEMORY
: {
282 /* Once a batch uses more than 75% of the maximum mappable size, we
283 * assume that there's some fragmentation, and we start doing extra
284 * flushing, etc. That's the big cliff apps will care about.
286 const unsigned gpu_mappable_megabytes
=
287 (screen
->aperture_bytes
* 3 / 4) / (1024 * 1024);
289 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
290 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
292 if (system_memory_pages
<= 0 || system_page_size
<= 0)
295 const uint64_t system_memory_bytes
=
296 (uint64_t) system_memory_pages
* (uint64_t) system_page_size
;
298 const unsigned system_memory_megabytes
=
299 (unsigned) (system_memory_bytes
/ (1024 * 1024));
301 return MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
303 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
304 case PIPE_CAP_MAX_VARYINGS
:
306 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
307 /* AMD_pinned_memory assumes the flexibility of using client memory
308 * for any buffer (incl. vertex buffers) which rules out the prospect
309 * of using snooped buffers, as using snooped buffers without
310 * cogniscience is likely to be detrimental to performance and require
311 * extensive checking in the driver for correctness, e.g. to prevent
312 * illegal snoop <-> snoop transfers.
314 return devinfo
->has_llc
;
315 case PIPE_CAP_THROTTLE
:
316 return screen
->driconf
.disable_throttling
? 0 : 1;
318 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
319 return PIPE_CONTEXT_PRIORITY_LOW
|
320 PIPE_CONTEXT_PRIORITY_MEDIUM
|
321 PIPE_CONTEXT_PRIORITY_HIGH
;
323 // XXX: don't hardcode 00:00:02.0 PCI here
324 case PIPE_CAP_PCI_GROUP
:
326 case PIPE_CAP_PCI_BUS
:
328 case PIPE_CAP_PCI_DEVICE
:
330 case PIPE_CAP_PCI_FUNCTION
:
334 return u_pipe_screen_get_param_defaults(pscreen
, param
);
340 iris_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
343 case PIPE_CAPF_MAX_LINE_WIDTH
:
344 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
347 case PIPE_CAPF_MAX_POINT_WIDTH
:
348 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
351 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
353 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
355 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
356 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
357 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
360 unreachable("unknown param");
365 iris_get_shader_param(struct pipe_screen
*pscreen
,
366 enum pipe_shader_type p_stage
,
367 enum pipe_shader_cap param
)
369 gl_shader_stage stage
= stage_from_pipe(p_stage
);
371 /* this is probably not totally correct.. but it's a start: */
373 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
374 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 16384;
375 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
376 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
377 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
378 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 0;
380 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
383 case PIPE_SHADER_CAP_MAX_INPUTS
:
384 return stage
== MESA_SHADER_VERTEX
? 16 : 32;
385 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
387 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
388 return 16 * 1024 * sizeof(float);
389 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
391 case PIPE_SHADER_CAP_MAX_TEMPS
:
392 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
393 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
395 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
396 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
397 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
398 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
399 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
400 * which we don't want. Our compiler backend will check brw_compiler's
401 * options and call nir_lower_indirect_derefs appropriately anyway.
404 case PIPE_SHADER_CAP_SUBROUTINES
:
406 case PIPE_SHADER_CAP_INTEGERS
:
408 case PIPE_SHADER_CAP_INT64_ATOMICS
:
409 case PIPE_SHADER_CAP_FP16
:
411 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
412 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
413 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
414 return IRIS_MAX_TEXTURE_SAMPLERS
;
415 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
416 return IRIS_MAX_ABOS
+ IRIS_MAX_SSBOS
;
417 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
418 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
420 case PIPE_SHADER_CAP_PREFERRED_IR
:
421 return PIPE_SHADER_IR_NIR
;
422 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
423 return 1 << PIPE_SHADER_IR_NIR
;
424 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
425 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
427 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
428 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
429 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
430 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
431 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
432 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
433 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
436 unreachable("unknown shader param");
441 iris_get_compute_param(struct pipe_screen
*pscreen
,
442 enum pipe_shader_ir ir_type
,
443 enum pipe_compute_cap param
,
446 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
447 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
449 const unsigned max_threads
= MIN2(64, devinfo
->max_cs_threads
);
450 const uint32_t max_invocations
= 32 * max_threads
;
452 #define RET(x) do { \
454 memcpy(ret, x, sizeof(x)); \
459 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
460 RET((uint32_t []){ 32 });
462 case PIPE_COMPUTE_CAP_IR_TARGET
:
467 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
468 RET((uint64_t []) { 3 });
470 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
471 RET(((uint64_t []) { 65535, 65535, 65535 }));
473 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
474 /* MaxComputeWorkGroupSize[0..2] */
475 RET(((uint64_t []) {max_invocations
, max_invocations
, max_invocations
}));
477 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
478 /* MaxComputeWorkGroupInvocations */
479 RET((uint64_t []) { max_invocations
});
481 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
482 /* MaxComputeSharedMemorySize */
483 RET((uint64_t []) { 64 * 1024 });
485 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
486 RET((uint32_t []) { 1 });
488 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
489 RET((uint32_t []) { BRW_SUBGROUP_SIZE
});
491 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
492 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
493 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
494 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
495 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
496 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
497 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
498 // XXX: I think these are for Clover...
502 unreachable("unknown compute param");
507 iris_get_timestamp(struct pipe_screen
*pscreen
)
509 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
510 const unsigned TIMESTAMP
= 0x2358;
513 iris_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &result
);
515 result
= gen_device_info_timebase_scale(&screen
->devinfo
, result
);
516 result
&= (1ull << TIMESTAMP_BITS
) - 1;
522 iris_destroy_screen(struct pipe_screen
*pscreen
)
524 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
525 iris_bo_unreference(screen
->workaround_bo
);
526 u_transfer_helper_destroy(pscreen
->transfer_helper
);
527 iris_bufmgr_destroy(screen
->bufmgr
);
528 disk_cache_destroy(screen
->disk_cache
);
534 iris_query_memory_info(struct pipe_screen
*pscreen
,
535 struct pipe_memory_info
*info
)
540 iris_get_compiler_options(struct pipe_screen
*pscreen
,
541 enum pipe_shader_ir ir
,
542 enum pipe_shader_type pstage
)
544 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
545 gl_shader_stage stage
= stage_from_pipe(pstage
);
546 assert(ir
== PIPE_SHADER_IR_NIR
);
548 return screen
->compiler
->glsl_compiler_options
[stage
].NirOptions
;
551 static struct disk_cache
*
552 iris_get_disk_shader_cache(struct pipe_screen
*pscreen
)
554 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
555 return screen
->disk_cache
;
559 iris_getparam(struct iris_screen
*screen
, int param
, int *value
)
561 struct drm_i915_getparam gp
= { .param
= param
, .value
= value
};
563 if (ioctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1)
570 iris_getparam_integer(struct iris_screen
*screen
, int param
)
574 if (iris_getparam(screen
, param
, &value
) == 0)
581 iris_shader_debug_log(void *data
, const char *fmt
, ...)
583 struct pipe_debug_callback
*dbg
= data
;
587 if (!dbg
->debug_message
)
591 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_SHADER_INFO
, fmt
, args
);
596 iris_shader_perf_log(void *data
, const char *fmt
, ...)
598 struct pipe_debug_callback
*dbg
= data
;
603 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
605 va_copy(args_copy
, args
);
606 vfprintf(stderr
, fmt
, args_copy
);
610 if (dbg
->debug_message
) {
611 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_PERF_INFO
, fmt
, args
);
618 iris_screen_create(int fd
, const struct pipe_screen_config
*config
)
620 struct iris_screen
*screen
= rzalloc(NULL
, struct iris_screen
);
626 if (!gen_get_device_info_from_fd(fd
, &screen
->devinfo
))
628 screen
->pci_id
= screen
->devinfo
.chipset_id
;
629 screen
->no_hw
= screen
->devinfo
.no_hw
;
631 if (screen
->devinfo
.gen
< 8 || screen
->devinfo
.is_cherryview
)
634 screen
->aperture_bytes
= get_aperture_size(fd
);
636 if (getenv("INTEL_NO_HW") != NULL
)
637 screen
->no_hw
= true;
639 bool bo_reuse
= false;
640 int bo_reuse_mode
= driQueryOptioni(config
->options
, "bo_reuse");
641 switch (bo_reuse_mode
) {
642 case DRI_CONF_BO_REUSE_DISABLED
:
644 case DRI_CONF_BO_REUSE_ALL
:
649 screen
->bufmgr
= iris_bufmgr_init(&screen
->devinfo
, fd
, bo_reuse
);
653 screen
->workaround_bo
=
654 iris_bo_alloc(screen
->bufmgr
, "workaround", 4096, IRIS_MEMZONE_OTHER
);
655 if (!screen
->workaround_bo
)
658 brw_process_intel_debug_variable();
660 screen
->driconf
.dual_color_blend_by_location
=
661 driQueryOptionb(config
->options
, "dual_color_blend_by_location");
662 screen
->driconf
.disable_throttling
=
663 driQueryOptionb(config
->options
, "disable_throttling");
664 screen
->driconf
.always_flush_cache
=
665 driQueryOptionb(config
->options
, "always_flush_cache");
667 screen
->precompile
= env_var_as_boolean("shader_precompile", true);
669 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
, false);
671 screen
->compiler
= brw_compiler_create(screen
, &screen
->devinfo
);
672 screen
->compiler
->shader_debug_log
= iris_shader_debug_log
;
673 screen
->compiler
->shader_perf_log
= iris_shader_perf_log
;
674 screen
->compiler
->supports_pull_constants
= false;
675 screen
->compiler
->supports_shader_constants
= true;
677 iris_disk_cache_init(screen
);
679 slab_create_parent(&screen
->transfer_pool
,
680 sizeof(struct iris_transfer
), 64);
682 screen
->subslice_total
=
683 iris_getparam_integer(screen
, I915_PARAM_SUBSLICE_TOTAL
);
684 assert(screen
->subslice_total
>= 1);
686 struct pipe_screen
*pscreen
= &screen
->base
;
688 iris_init_screen_fence_functions(pscreen
);
689 iris_init_screen_resource_functions(pscreen
);
691 pscreen
->destroy
= iris_destroy_screen
;
692 pscreen
->get_name
= iris_get_name
;
693 pscreen
->get_vendor
= iris_get_vendor
;
694 pscreen
->get_device_vendor
= iris_get_device_vendor
;
695 pscreen
->get_param
= iris_get_param
;
696 pscreen
->get_shader_param
= iris_get_shader_param
;
697 pscreen
->get_compute_param
= iris_get_compute_param
;
698 pscreen
->get_paramf
= iris_get_paramf
;
699 pscreen
->get_compiler_options
= iris_get_compiler_options
;
700 pscreen
->get_disk_shader_cache
= iris_get_disk_shader_cache
;
701 pscreen
->is_format_supported
= iris_is_format_supported
;
702 pscreen
->context_create
= iris_create_context
;
703 pscreen
->flush_frontbuffer
= iris_flush_frontbuffer
;
704 pscreen
->get_timestamp
= iris_get_timestamp
;
705 pscreen
->query_memory_info
= iris_query_memory_info
;
706 pscreen
->get_driver_query_group_info
= iris_get_monitor_group_info
;
707 pscreen
->get_driver_query_info
= iris_get_monitor_info
;